On Sat, Apr 23, 2022, 11:40 AM ron minnich wrote:
> On Fri, Apr 22, 2022 at 11:59 PM Karl Semich <0xl...@gmail.com> wrote:
> >>
> >> We are deprecating ALL boards on oreboot that need FSP, as we took the
> >> decision a few weeks ago to drop boards
> >> that require blobs on the main CPU (we're a
Hi,
Observing ACPI on my new ryzen machine it seems its UEFI can generate the state
of PS/2 mouse and keyboard accordingly to which one of them is connected or
disconnected. I was trying to add something like that to my Core 2 Duo testing
setup, but it seems there is no easy way how to export i
Hi,
My board Kontron 986lcd-m (i945) sometimes fails in quick_ram_check_or_die()
with
RAM INIT FAILURE!
The failure occurs in about 33% of reboots. RAM modules are fine (multiple
memtest checks over the years), used RAM modules are rated with a reserve
(DDR2-800 compatible modules and
Hello,
On i945 northbridge:
ASSERTION ERROR: file 'src/cpu/x86/smm/tseg_region.c', line 31
can be triggered by some configurations. The assert
ASSERT(IS_ALIGNED(sub_base, sub_size));
tests alignment of SMM base with SMM size. The problem is that IGD stolen
memory can offset th
Yes, nice job Werner!
Since you’ve been working on Elkhart Lake, can I inquire if you have booted it
to an OS via eMMC and/or iPXE using coreboot? If so, with which payload?
Thanks,
- Jay
From: ron minnich
Sent: Friday, April 22, 2022 7:02 PM
To: Zeh, Werner
Cc: coreboot
Subjec
On Fri, Apr 22, 2022 at 11:59 PM Karl Semich <0xl...@gmail.com> wrote:
>>
>> We are deprecating ALL boards on oreboot that need FSP, as we took the
>> decision a few weeks ago to drop boards
>> that require blobs on the main CPU (we're accepting PSP blobs for now)
>
>
> Just a quick note that our s
Martin Roth via coreboot wrote:
> https://review.coreboot.org/c/coreboot/+/63797
This is great!
Do you think we can generate the table for each branch from Kconfig
select MAINBOARD_SUPPORTED_ON_BRANCH_* automatically on releases?
Initially I also had a concern that maybe column width would need
Hi Martin,
Martin Roth via coreboot wrote:
> https://review.coreboot.org/c/coreboot/+/63754
..
> It's not a complete solution, but hopefully it's seen as a step in
> the right direction.
Thanks a lot for this.
I think that this really helps with visibility while guiding people
at the same time.
Andy Pont wrote:
> As soon as they get here I will start testing the various configs
> to see what works and what is broken.
Many thanks to you and everyone who helped make this happen!
//Peter
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Putsala Amar via coreboot wrote:
> We are working on intel c508 intel denverton board.
> We have programmed coreboot image in 16MB NOR flash.
>
> How can i get the coreboot version and build time stamp details in
> linux user mode? Does it creates any sys/proc entry?
Investigate DMI and cbmem.
Martin Butt wrote:
> Do you know if Coreboot would work on either of these systems?
..
> Both the 3290 and the 3030 CPUs are a Intel Celeron N2807 1.58GHz
That's the CPU marketing name which in firmware like coreboot doesn't
mean much. What matters is that this is a Bay Trail platform.
> From a
Rudolf, thanks a lot for challenging me and clarifying the problem!
ron minnich wrote:
> Rudolf's point is crucial: "Challenge accepted. They aren't [self
> defining] because they are defined with ABI/compiler:"
>
> As Rudolf points out, we are defining a binary layout with a c
> compiler. That's
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