Hi,
I just want to verify has anyone tested the ITE IT8718F superio support?
Over at: http://www.coreboot.org/Supported_Motherboards
all motherboards mentioned are in the unknown status at the moment.
I'm currently porting to motherboard with this specific superIO chip.
There's nothing
On 3/8/15, Kyösti Mälkki kyosti.mal...@gmail.com wrote:
On Sun, 2015-03-08 at 20:26 +0700, Darmawan Salihun wrote:
Hi,
I just want to verify has anyone tested the ITE IT8718F superio support?
Over at: http://www.coreboot.org/Supported_Motherboards
all motherboards mentioned
Hi,
I have checked the list of supported chipset and board but it seems
that Intel Q45 is not yet in the list. I recall, this chipset is the
same family with Intel gm45. Anyway, the specific board I'm going to
port into is Gigabyte GA-EQ45M-S2 Rev.1. This board has Intel Q45
northbridge and
Hi Kyosti,
On 1/30/14, Kyösti Mälkki kyosti.mal...@gmail.com wrote:
On 01/30/2014 09:41 AM, Darmawan Salihun wrote:
Hi all,
Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536
board?
Or do I have to resort to other Coreboot version?
You might be very much on your own
Hi Christian,
On 1/30/14, Christian Gmeiner christian.gmei...@gmail.com wrote:
Hi
...
Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536
board?
Or do I have to resort to other Coreboot version?
You might be very much on your own just with the v3 build environment. I
Hi all,
Is it still possible to use Coreboot v3 for an AMD Geode LX800-CS5536 board?
Or do I have to resort to other Coreboot version?
I have all the required datasheet and circuit diagram to do the port.
The board is a custom board, not from any of the usual motherboard
manufacturers.
Kind
Thanks Marc :-)
On 7/13/12, Marc Jones marcj...@gmail.com wrote:
On Thu, Jul 12, 2012 at 2:01 PM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
Hi guys,
The link to: Low Cost Embedded x86 Teaching Tool
in the wiki:
http://www.coreboot.org/Previous_GSoC_Projects
I'm sorry if this is not really related to Coreboot.
I have yet to make active contribution to the project.
I have released the PDF version of my BIOS Disassembly Ninjutsu book.
Direct link:
hxxp://www.4shared.com/office/k6ooEak2/BIOS_Disassembly_Ninjutsu_Unco.html
two errata have been found so
Hi guys,
Does this have something to do with remapping the RAM shadowed by
PCI devices to above 4GB?
Anyway, I haven't know yet whether Coreboot remaps RAM shadowed by
PCI devices.
Regards,
Darmawan
On 2/22/12, Peter Stuge pe...@stuge.se wrote:
David Hillman wrote:
It looks like I am
Hi Ron,
I've been looking for DDR-SDRAM start-up tutorial. Is there any on the
web outside of the JEDEC specs? Anyway, where are the codes located in
the Coreboot source ? is it on the motherboard-specific codes?
TIA,
Darmawan
On 2/15/12, ron minnich rminn...@gmail.com wrote:
reading your
Well, sorry about the noise. I forgot to mention that most of the RAM
init I found was in the raminit.c of each of the northbridge. Is there
any other important file(s) that I missed?
Thanks,
Darmawan
On 2/20/12, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi Ron,
I've been looking
Thanks Ron. I'm looking into it.
On 2/20/12, ron minnich rminn...@gmail.com wrote:
you commented out a number of calls to critical functions. You can't
just simply set a register and assume it all works. Maybe I
misunderstood.
I think stepan's i945 code is a great example of how to turn on
I made a blogpost detailing the steps to debug PCI Option ROM with
Coreboot+SeaBIOS and a GDB-server-compatible debugger:
http://bioshacking.blogspot.com/search/label/PCI%20Option%20ROM
Hopefully would help those in need because it takes quite a while to
get it right.
Thanks to Kevin O'Connor
Hi everyone,
I'm looking for AMD Hudson datasheet. I've looked at the links in the
Coreboot datasheet section but only AMD Family 14h links exists.
Has the Hudson FCH datasheet made public?
Thanks,
Darmawan
--
-= Human
Hi Guys,
Does enabling CONFIG_PCI_ROM_RUN in SeaBIOS is enough to test a PCI
expansion ROM ?
I have a PCI Expansion ROM to test with SeaBIOS (running in QEMU).
TIA,
Darmawan
--
-= Human knowledge belongs to the world =-
--
Hi Mark,
On 1/5/11, Marc Jones marcj...@gmail.com wrote:
On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi guys,
I'm looking for the support code for the IDE controller in CS5536
southbridge
Hi guys,
I'm looking for the support code for the IDE controller in CS5536 southbridge.
I checked-out Coreboot source code but only saw Flash interface
support in there.
I saw the IDE controller is switched to Flash interface support with
the DEADBEEF
magic number.
The board I'm working with
On 1/2/11, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hi guys,
I'm looking for the support code for the IDE controller in CS5536
southbridge.
I checked-out Coreboot source code but only saw Flash interface
support in there.
I saw the IDE controller is switched to Flash interface
,
Darmawan
On 10 Dec 2010 16:17, Darmawan Salihun darmawan.sali...@gmail.com wrote:
Hello,
Unfortunately, the board is a custom-build board.
I'm currently waiting for information from the board vendor.
Yes, I've tried using only the PATA interface (there's a PATA
connector on the board).
With the stock
Hi,
I'm working on an AMD LX800-CS5536 board. The IRQ is now working properly.
However, it's impossible to install an operating system through the
IDE interface or
the Compact Flash (CF) interface. Booting to the OS installation works
just fine
(Ubuntu Hardy Heron Linux and FreeBSD 8.0 and 8.1).
into,
MBR loading occasionally failed as well.
I'm still on the process of porting coreboot to this particular board.
As for the cs5536_pata.msr=1, haven't try that one. I'll test ASAP.
Thanks for the hints.
-Darmawan
On 12/10/10, Peter Stuge pe...@stuge.se wrote:
Darmawan Salihun wrote
I have the datasheet of this chipset. I'll send it to you later. I was
one working with legacy BIOS on moatherboard with this chipset.
-Darmawan
On 8/27/10, Mats Erik Andersson mats.anders...@gisladisker.se wrote:
Hello,
is there now, or has there been, someone interested
in the legacy
Hello guys,
Sorry, I haven't been able to update Winflashrom for more than 3 years now.
I'm planning to add Windows 7 support next month.
Therefore, I'm looking for suggestions.
A bit of Winflashrom background of the currently available Winflashrom
(at flashrom.org):
The programming model:
a.
-- Forwarded message --
From: Darmawan Salihun darmawan.sali...@gmail.com
Date: Mon, 7 Jun 2010 20:00:08 +0700
Subject: Re: [coreboot] SIS630ET coreboot challenge
To: Tiago Marques tiago...@gmail.com
I've sent a datasheet in my posession to Keith. Haven't heard back
from him yet
I'm not sure if this will work and it's risky as well, but you might
want to try it out:
In most BIOS, shorting the address pins (or the equivalent of that
act) upon boot will force the machine to boot from the bootblock BIOS.
The bootblock routine usually searches for BIOS binary file to flash,
Hi,
I wonder how coreboot passes the e820-style system memory map to the OS.
I found the following data structure pointer in the coreboot source code:
static struct parameters *faked_real_mode = (void *)REAL_MODE_DATA_LOC;
and also this line:
void append_command_line(struct parameters
Thanks, all clear now :)
On 3/26/10, Stefan Reinauer ste...@coresystems.de wrote:
On 3/25/10 5:39 PM, Darmawan Salihun wrote:
Hi,
I wonder how coreboot passes the e820-style system memory map to the OS.
With SeaBIOS, the OS or bootloader just calls an e820 int call.
With FILO or Grub2
I think every UEFI/EFI implementation will boot to old school boot
mode when it can't find any EFI/UEFI-compliant
boot-device/boot-partition. It would take too long though but at least
the fallback is there.
-Darmawan
On 3/9/10, Ed Swierk eswi...@aristanetworks.com wrote:
On Fri, Mar 5, 2010 at
On 3/9/10, Ed Swierk eswi...@aristanetworks.com wrote:
On Fri, Mar 5, 2010 at 8:58 AM, ron minnich rminn...@gmail.com wrote:
Just got a new nehalem box in for test yesterday. Experiences so far:
1. POST from power-on takes 45 seconds. *45 SECONDS*. Now, I had it
said to me at SCALE7x last
Flashrom used to have Windows port that I worked on back in 2007
(Winflashrom). I'm willing to help if any student want to port to
Windows 7. I'm not a student anymore ;-)
Regards,
Darmawan
On 3/5/10, Marc Jones marcj...@gmail.com wrote:
On Thu, Mar 4, 2010 at 8:55 AM, Carl-Daniel Hailfinger
Hi Mark,
Thanks. I'll have a look.
-Darmawan
On 1/22/10, Marc Jones marcj...@gmail.com wrote:
On Wed, Jan 20, 2010 at 2:13 AM, Darmawan Salihun
darmawan.sali...@gmail.com wrote:
The default value of MSRC001_001A (Top of Memory below the 4GB limit)
according to BKDG for AMD Fam 10h rev. 3.06
on is: __0400_h
Which one of this information is correct?
I need to know it because I want to know what is the default MMIO range
after reset.
Thanks.
--
Regards,
Darmawan Salihun
-= Human knowledge belongs
: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
--
Regards,
Darmawan Salihun
-= Human knowledge belongs to the world =-
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
--
Regards,
Darmawan Salihun
[mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of
Darmawan Salihun
Sent: Wednesday, November 18, 2009 2:51 PM
To: coreboot@coreboot.org
Subject: [coreboot] Looking for AMD AGESA GPL-ed source code
Hello all,
Sorry if this sounds like a rather stupid question. Is the GPL
OK. Thanks for the links.
On 11/18/09, Stefan Reinauer ste...@coresystems.de wrote:
On 11/18/09 7:50 AM, Darmawan Salihun wrote:
Hello all,
Sorry if this sounds like a rather stupid question. Is the GPL-ed
AGESA source code already becomes part of the coreboot svn? or I have
to download
Hello all,
Sorry if this sounds like a rather stupid question. Is the GPL-ed
AGESA source code already becomes part of the coreboot svn? or I have
to download it somewhere else?
Thanks.
--
Regards,
Darmawan Salihun
-= Human
What is the BIOS RAM in AMD SB7XX used for?
Is it to buffer the BIOS contents from SPI flash chip prior to
execution of the very first instruction?
I recall that it's impossible to execute code directly in an SPI chip.
or am I missing something?
--
Regards,
Darmawan Salihun
it with other
board ASAP :-(.
Anyway, how to set the baudrate?
--
Kind Regards,
Darmawan Salihun
-= Human knowledge belongs to the world =-
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo
/coreboot
--
Regards,
Darmawan Salihun
-= Human knowledge belongs to the world =-
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
http://www.coreboot.org/mailman/listinfo/coreboot
--
Regards,
Darmawan Salihun
-= Human knowledge belongs to the world =-
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Hi Marc,
On Jan 22, 2008 1:21 AM, Marc Jones [EMAIL PROTECTED] wrote:
The 690/600 support should be available in the first half of this year.
We moved it out a few months to bring in the Barcelona support.
I don't have specific dates but we will announce the code to the list as
soon as it is
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