When I tried using flashrom and the file downloaded off John's site, I get
a failure result. If I flash back to the backup.bios it says sucess. Why
would this be happened on the Samsung 550?
On Tue, Aug 6, 2013 at 3:00 AM, coreboot-requ...@coreboot.org wrote:
Send coreboot mailing list
On 21.06.2011 03:54, ali hagigat wrote:
I have a motherboard, Pentium III, 815/ICH2. How the CPU can be put
into the deep sleep state?
Is it possible to do it while not having the board schematic?
Sure read the sleep states in ICH2 datasheet.
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On 22.05.2011 11:50, Gregg Levine wrote:
Hello!
I just ran the commands to update a previously checked out release.
And without any complaints or anything else repeatable it just worked.
Well that is a good thing :-)
Thank god for SVN :-)
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On 04/28/2011 10:55 AM, Boris Shpoungin wrote:
Is there searchable version of this mail list which allows to search posts by
keywords?
Thanks
http://www.mail-archive.com/linuxbios@clustermatic.org/
http://blog.gmane.org/gmane.linux.bios/
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on
http://blogs.coreboot.org.
Hello Hamo, Leandro, Stefan, and Tadas! Welcome to coreboot, glad to
have you :-)
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Happy Bunny Day Everyone!
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On 04/12/2011 05:10 PM, Stefan Reinauer wrote:
Hi,
just a heads up, I got romcc to segfault with the following sample program:
D'oh!
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to other value than 0x0 so that we can put boot code
at the start of rom.
Which one should I take or Do we have any better choice?
Hope for your help.
How about spitting up the code using pre-processing directives? One for
arm and one for IA32? Just a thought.
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On 04/10/2011 12:25 PM, Patrick Georgi wrote:
Am 10.04.2011 18:10, schrieb Joseph Smith:
How about spitting up the code using pre-processing directives? One for
arm and one for IA32? Just a thought.
AH
please. not. more. compile. time. options.
sorry I
shouldn't be forced to
use git, especially since subversion has been used for aeons with
coreboot. Personally, I would be very unhappy to be forced to use git.
-1 to gitification
Yes Alex, I prefer svn over git 10 to 1.
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most of coreboot coding is pci_write_configX(whatever the
datasheet tells you). The hard part is figuring out all the stuff the
datasheet doesn't tell you :(
Yeah and Intel is great at only giving you half the picture ;-)
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. It would be great if you
could suggest how to link that dependency.
Maybe instead libpayloads USB options should be enabled by default?
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of the logical flow of coreboot in
general.
http://qa.coreboot.org/docs/doxygen/
I believe PPC was purged from the tree a little while ago so if you go
back some revisions you will be able to find it.
Hope that helps.
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:-)
Please supply a patch that adds this entry key to the fintec code in
superiotool.
Yes on my todo list.
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On 02/28/2011 02:16 AM, Rudolf Marek wrote:
Hi all,
Would someone be interrested if I write something about microcoded CPUs
controllers? Like the classic uCode ROM + ALU + Regs + IO unit?
Thanks,
Rudolf
Yeah sure :-)
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Hello I am in the new england area so NYC is not to far for me :-)
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Gregg Levine gregg.drw...@gmail.com wrote:
On Fri, Mar 11, 2011 at 9:29 PM, David Hendricks dhend...@google.com wrote:
Hey everyone, Stefan and I are going
respondents. We're getting tired of having to
tell people that Intel does not provide the documentation needed to
support their hardware.
So, suck it up, and look at AMD's offering instead.
Wow!
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quadcores Phenom2 AM3 or
AM+..
(i wrote your sentence about Satan,but i dont want to spend money on
unworking system)
I just need as much powerfull CPU as it can be to use with Coreboot.
Did you look here?
http://www.coreboot.org/Supported_Motherboards
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could be
available ?
Good luck to you, no part of that board is currently supported by coreboot
it is simply way too old. Also good luck trying to find any datasheets for
something that old.
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be something is funky with your memory controller not
initializing correctly, this would cause bad SPD reads.
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did you actually test CAR on a Socket
604 board? Or is this all just abuilded?
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On 03/09/2011 08:04 PM, Alex G. wrote:
On 03/10/2011 02:30 AM, Joseph Smith wrote:
Yes I am a little confused. Alex did you actually test CAR on a Socket
604 board? Or is this all just abuilded?
I researched the matter, found that those CPUs support it, and I even
found that a board already
for that.
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On 03/02/2011 12:03 PM, Andy wrote:
How to use the coreboot-5917 software??
$ svn co svn://coreboot.org/coreboot/trunk coreboot -r 5917
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don't you leave acpi out for now, Linux doesn't need it to
boot. I would concentrate on your IRQ routing issue.
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On 03/02/2011 05:03 PM, Alex G. wrote:
On 03/02/2011 11:41 PM, Joseph Smith wrote:
On 03/02/2011 04:38 PM, Peter Stuge wrote:
Alex G. wrote:
Add support for ASUS K8X-X SE motherboard.
..
Linux cannot complete booting.
Also not with acpi=off so that it uses the mptable?
Yes. It fails
know some of you get sick of my assembly questions :-)).
Could I be considered a student candidate for GSoC?
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in living.
coreboot is selling life insurance now?
Is this in case of electro static discharge?
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no, no.
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really compare AMD to Intel, the same way you cannot compare
an athlete to an old fart. :)
The day Intel directly contributes code to coreboot will be the day
monkeys land on mars.
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to them, many thanks, you know who you are :-)
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the bare minimum and get raminit
working. After that you can worry about things like cmos, vga, etc. No need
to make things to complicated right off the bat, your just end up with a
headache :-)
Well I hope this helps.
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sent?
Why don't you try it and find out!
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running on a board no way better to
learn than to get your hands dirty, then maybe you will stop asking all
these silly newbie questions.
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, which is modified from serprog, mainly by
adapting it to suit SPI.
Best regards,
Juhana Helovuo
Wow! that is really cool! I hope it works out as planned :-)
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On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson myle...@gmail.com wrote:
On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith j...@settoplinux.org
wrote:
Hello,
Working on a new CK804 board
Which board did you base it on? What are the differences?
I based it on the Asus A8N-E. The only
On Thu, 27 Jan 2011 07:02:04 -0700, Myles Watson myle...@gmail.com wrote:
On Thu, Jan 27, 2011 at 6:38 AM, Joseph Smith j...@settoplinux.org
wrote:
On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watson myle...@gmail.com
wrote:
On Thu, Jan 27, 2011 at 5:29 AM, Joseph Smith j...@settoplinux.org
On 01/27/2011 10:26 AM, Joseph Smith wrote:
On Thu, 27 Jan 2011 07:02:04 -0700, Myles Watsonmyle...@gmail.com wrote:
On Thu, Jan 27, 2011 at 6:38 AM, Joseph Smithj...@settoplinux.org
wrote:
On Thu, 27 Jan 2011 06:15:34 -0700, Myles Watsonmyle...@gmail.com
wrote:
On Thu, Jan 27, 2011
by coreboot (CPU's, CK804, and SuperIO). This being my first AMD board
any key tips would be great... like how to find gpios...etc. Too bad
there is no public datasheet for CK804
Also is PCIE-1x and PCIE-16x both working on the CK804?
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by
isolating hardware access - this patch doesn't improve or degrade
security as the memory regions in question were already copied back
after emulation before this patch.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Nice work!
Acked-by: Joseph Smith j...@settoplinux.org
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This is more of a trivial thing but
Acked-by: Joseph Smith j...@settoplinux.org
It would be really nice to be able to choose Kconfig options for the INT15
Handler ;-)
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?
Is there a simple way to verify/read the raw data after coreboot is
copied to memory? Help?
Here is my bootlog: http://coreboot.pastebin.com/KNyMM9xZ
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is different between it (the 630) and
my chip (630ET).
Appreciate all the help I can get for this one.
Sweet! I have a bunch of SIS 630 boards laying around, anything I can do to
help just let me know :-)
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LMFAO !!!
Patrick Georgi patr...@georgi-clan.de wrote:
Am 03.01.2011 13:14, schrieb ali hagigat:
How .cb files are created?
Creative work of human beings.
and what they are used for?
All kinds of things.
In case you're wondering (which might qualify you for the creative work
mentioned above
know
what your doing???
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On Mon, 20 Dec 2010 22:53:13 -0500, Keith Hui buu...@gmail.com wrote:
Joseph, now go fix i810. ;-)
Sorry, It will not be for a while
I am to busy working on other things at the moment. Maybe Uwe, Anders, or
anyone else contributing to i810?
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...
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of their
blobs re-distributable...
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On 12/15/2010 06:51 AM, Patrick Georgi wrote:
Hi,
We have a couple of chipsets in the tree that require external data in CBFS,
sometimes with placement requirements (eg. for embedded controllers), and
there will be more of that kind to come.
Right now, we're adding Kconfig options for each and
On 12/15/2010 09:10 AM, Patrick Georgi wrote:
Am Mittwoch, 15. Dezember 2010, um 14:36:51 schrieb Joseph Smith:
Hmm, still a little confused what you mean here. So your patch just
reworks the code to handle all binary blobs the same???
It provides an easier way to add binary components.
Right
, great point Peter! The MBI binary bolb modules ***-have-*** to be
aligned in order for the VGA Bios to read them, other wise they are
useless blobs of crap, and the VGA Bios is smart enough to know that and
reject them.
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On 12/03/2010 10:32 AM, Joseph Smith wrote:
On Fri, 03 Dec 2010 10:02:57 -0500, Joseph Smithj...@settoplinux.org
wrote:
Hello,
Just an FYI for anyone interested in a cheap powerful server board to
develop coreboot on:
IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal
On 12/09/2010 05:41 PM, Stefan Reinauer wrote:
* Jonas Bülowjonas.bu...@gmail.com [101209 22:36]:
SerialICE sounds interesting. Is the project still alive?
Yes, it is. Alive and waiting for contributions. :-)
Stefan
It is as alive as you want to it to be Jonas :-)
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-/230548264166?pt=Motherboardshash=item35adbf54e6
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On Fri, 03 Dec 2010 10:02:57 -0500, Joseph Smith j...@settoplinux.org
wrote:
Hello,
Just an FYI for anyone interested in a cheap powerful server board to
develop coreboot on:
IWILL DK8S2, comes with two 2.2GHz dual core Opterons for a steal at
$29.99
and there is 248 of them available
Hello,
I was just looking a iWill DK8S2 Opteron board but can not find the iWill
website on the web. Anyone know what happened to them?
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Hello,
I am in desperate need of a full (all tables) ACPI dump from somone with a
i852 or i855 chipset. You can send it to me offlist if you like. Thanks in
advance.
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should deduct the reserved range from the DRAM range before
this code runs?
Hmm. The UMA resource should be in high memory. And code should say if
UMA high memory resource is used do not allocate c. Interesting.
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On 11/10/2010 07:30 PM, Scott Duplichan wrote:
-Original Message-
From: Joseph Smith [mailto:j...@settoplinux.org]
Sent: Wednesday, November 10, 2010 05:42 PM
To: Scott Duplichan
Cc: 'Patrick Georgi'; coreboot@coreboot.org
Subject: Re: [coreboot] [PATCH] Avoid hang when 4GB or more DRAM
ramstage at the latest (because RAM init
failed for some reason).
Yes, sounds to me more like a raminit issue more than a CAR issue.
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) then it seems that you you have
a lot of research and development ahead of you.
Is it possible to have ACPI support for a board without SMM?
Sure can, it may have some limits though without a SMI Handler (SMM).
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mainboard will successfully compile and
generate the coreboot.rom
It is Intel D945GCLF motherboard.
The source code I used is coreboot v4 lastest version.
It would be great if someone could confirm this, thank you very much!
Best,
Fengwei
Ahh ICH4 also supports SMM :-)
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image. In
other
words, coreboot BIOS doesn't use any code under src/cpu/x86/smm/.
Since SMM is a special mode, am I supposed to use other ways to compile
SMM
mode code?
Thank you very much!
Well that is really not good!
What kind of board are you trying to compile it for?
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On 10/21/2010 11:01 AM, fengwei zhang wrote:
On Thu, Oct 21, 2010 at 10:52 AM, Joseph Smith j...@settoplinux.org
mailto:j...@settoplinux.org wrote:
On Thu, 21 Oct 2010 09:50:44 -0400, fengwei zhang
namedy...@gmail.com mailto:namedy...@gmail.com
wrote:
Hi
On 10/13/2010 03:00 PM, Uwe Hermann wrote:
Hi,
patch is committed with Peter's ack in r5949 as it's not really directly
related to this discussion and also boot-tested by me on MSI MS-6178
as mentioned in the patch description.
On Wed, Oct 13, 2010 at 09:50:52AM -0400, Joseph Smith wrote
On 10/14/2010 08:35 AM, Joseph Smith wrote:
On 10/13/2010 03:00 PM, Uwe Hermann wrote:
Hi,
patch is committed with Peter's ack in r5949 as it's not really directly
related to this discussion and also boot-tested by me on MSI MS-6178
as mentioned in the patch description.
On Wed, Oct 13, 2010
everywhere (and not
use SSE2 for ramtest) and get rid of the MMX/SSE/SSE2 config options?
Good point Uwe, I like how you think :-)
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On 10/13/2010 01:24 AM, Warren Turkal wrote:
On Tuesday 12 October 2010 19:22:43 Joseph Smith wrote:
FC-PGA's support SSE2 while the PGA's do not. that is the difference. I
created FC_PGA370 to make the CAR coversion simpler. Hope that helps.
I must be misunderstanding this entirely.
First
than the options in the
FC_PGA370 socket.
Thanks,
wt
On Tuesday 12 October 2010 15:08:22 Uwe Hermann wrote:
See patch.
Uwe.
FC-PGA's support SSE2 while the PGA's do not. that is the difference. I
created FC_PGA370 to make the CAR coversion simpler. Hope that helps.
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MAINBOARD_DIR
string
Hello Warren,
Unfortunately I do not have alot of coreboot time right now, but I will
try to test it this next week sometime. Yes I am the one who wrote the
code for this board; it is my freenas box at the moment :-)
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would like to ask if int0x42 is the same as int0x10 and if we
could assume the same handler for both of them to avoid such error?
Thanks,
Tadas S.
Yes int42 is the alternate of int10
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Coreboot
image is not in those formats, means it is not in elf, COFF formats? It
is
an executable file.
Can you please explain why you are so interested in coreboot's
build(make) process?
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, we can't have this happening.
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,
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On Tue, 03 Aug 2010 19:14:51 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
New version, also drop unused CAR descriptors from romstage GDT.
Yeah, I really like the macros, it makes it easier to read. I would like to
test it first before I ack it.
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On Sun, 01 Aug 2010 20:01:19 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
See patch.
As far as the CONFIG_USE_INIT, if nothing is using it and we have no tester
for the ASROCK...I say drop it and the associated code.
Acked by: Joseph Smith j...@settoplinux.org
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I don't really understand where the security hole is?
Can you explain a little more in depth?
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the built-in NM-10 video
onboard, and also includes a PCI-E 1x ION graphics card. I will try to
get both working.
Sweet! Good Luck Corey :-)
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to
Peter for spotting this)
Remove unused code in src/southbridge/amd/cs5535/ .
Thanks Nils, r5669.
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On 07/24/2010 01:12 AM, ali hagigat wrote:
You can talk about the Makefile too. How Coreboot is built in a typical
scenario and by what tools.
You mean Kconfig and crossgcc?
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:-)
By the way Ron, is there a page on the wiki or somewhere that gives a
little history I can use?
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!
At first glance, it looks like there is something wrong with your mtrr
setup. Maybe something weird about memory region allocations.
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sprouted off of the
coreboot tree.
5. Talk about how the code process flows and how you(audiance) can start
to develop coreboot.
6. Open for Question and Answer time.
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structure as v2
but we are now using Kconfig for our build system, don't get me wrong
though... alot has changed sinse v2 so dive in:-)
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.
As long as you can send a working/tested updated patch to the list:
Acked-by: Joseph Smith j...@settoplinux.org
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.
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SuperIO has many GPIO lines.
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.
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results,
and alot more information.
http://www.serialice.com
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in the US.
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On Mon, 28 Jun 2010 11:17:34 +0200, Stefan Reinauer
stefan.reina...@coresystems.de wrote:
On 6/28/10 5:08 AM, Joseph Smith wrote:
I am getting this error on the wiki:
http://www.coreboot.org/File:Paraflashersch.jpg
any ideas?
http://www.coreboot.org/pipermail/coreboot/2009-March
by the Lippert Frontrunner
board) which i had to fix.
It is ABUILD tested and boot tested on my Wyse S50.
Signed-off-by: Nils Jacobsnjaco...@hetnet.nl
Patch and bootlog attached.
I hope someone will find some time to review this rather large patch.
Thanks,Nils.
Sweet!
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Joseph Smith
Set
I am getting this error on the wiki:
http://www.coreboot.org/File:Paraflashersch.jpg
any ideas?
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Joseph Smith
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at
git://git.linuxtogo.org/home/kevin/seabios.git
http://git.linuxtogo.org/?p=kevin/seabios.git;a=blob;f=tools/buildrom.py
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PIII and Celerons. That is probably why I got the two
confused :-)
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On 06/22/2010 04:49 AM, Rudolf Marek wrote:
Hi,
I have done a ROMCC version too. Stay tuned. Btw this means that
SerialICE over Ethernet is closer too.
YAHOO! This is great news for serialice Rudolf :-)
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microcode_info: sig = 0x068a pf=0x0010 rev = 0x
microcode updated to revision: 0001 from revision
Before I did not get the Using generic cpu ops (good) is that ok?
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On Mon, 21 Jun 2010 09:57:36 +0200, Peter Stuge pe...@stuge.se wrote:
Joseph Smith wrote:
Hmm. If I add 0x0680 and delete the others I get:
CPU: vendor Intel device 68a
CPU: family 06, model 08, stepping 0a
Using generic cpu ops (good)
Enabling cache
Before I did not get
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