On 11/11/18 5:42 PM, Piotr Kubaj via coreboot wrote:
> The size of AGESA is currently about 10% of coreboot. Nico, do you
> think a single person working in spare time can reimplement 10% of
> coreboot?
I don't care how much it looks like. It's likely bloated vendor code.
For instance, look at the
Hi,
has anyone made good or bad experience with the Apollo Lake FSP
currently on Github (it's the MR5, afaict)? FSP-M never returns
for me and I have no post-code display :-/
I tried both XIP and loading into CAR, same result. Maybe it's
still something wrong with my configuration. If anybody had
Am 19.11.18 um 10:37 schrieb Nico Huber:
> My FSP-M UPDs could be wrong as well. But can that result in a
> hanging FSP? Do we have to expect undefined behaviour because
> of bad memory parameters?
Solved it. My board has an SPD and I was missing the pad configuration
for SMBus.
Hi Alexey,
On 11/20/18 7:13 PM, Alexey Borovikov wrote:
> Is there an external superio on your board?
yes, kind of. There's an FPGA attached to the LPC bus that exposes UARTs
among some other interfaces.
> At the moment I am trying to solve the problem of initializing the
> external superio chip
On 23.11.18 17:00, Patrick Georgi via coreboot wrote:
> Am Fr., 23. Nov. 2018 um 16:32 Uhr schrieb Arthur Heymans <
> art...@aheymans.xyz>:
>
>> Nico also suggested to set the timeframe 2 weeks before the release, to
>> avoid last minute WIP patches attempting to tackle the issue right
>> before t
On 25.11.18 18:24, j44...@goat.si wrote:
> the mac 70:3a:cb:bd:fd:e3 . This is probably some Google device his
> device is connecting to because the mac range is registered to Google
> Inc. Now i can lookup in public wifi databases and in some cases i then
> know where the users lives.
You can als
Hi Yannik,
On 25.11.18 20:05, Yannik Catalinac wrote:
> For the SPI programmer I decided to use a CH341A, but when I search for
> it there are different CH341A. Which one should I buy?
It shouldn't matter as long as it says to be compatible to SPI 25
series. There were reports about bad batches o
Hi Mike,
On 25.11.18 23:40, Mike Banon wrote:
> Hi Nico, please could you confirm that FT2232H (link to which you have
> provided) could work as a debug dongle? At "menuconfig" I only see
> USBDEBUG_DONGLE_FTDI_FT232H but not FT2232H , don't know how similar
> they are to each other
yes, it works
On 25.11.18 23:40, Mike Banon wrote:
>> If u have an Raspi or Beaglebone laying around , they are also suitable for
>> flashing
> Although there's a problem with
> Raspi/Beaglebone/any-other-SBC(single.board.computer)-except-EOMA68 I
> have to mention - they're running the non-free binary blobs, a
Hi Grant,
I don't know how it is supposed to work on Haswell, but can give you
some pointers anyway.
tl;dr I don't think you are looking for a PCI device.
Am 27.11.18 um 08:11 schrieb Grant Grundler:
> Asus Chromebox (Panther) with Celeron 2995U processor is supposed to
> have a HW Random Number
Hello Mike,
Am 28.11.18 um 13:27 schrieb Mike Banon:
>> As a pure consulting service, the ports and customizations that we have
>> made to coreboot to support our clients' hardware (including the work
>> done for Intel) is turned over to the client at the end of each project
>> to do with as they
On 28.11.18 14:25, Arthur Heymans wrote:
> "Jay Talbott" writes:
>> I know I don't post much here, but I feel like I need to chime in on this
>> thread... Perhaps it's time that SysPro becomes a louder voice in the
>> community.
>>
>> Bay Trail and Broadwell DE are both still very popular platform
On 28.11.18 16:10, Jay Talbott wrote:
>> "Jay Talbott" writes:
>>> I know I don't post much here, but I feel like I need to chime in on this
>>> thread... Perhaps it's time that SysPro becomes a louder voice in the
>>> community.
>>>
>>> Bay Trail and Broadwell DE are both still very popular platf
On 28.11.18 02:59, Jay Talbott wrote:
> Although I have participated in a number of reviews of coreboot patches,
> I/we have not directly upstreamed any patches to coreboot.org. As a pure
> consulting service, the ports and customizations that we have made to
> coreboot to support our clients' hard
Hi Pete,
On 01.12.18 17:21, petecb via coreboot wrote:
> I'm wondering if my problem is related to not having any SATA drives
> installed? (I just have a PCI-E SSD). It may be the case that the logic
> to disable combined mode is not getting triggered in my scenario, yet it
> would do if there was
Hi Pete,
On 02.12.18 23:13, petecb via coreboot wrote:
> As the default SATA setting already appeared correct, I modified the 3
> additional settings that Taiidan had already indicated worked
> (memory_speed_boost, 1394 controller and SATA ALPM) so in my mind I was
> only adjusting one additional
On 03.12.18 19:50, petecb via coreboot wrote:
> I have attached a text file with an overview of all the options I have
> selected with the nconfig utility, on the off-chance someone spots
> something I have done wrong.
Best way to find out is to disable USE_OPTION_TABLE again and leave
everything
On 03.12.18 11:35, Felix Held wrote:
>> No idea why combined mode is the default, it's only useful for OSes from
>> the '90s. It's not about the type of drives (SATA vs PATA) connected but
>> how the SATA controller identifies itself to the OS.>
> I agree that the combined mode isn't the best defau
Hello Ed,
> I just started looking into adding support for the dell r610.
I really don't want to discourage you, but if I'm looking at the correct
datasheet, this machine is using Nehalem/Westmere EP processors (e.g.
Xeon X5550 etc.). If that is the case, this is no project suited for a
coreboot
Hello Frans,
On 13.12.18 08:48, Frans Hendriks wrote:
> I've uploaded a patch to gerrit, but the build was unstable.
> This caused by another patch in gerrit, without any relation to my patch.
>
> This issue in now solved in gerrit, so my patch should build without any
> problems now.
> What is
Hi,
On 13.12.18 16:15, kinky_nekoboi wrote:
> In Debians non-free repo there is already a newer version of Intels
> microcode, patching spectre ng attacks.
did that change? AFAIK, the updates don't patch the Spectre vulnerabili-
ties but rather only the performance regressions introduced by the s
On 07.12.18 22:46, taii...@gmx.com wrote:
> rowhammer is almost entirely a laptop problem or for that matter
> anything that uses SODIMM's due to their high density.
That doesn't seem right. Can you give any examples of chips commonly
used on SO-DIMMs that can't be found on DIMMs? I had the feelin
Hi,
>> Side note: I still wish there was an easier way to do this; I never
>> bothered transferring documentation to GIT because of the added time /
>> complexity vs. the Wiki WYSIWYG editor.
we are writing documentation in markdown now. IMHO, a much better choice
than WYSIWYG because you can wor
Hi Ranga,
On 03.01.19 09:24, galla rao wrote:
> Video Mode in Coreboot
>
> *CorebootLog*
> coreboot video frame buffer information
> physical_address: 0xC000
> *x_resolution: 0x400*
> *y_resolution: 0x300*
0x400 x 0x300 is exactly 1024x768.
> bits_per_pixel: 0x20
> bytes_per_line: 0x1000
>
Hi Mike,
On 07.01.19 20:33, Mike Banon wrote:
> Hi Felix,
>> I only know one board where the IMC is used for fan control - gizmo2
> Could you please clarify the IMC status for ASUS AM1I-A (AMD 16h
> mini-ITX board) ?
> Because at coreboot's "menuconfig" I see this dependency :
>
> > Chipset
> Ad
On 14.01.19 23:30, Ivan Ivanov wrote:
> tldr :P ...just kidding friend ;) here are some replies
>
>> 3.19 [*] Add gigabit ethernet firmware
>> # If I read correctly I need that for internet connection and this
>> bianry has just some configuration in it and no excecutable?
> That means your E
Hi Yannik,
On 17.01.19 13:46, Yannik Catalinac wrote:
>> Being a closed source this firmware may contain the backdoors or help
>> the backdoor-like functionality of intel me. So yes, this is a privacy
>> concerning thing.
>>> Well, don't use modern controllers (ethernet, USB, etc.) if you don't
>>
Hi akjuxr3,
On 19.01.19 13:33, akjuxr3--- via coreboot wrote:
> Here a fresh build and the cbmem of it:
>
> https://pastebin.com/RkNtM1GL
it looks like coreboot is doing it's job. The external GPU is made the
primary gfx adapter:
> Use plugin graphics over integrated.
> Setting up VGA for PCI:
Hi,
sorry for reviving this old thread (it wasn't long though). The topic
came up again in IRC today.
On 03.04.18 18:47, ron minnich wrote:
> So I would actually be in favor of what paul is advocating, but not the
> inconistency. To keep it consistent, I don't see that just using 1U
> everywhere
Hi Zvika,
On 09.02.19 12:23, Zvi Vered wrote:
> I noticed that starting from version 4.9, I can set the debug level of FSP.
>
> I downloaded FSP for Bay trail and used Intel's BCT to modify it.
> But coreboot hangs after calling to the FSP binary.
>
> How can I use the "FSP debug level" ?
This
Hi,
On 09.02.19 23:27, Mike Banon wrote:
> I am trying to enable FRAMEBUFFER_SET_VESA_MODE for G505S at its'
> Kconfig ( ./src/mainboard/lenovo/g505s/Kconfig ) and also set the VESA
> mode to 0x118 instead of default 0x117 setting, by inserting the
> following lines to G505S Kconfig:
>
> config F
Hi Zvika,
On 09.02.19 20:40, Zvi Vered wrote:
> PcdMrcInitSPDAddr1 = A0
> PcdMrcInitSPDAddr2 = A2
> ...
> C0.D0: SPD not present.
> C1.D0: SPD not present.
Did you solve this SPD problem yet? If not, this is likely still where
your later logs end, i.e. in FSP's raminit. It seems you try to tell F
Hi Ranga,
On 12.02.19 15:24, galla rao wrote:
> To pull cross compile tools in Coreboot the below command is run,
> make crossgcc-i386 CPUS=6
>
> Is there a step or a command to clean all the tools that got installed ?
simply, what `make help` suggests: `make crossgcc-clean`.
The resulting tool
Hi,
On 13.02.19 09:45, Patrick Rudolph wrote:
> With UEFI the defactor standard it seems reasonable to improve the
> tianocore payload integration.
I agree that UEFI may seem ubiquitous (we've slept too long, never pro-
vided an alternative), but why should we focus on tianocore?
Tianocore isn't
Hi Jonathan,
On 13.02.19 08:31, Jonathan Zhang wrote:
> Hi, I am working on porting coreboot to Skylake SP and OCP Tiogapass
> with FSP 2.0. I have a strange issue that I hope to get some wisdom.
> The boot hangs when executing this line "sub %ecx, %ebx" in
> src/arch/x86/walkcbfs.S
I don't know
On 13.02.19 07:17, galla rao wrote:
> Thank you Nico for response, it clears xgcc folders in crossgcc
> How about tarballs that were also downloaded ?
Probably not. `make -Cutil/crossgcc/ distclean` should do it. Don't
know if there is any top-level make target that triggers it. These
things are
Hi Matt,
On 14.02.19 18:56, Patrick Georgi via coreboot wrote:
> Am Do., 14. Feb. 2019 um 18:47 Uhr schrieb Vadim Bendebury
> :
>> Why does it have to be done by Seabios as opposed to Linux? It is easy
>> to create a USB stick which would boot Linux compiled with permissions
>> needed and with sta
On 14.02.19 09:28, Patrick Rudolph wrote:
> On Wed, 2019-02-13 at 10:15 +0100, Nico Huber wrote:
>> On 13.02.19 09:45, Patrick Rudolph wrote:
>>> With UEFI the defactor standard it seems reasonable to improve the
>>> tianocore payload integration.
>>
>> I agr
On 14.02.19 21:54, Matt B wrote:
>>
>> Actually that's what we do in the FILO payload.
>
>
> What is libflashrom used for in FILO? Was it intended at some point that
> FILO be able to reflash the BIOS, or is it being used for something like
> reading the flash chip in order to load other things?
On 16.02.19 16:08, Frank Beuth wrote:
> On Sat, Feb 16, 2019 at 05:23:40PM +0300, Sergej Ivanov wrote:
>> To make a real write protection on your spi flash you may go two ways
>> after
>> setting region protection and configuration bits in your flash
>
> Where are the write protection bits for the
Hello Alex,
On 16.02.19 18:39, Alex Feinman wrote:
> In my Coreboot build I provide both VBIOS and VBT blobs via appropriate
> configuration items. The VBIOS blob contains expected signature at the
> top and VBT is valid as confirmed by running intelvbttool against it.
> The platform is slightly m
On 17.02.19 02:35, Frank Beuth wrote:
> On Sat, Feb 16, 2019 at 06:00:26PM +0100, Nico Huber wrote:
>> Generally, what locking options you have depend much on your hardware.
>> Hence, there is no generic solution in coreboot. Plus, coreboot is more
>> a firmware framework th
On 17.02.19 11:12, Frank Beuth wrote:
> On Sun, Feb 17, 2019 at 10:02:42AM +0100, Nico Huber wrote:
>> What, why? Did you just say "SeaBIOS" because I said "sometimes ...
>> payload"?
>>
>> SeaBIOS is a very generic payload, trying not to be board
Hi Alex,
On 20.02.19 15:56, Alex Feinman wrote:
> I think I almost got to the bottom of it. I thought, incorrectly, that
> the VBT on my system is not accessible because I trusted intelvbttool
> from utils/ to dump it.
ah, quite some misunderstanding. You said initially the "VBT cannot be
located
Hi Ivan,
On 21.02.19 07:24, Ivan Ivanov wrote:
> Tianocore, being a standard UEFI, is vulnerable to UEFI-targeting
> malware whose functionality is based on UEFI architecture.
can you give an example of a malware (or exploit) that targets the
UEFI architecture in general (and not specific feature
Hello Masanori,
sorry for the late reply, I guess I could have saved you from some
confusion.
Am 26.02.19 um 05:35 schrieb Masanori Ogino:
> On Mon, Feb 25, 2019 at 4:27 AM Lance Zhao wrote:
>> Current coreboot should have same level of microcode compare to
>> intel-microcode for Linux.
>
> In
On 26.02.19 20:16, ron minnich wrote:
> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
> wrote:
>>
>> Hi coreboot folks,
>> in order to support TEE like Intel TXT it is necessary to be able to
>> clear all DRAM at boot on request.
>>
>> As all of the x86 coreboot code is x86_32, it is necessary t
Hello Neelix,
On 26.02.19 22:54, Neelix via coreboot wrote:
> I just compiled coreboot for a x220 and I got a error saying that
> data.vbt wasn't located in src/mainboard/lenovo/x220. It's indeed not
> in directory it should be in. Its located in
> src/mainboard/lenovo/x220/variants/x220/.
I gues
Hi Michal,
On 28.02.19 10:38, Michal Zygowski wrote:
> AFAIK gerrit now adds the reviewers to patches based on MAINTAINERS
> file. It would be great to be added automatically to Braswell patches.
> Is there a way to workaround that without being Braswell maintainer?
you can just push a patch that
Hi Martin,
Am 14.03.19 um 10:19 schrieb Martin Kepplinger:
> So, I'm looking into h8 EC access.
>
> Where does ec_set_bit(0x3a, 0) for audio-mute or ec_set_bit(0x3a, 6) for
> wwan-enable
> come from (let's keep that as an example)?
this uses a software interface that is defined by the program t
Hi,
trying to figure out in which ways clang-format is (supposed to be)
hooked up in our git-hooks. And what role it plays, yet.
There is a lint test, that so far never did something for me because
it relies on a `.clang-format-scope` file (that is not in the tree?).
Still, this check seems to be
Hey folks,
I overeagerly reviewed and submitted a change[1] lately, that set the
column limit for our C code to 96. My reasoning was that we already
live a "soft" limit of 80 chars and that tools shouldn't complain about
every single 8x-chars line (personally, I find this quite annoying
during rev
On 16.03.19 18:15, Ron Minnich wrote:
> On Sat, Mar 16, 2019 at 9:41 AM Patrick Georgi wrote:
> o Huber schrieb am Sa., 16. März 2019, 16:32:
>>>
>>> Do we want to enforce a single editor / IDE + configuration for coreboot
>>> contributions?
>
> we don't want to lock out, e.g., sublime, emacs, an
On 16.03.19 14:50, Nico Huber wrote:
> And also a `util/lint/check-style` that is only hooked up if you run
> `make git-config` recently (I didn't, so I'm a little surprised). This
> one doesn't have a scope file, it seems?
Does nobody know this one? It seems like a
Hi Michal,
On 29.03.19 16:49, Michal Zygowski wrote:
> I am wondering what is the format of CPU-DRAM DQ byte map for FSP-M
> configuration. Typically there are 64 DQ lanes per non-ECC SODIMM/DIMM
> (correct me if I'm wrong) for DDR4 for example. But the DQ map is an
> 2x12 array, so I assume 12 by
Hello Rafael,
On 28.03.19 17:12, Rafael Send wrote:
> Where would I generally find information about what controls the flash chip?
in the datasheet of the chip that is connected to the BIOS flash. What
chip that is, is not always easy to answer. If you don't have access to
the board's schematics,
On 29.03.19 19:08, Rafael Send wrote:
> Hi Nico-
> Can you clarify what you mean by coreboot on x86 is special?
on x86, there are two ways to access a SPI flash chip: 1. you can ask
the SPI controller via a register based interface to access the flash
chip. 2. by default, the flash chip contents o
Hi Alex, all,
Am 30.03.19 um 02:40 schrieb Alex Feinman:
> DDR RComp calculation is explained in the CPU platform design guide. If
> you are an Intel licensee, you can request this document by number -
> 561280 for KBL. There seems to be also a whitepaper you can ask your OEM
> rep for.
that ment
Hi Mike, Rafael,
Am 09.04.19 um 11:05 schrieb Mike Banon:
> Usually the size of CBFS filesystem should be equal to the size of
> your chip. In your case - ~15MB rounded up to 16MB - it should be
> 0x100 (16*1024*1024 = 16777216 in dec = 0x100) . So
> CONFIG_CBFS_SIZE=0x100 .
this is o
On 09.04.19 17:13, Rafael Send wrote:
>>
>> this is only true if the flash chip isn't shared with other firmware
>> components. But it often is. If you are running a modern Intel-based
>> system, for instance, CBFS size should be at most the size of the
>> BIOS partition of the flash.
>
>
> If I'm
On 10.04.19 14:31, Maxim Poliakov wrote:
> But, in this case, the loading of the coreboot stops after running the
> FSP-S in ramstage.
>
> Please see logs: https://drive.yadro.com/s/3ocCtS3EemjyT5f
Last line (would have been easier if you'd have attached it btw.):
> POST: 0x93
This is POST_FSP_S
Hi all,
I just noticed that there is a seemingly abandoned board that creates
a lot of maintenance burden for coreboot, also because it's using FSP
UPDs that are not present in the upstream header files.
Does anybody still care about Intel/Strago? If not, I'd prefer to drop
it immediately. It's o
Hi,
On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote:
> I've been looking into S3 resume on GM45 mainboards, which often fails
> in rather interesting ways.
Well, the S3 support wasn't really tested during GM45 development. Maybe
it's just plainly broken. My development system at work (roda/rk
Hi,
had a look at your logs:
On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote:
> These systems fail to resume in one of the following ways:
>
> * S3 resume (indicated by the SLP_TYP bit) is detected, SLP_TYP is
> cleared, DRAM receive-enable calibration fails with a timing
> under/
On 12.11.2015 04:37, Patrick 'P. J.' McDermott wrote:
> On 2015-11-11 16:50, Nico Huber wrote:
>> Hi,
>>
>> On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote:
>>> I've been looking into S3 resume on GM45 mainboards, which often fails
On 04.02.2016 22:25, Patrick Georgi via coreboot wrote:
> 2016-02-04 22:22 GMT+01:00 Martin Roth :
>> I don't think we need redefinitions of TRUE/FALSE
> We have no canonical definitions for TRUE/FALSE right now.
> Contributions that use them (for whatever reason) tend to bring local
> copies, and
On 04.02.2016 10:35, Patrick Georgi via coreboot wrote:
> I think we should seek uniformity here: decide on some style,
> recommend it, clean up the tree to match, and help people stay
> consistent through lint tests.
That's a good idea.
> 2. BIT16 vs BIT(16) vs (1 << 16) vs 0x1
> I don't thin
On 08.02.2016 12:10, Patrick Georgi via coreboot wrote:
> 2016-02-04 10:35 GMT+01:00 Patrick Georgi :
>> during the review of some commits that are in the process of being
>> upstreamed from Chrome OS, people noticed that chipset drivers like to
>> define their own TRUE/FALSE defines (sometimes pre
6346 bytes (865
>> KB)@0x0]; too big?
> This is indicates a 865K image. How is that supposed to fit?
you also stripped:
fallback/payload 0x1b140payload 769955
I guess he means that a fresh build with a bigger (865KiB instead of
752KiB) payload fails.
Nico
--
M.
n't know how to change the offsets. Some might not be chosen
arbitrarily at all. But maybe there is another simple option: Did you
already try to increase the size of your CBFS (CONFIG_CBFS_SIZE)? It
may be as large as the "bios" partition of your flash chip.
Hope that helps,
Nico
Hi Daniel,
first thing: We never got to the deepest processor sleep states (C3, C4)
when we originally ported coreboot for the GM45 chipset. But we didn't
see a difference in power consumption back then on the Roda/RK9.
On 01.05.2016 00:55, Daniel Kulesz via coreboot wrote:
> No tweaking with pow
Hi Daniel,
On 01.05.2016 12:26, Daniel Kulesz via coreboot wrote:
> Coreboot with idle=poll: 15,8W
> Coreboot running "stress": 37,2W
well, this is what I would expect from the specs.
> Vendor BIOS with idle=poll: 15W
> Vendor BIOS with intel_pstate=disabled: 10W
> Vendor BIOS running "stress": 2
On 01.05.2016 15:30, Daniel Kulesz wrote:
> Hi Nico,
>
>> On 01.05.2016 12:26, Daniel Kulesz via coreboot wrote:
>>> Coreboot with idle=poll: 15,8W
>>> Coreboot running "stress": 37,2W
>> well, this is what I would expect from the specs.
>>
>>> Vendor BIOS with idle=poll: 15W
>>> Vendor BIOS with
On 01.05.2016 21:40, Daniel Kulesz wrote:
> Hi again,
>
> I did some more experiments with the vendor BIOS and made the following
> observations:
>
> - disabling "cpu power management" makes the idle consumption raise to 12,8W
Is this 12.8W compared to 7.5W (i.e. with lowest backlight)?
> - disa
3, 0x02, 300,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x20, 0 }
},
for C3 or
{
/* acpi C3 / cpu C4 */
3, 0x02, 300,
{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 }
},
for C4. You can not have all of them
Hi Daniel,
On 03.05.2016 00:47, Daniel Kulesz via coreboot wrote:
> Hi all,
>
> On Mon, 2 May 2016 13:16:15 +0200
> Nico Huber wrote:
>> Regarding C3/C4 support, AFAIK, we implemented it fully but it just
>> didn't work on the system we originally ported coreboot
On 06.06.2016 23:40, Kyösti Mälkki wrote:
> On Mon, Jun 6, 2016 at 10:36 PM, ron minnich wrote:
>> I'm getting the sense here that reasonably modern CPUs can easily handle the
>> 2G hole. From what I've seen, it would not cause trouble for older CPUs
>> because they're most likely to be in small s
Hello Naveed,
On 07.06.2016 07:21, Naveed Ghori wrote:
> But I should still see 4GB without any patch. Right?
no, I'm afraid not.
> Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System.
This is correct as the 4GiB address space is not only used for RAM but
shared with othe
On 08.06.2016 04:26, Naveed Ghori wrote:
> Thanks Nico,
> What options should I be looking to tune? 3Gig should be fine as that
> is what I have seen in another product.
>
This depends heavily on the used hardware platform. I don't think all of
them have an option in coreboot. But it might be just
On 07.06.2016 16:40, Patrick Rudolph wrote:
> On 2016-06-06 09:58 PM, ron minnich wrote:
>> On Mon, Jun 6, 2016 at 12:52 PM Patrick Rudolph
>> wrote:
>>
>>> To summarize:
>>> The easy way is to use 2G.
>>> The preferred way would be to mimic mrc behaviour and reboot after
>>> finding the correct s
Hi Cheng,
On 22.07.2016 12:14, cheng yichen wrote:
> Hi all
>
> My platform is braswell SOC with W83627dhg superIO. In post stage I can get
> debug message over w83627 uart1(3f8/irq4). but after boot to linux, uart
> port is not woarkable. I test the function by minicom but I can't receive
> and
Hi Cheng,
On 25.07.2016 04:33, cheng yichen wrote:
> Hi all
>
> After i follow kontron/ktqm77 setting. I can't solve the issue.
> I try to change iqr(for com1) to 5 or 6. but system can't print linux
> message and minicom is not workable.
Can you confirm that you see the full coreboot log on you
Hi,
On 31.07.2016 17:07, Zheng Bao wrote:
> Hi, All,
>
> I want to add support MMIO UART support on OS.
>
> I checked the file pnp_uart.asl.
>
> For IO UART, a device with EisaId("PNP0501") is added into DSDT, the windows
> can detect the COM port in device manager.
>
> I am wondering if MMIO
On 10.08.2016 10:35, ron minnich wrote:
> ah, no, those are not it. Sorry. I'll get you some pictures.
Maybe [1] helps. It's my best FS2 shot for something coreboot related.
Nico
[1] http://web.archive.org/web/20080915062711/http://www.fs2.com/
>
> ron
>
>
>
> On Wed, Aug 10, 2016 at 12:42 A
On 26.08.2016 17:56, Vadim Bendebury wrote:
> I actually tend to agree with Julius that it does not make sense to waste 4
> lines for a two line comment. So, ideally the tool should be enforcing the
> verbose style for comments longer than say 2 lines.
Well, I too prefer the concise style for sho
On 24.08.2016 09:08, Paul Menzel via coreboot wrote:
> The coding style currently demands the following style of multi-line
> comments [1].
That's not true.
>
>> The preferred style for long (multi-line) comments is:
See, it just declares what is _preferred_.
Nico
>
> [1] https://www.coreboot.
Hi folks,
I think we kind of agreed that the wiki text about "Commenting" should
change. So here is my proposal, feel free to edit, add something or just
ack or complain about it.
> == Commenting ==
>
> Comments are good, but there is also a danger of over-commenting. NEVER
> try to explain HOW y
On 04.09.2016 21:36, Martin Roth wrote:
> Hey Nico,
> Thanks for writing that up and not just letting this drop with no
> resolution and action.
>
> To anyone just coming in on the discussion, here's what we're talking about
> changing:
> https://www.coreboot.org/Coding_Style#Commenting
>
>
> I'
On 06.09.2016 00:04, Vadim Bendebury wrote:
> On Sun, Sep 4, 2016 at 7:42 AM, Nico Huber wrote:
>
>> Hi folks,
>>
>> I think we kind of agreed that the wiki text about "Commenting" should
>> change. So here is my proposal, feel free to edit, add somet
e block with
>> '//'"?
>> -- "I know it says not to say 'increment i', but as the author, I
>> think it's
>> helpful."
>> 4) I think this would be the only "the author has the final say"
>> policy - what
>>
Hi Iru,
On 08.09.2016 13:25, Iru Cai wrote:
> Hi Patrick,
>
> On Wed, Sep 07, 2016 at 05:36:45PM +0200, Patrick Rudolph wrote:
>> On Wed, 7 Sep 2016 21:15:05 +0800
>> Iru Cai wrote:
>>
>> Hi Iru,
>> I've got a T520 with soldered pin header as in the referenced wiki page,
>> and I've got a T420 w
Hi Merlin,
On 24.09.2016 21:25, Merlin Büge wrote:
> Hello everyone!
>
>
> This is my first post to this mailing list :)
>
welcome to coreboot ;)
I didn't have the time for a closer look at your logs. But there is one
thing coreboot does definitely wrong: The clock configuration. You can
see it f
Hi Arthur,
On 09.10.2016 18:50, Arthur Heymans wrote:
> Hi
>
> I'm trying to port coreboot to the gigabyte ga-945gcm-s2l, which has a
> 945gc northbridge, a ich7 southbridge and a ite it8718f sio. I'm trying
> all this with a 1067fsb cpu, so in that last aspect there is no
> precedent in coreboot
Hello Mohan,
On 13.10.2016 09:14, Mohan Shanmuga Sundaram wrote:
> Dear Coreboot Community!
> I have modified the following CMOS option table bit using 'nvramtool'
> utility from Ubuntu:
> 384 1 e 4boot_option
>
> Its default value was 'Normal', which I modified to 'F
Hi Rick,
from your messages on IRC, I guess you almost got it. You have to select
SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git
grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set
for other boards. The correct files should then be added by Makefiles.
M
Hi,
On 15.10.2016 13:26, Antonius Riko wrote:
> I closed the patch
>
> //#include
> //#include
> //#include
>
> and I got error :
>
> bianchi@ubuntu:~/coreboot$ make
> GENgenerated/bootblock.ld
> CP bootblock/arch/x86/bootblock.ld
> LINK cbfs/fallback/bootbl
On 15.10.2016 14:57, Antonius Riko wrote:
> I did rm .config and did make again :
>
> bianchi@ubuntu:~/coreboot$ make clean
> bianchi@ubuntu:~/coreboot$ make
> #
> # configuration written to /home/bianchi/coreboot/.config
> #
> HOSTCC util/sconfig/lex.yy.o
> HOSTCC util/sconfig/sco
7;t matter, as long as coreboot doesn't boot
through. You can just leave it at the default "SeaBIOS", or change it
to "None" until you have a working coreboot.
Nico
>
>
> On 15/10/2016 9:12 PM, Nico Huber wrote
>
>> On 15.10.2016 14:57, Antonius Riko wrote:
Hi Philipp,
On 20.10.2016 16:50, Philipp Stanner wrote:
> Hi cb-community,
>
> as everyone who owns a computer can subscribe to the list and there is
> no coreboot-forum, I presume that I'm allowed to ask a few primitive
> questions about the topic :)
sure.
>
> 1. Coreboot+Payload are only use
On 22.10.2016 09:15, Philipp Stanner wrote:
> Is it possible to activate virtualization in the CPU somewhere?
Yes, look under "Chipset" in the configuration, it's "Enable VMX for
virtualization" (CONFIG_ENABLE_VMX).
Nico
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