Timothy Pearson [mailto:tpear...@raptorengineeringinc.com] wrote:
]Sent: Thursday, February 05, 2015 06:49 PM
]To: Coreboot
]Subject: Re: [coreboot] memtest86 reading 0k memory
]
]On 02/05/2015 06:42 PM, Timothy Pearson wrote:
] On 02/05/2015 02:06 PM, Timothy Pearson wrote:
] On 02/05/2015 01:51
Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2...@gmx.net] wrote:
]Sent: Tuesday, February 03, 2015 06:04 PM
]To: coreboot@coreboot.org
]Subject: Re: [coreboot] AMD Mahogany Fam10 not booting
]
]On 02.02.2015 06:30, Kyösti Mälkki wrote:
] On 02/02/2015 05:40 AM, Scott Duplichan wrote:
] I
Patrick Georgi [mailto:patr...@georgi-clan.de] wrote:
]Sent: Wednesday, February 04, 2015 11:57 AM
]To: Scott Duplichan
]Cc: coreboot@coreboot.org
]Subject: Re: [coreboot] AMD Mahogany Fam10 not booting
]
]Am 2015-02-04 18:01, schrieb Scott Duplichan:
] The reason is that I wanted to
] see
Yang, York [mailto:york.y...@intel.com] wrote:
]Sent: Wednesday, February 04, 2015 01:22 PM
]To: Patrick Georgi
]Cc: coreboot@coreboot.org
]Subject: Re: [coreboot] Can I upstream an UEFI payload binary for MinnowMax
board project
]Actually we also work on a solution to build an UEFI payload
I found coreboot for AMD Mahogany Fam10 is no longer working. The problem
starts with this change:
http://www.coreboot.org/pipermail/coreboot-gerrit/2013-July/002391.html
Some other older AMD boards are likely affected too. Here is a workaround:
src/device/pci_ops.c | 2 +-
1 file changed, 1
Timothy Pearson [mailto:tpear...@raptorengineeringinc.com] wrote:
]
]All,
]
]I have been working on porting Coreboot to a new CK804-based K10
]mainboard; it warm boots but will not cold boot due to IRQ/MSI
]configuration issues.
]
]While tracing the IRQ problem I noticed that the CK804 PCI
ron minnich [mailto:rminn...@gmail.com] wrote:
]Sent: Sunday, August 10, 2014 06:34 PM
]To: Marc Jones
]Cc: Scott Duplichan; coreboot
]Subject: Re: [coreboot] why is firmware 32 bit as opposed to 64 bit
]
]I understand the arguments.
]
]It's worth remembering that coreboot has to date run on 5
I found the AMD mahogany Family 10h coreboot is no longer booting on my
ECS-A780GM-M3 board. The first problem it encounters is a hang after warm
reset. The hang is due to HT training fail. Using the config option to
limit the HT speed works around the problem. Though older coreboot builds
do not
Peter Stuge [mailto:pe...@stuge.se] wrote:
]Sent: Sunday, December 14, 2014 02:43 PM
]To: coreboot@coreboot.org
]Subject: Re: [coreboot] Updated coreboot build environment for Windows
]
]Peter Stuge wrote:
] Peter Stuge wrote:
] First, commit and push the change to the submodule repo. Do this by
Patrick Georgi [mailto:patr...@georgi-clan.de] wrote:
]Sent: Sunday, December 14, 2014 09:38 AM
]To: coreboot@coreboot.org
]Subject: Re: [coreboot] Updated coreboot build environment for Windows
]
]Am 13.12.2014 um 15:14 schrieb Peter Stuge:
] Finally push that to gerrit for review as usual.
]...
I have maintained a coreboot build environment for Windows for a while:
http://notabs.org/coreboot/windows-build.htm
Though maintaining it has never been a priority for me,
the website log files show quite a few people download it.
For this reason I am trying to improve this project. The
Patrick Georgi [mailto:patr...@georgi-clan.de] wrote:
]Sent: Thursday, December 11, 2014 12:40 PM
]To: coreboot@coreboot.org
]Subject: Re: [coreboot] problem with: vendorcode/amd/agesa/fam15: Build as a
static library
]
]Am 2014-12-10 07:27, schrieb Scott Duplichan:
] While trying to get abuild
While trying to get abuild working from Windows I found a coreboot
makefile problem. File src/vendorcode/amd/agesa/f15/Makefile.inc is
be processed twice. While this doesn't break a Linux build, it does
break the Windows build. The Windows problem is because the ar
command line contains each
Stefan Reinauer [mailto:stefan.reina...@coreboot.org] wrote:
]On 11/20/14 9:40 PM, Scott Duplichan wrote:
] The Gluglug [mailto:i...@gluglug.org.uk] wrote:
]
] ]-BEGIN PGP SIGNED MESSAGE-
] ]Hash: SHA1
] ]
] ]Hi,
] ]
] ]cbfs-mkstage.c: In function ‘is_phdr_ignored’:
] ]cbfs-mkstage.c:45
The Gluglug [mailto:i...@gluglug.org.uk] wrote:
]-BEGIN PGP SIGNED MESSAGE-
]Hash: SHA1
]
]Hi,
]
]cbfs-mkstage.c: In function ‘is_phdr_ignored’:
]cbfs-mkstage.c:45:84: error: cast to pointer from integer of different
]size [-Werror=int-to-pointer-cast]
]
]The fix was made in
ron minnich [mailto:rminn...@gmail.com] wrote:
]Thanks scott!
]
]So, what does an OS do to disable USB in the operating system? We have
]seen Linux do it, we're not quite sure just what
]place it gets done.
]
]ron
If I understand your question, I am not sure I know the answer. If you
boot linux
ron minnich [mailto:rminn...@gmail.com] wrote:
]This is really interesting information, thanks.
]
]This embedded USB stack problem actually impacts HPC applications.
]This type of periodic interference can cause big troubles when you
]have lots of nodes.
]
]Look for the case of the missing
Vladimir 'φ-coder/phcoder' Serbinenko [mailto:phco...@gmail.com] wrote
]On 10.08.2014 21:06, John de la Garza wrote:
] I understand that the calling functions in 32 bit C uses the stack and
] this is why coreboot needs to use cache as RAM. Doesn't 64 bit C use
] registers to pass arguments to
ron minnich [mailto:rminn...@gmail.com] wrote:
]you can no longer update microcode after the kernel boots
](on modern Intel CPUs). It has to happen before you do Cache
]As Ram in many cases, or you'll get some pretty unpleasant
]consequences.
]
]ron
]
][...]
While I am no expert on recent
that I know of.
Thanks,
Scott
]On 06/19/2014 08:11 PM, Scott Duplichan wrote:
] Scott Duplichan [mailto:sc...@notabs.org] wrote:
]
] ]Sent: Thursday, January 09, 2014 08:37 AM
] ]To: 'coreboot@coreboot.org'
] ]Subject: coreboot engineer needed
] ]
] ]
] ]https://intel.taleo.net/careersection/1
ron minnich [mailto:rminn...@gmail.com] wrote:
]realistically, though, it's hard for me to see how setting the
]serial # at firmware image build time scales. And setting it after
]boot makes no real sense either -- it's not really a serial number
]if you're changing it at that point.
]But some
Scott Duplichan [mailto:sc...@notabs.org] wrote:
]Sent: Thursday, January 09, 2014 08:37 AM
]To: 'coreboot@coreboot.org'
]Subject: coreboot engineer needed
]
]
]https://intel.taleo.net/careersection/1/jobdetail.ftl?job=725464
]
]Thanks,
]Scott
https://intel.taleo.net/careersection/1
The coreboot build environment for Windows is once again working:
http://notabs.org/coreboot/windows-build.htm (release 013).
SeaBIOS also builds, but requires a change not yet in
SEABIOS_STABLE. Use SEABIOS_MASTER for now. Thanks to
Kevin for that change:
Mark C. Mason [mailto:m...@edt.com] wrote:
]We are testing coreboot with our new IMB-A180 based AGESA design,
]and DMA interrupts are not functioning. I am looking into the Coreboot
]Options, but is there a recipie for enabling legacy interrupts in AGESA?
]We configure in Linux at IRQ 17.
]
Mark C. Mason [mailto:m...@edt.com] wrote:
]Is there a straightforward way to get an IMB-A180 to boot with a single
]DIMM in slot 0? It boots fine in slot 1. I've looked through the code
]at length, and thought it configures the dimm, it fails in
]
Krzysztof Pierwieniecki [mailto:kpierwienie...@teldat.com.pl] wrote:
]I have a problem on Intel DQ77KB board. I have two the same boards and
]on every board Memtest86 reports a problem at 2990.8MB. That problem
]occur only if I use 4 or 8GB memory. With 2GB memory everything is OK.
]
]What may
ron minnich [mailto:rminn...@gmail.com] wrote:
]On Tue, May 13, 2014 at 5:29 AM, Peter Stuge pe...@stuge.se wrote:
]
] That's an important question, but I believe the answer is no.
]
]That's all I wanted to know, to start.
]
]So why don't we just get that CL in and see where we go from there.
]
Paul Menzel wrote:
]Am Dienstag, den 06.05.2014, 00:18 -0500 schrieb Scott Duplichan:
] Paul Menzel wrote:
]
] ]I try to get KolibriOS running on the ASRock E350M1 with coreboot and
] ]SeaBIOS payload. Keyboard and mouse do not work [1] probably because
] ]KolibriOS needs PIC mode
Scott Duplichan [mailto:sc...@notabs.org] wrote:
[...]
]As for the mouse problem, I think it may be PIC interrupt
]routing related. I see our PIR table is incomplete and also
]the legacy interrupting route reporting registers in PCI
]config space are not filled in. I will look at that tomorrow
ron minnich [mailto:rminn...@gmail.com] wrote:
]So, how would these changes affect other payloads?
]
]ron
The patch adds programming and one reporting
mechanism for PIC mode PCI interrupt routing for
the ASRock E350M1 board only. Without the patch,
PIC mode PCI interrupt routing is not
ron minnich [mailto:rminn...@gmail.com] wrote:
]Thanks, that's a great explanation. Generally, we've tried to avoid
]too much hardware setup in coreboot; that's the job of the kernel.
The PIC mode interrupt routing configuration must be done by
BIOS because proprietary southbridge registers are
Paul Menzel wrote:
]Dear coreboot folks,
]
]
]I try to get KolibriOS running on the ASRock E350M1 with coreboot and
]SeaBIOS payload. Keyboard and mouse do not work [1] probably because
]KolibriOS needs PIC mode.
]
]Was somebody successful in getting KolibriOS working on a board with
]coreboot?
mrnuke [mailto:mr.nuke...@gmail.com] wrote:
]It's changing the ROM base (devfn 14.3, register 0x6c) from 0xffc0 to 0xff00.
]The bootblock sets it up correctly, but AmdInitReset messes it up.
]
]Any ideas? AGESA is particularly annoying to grep.
]
]Alex
It is probably 102 of
Allen Yan [mailto:lex...@gmail.com] wrote:
]Oh, sorry, incorrect address!
]http://www.google-]melange.com/gsoc/proposal/public/google/gsoc2014/jinyiyan/5629499534213120
]
]TianoCore as Coreboot payload
]JinyiYan
]
]Short description: The combination of coreboot + TianoCore
]is the most
陈军根 [mailto:c...@bolod.net] wrote:
]Hello Rudolf:
]
]Because coreboot can't work in F2A85-MLE, I buy a new mainboard
]f2a85-M,and coreboot can run ok in my f2a85-m, also can boot
]ubuntu.But I find a strange question: when I plug my DIMM in
]DIMM_A1 or DIMM_B1, coreboot can't work, and get the
Rostislav Lisovy [mailto:lis...@gmail.com] wrote:
]On Sun, 2014-03-02 at 00:00 -0600, Scott Duplichan wrote:
] This looks like a divide exception. Finding the source code
] for the failing divide might help narrow down the problem. I
] can't recreate your binary exactly so I can't find
Rostislav Lisovy [mailto:lis...@gmail.com] wrote:
]Hello;
]I am trying to run coreboot on F2A85-M motherboard (without VGA support
]enabled). The CPU used is AMD Trinity A8-5600K, RAM is Kingston HyperX
]PnP 4GB (2x2GB) DDR3 1866
](http://www.kingston.com/datasheets/KHX1866C11D3P1K2_4G.pdf).
]
]I
HacKurx [mailto:hack...@gmail.com] wrote:
] David wrote:
] With just 1 stick in the A1 slot, please post a pastebin of the console
] output.
]
]Perfect! It is perfectly detailed, the cpu is not recognized:
]http://pastebin.com/2Lbew82b
you could try adding your cupid to the list in
HacKurx [mailto:hack...@gmail.com] wrote:
]Thank you for adding this great feature that I hope will be added by
]default in Kconfig.
]Unfortunately, this option has no more help me to solve my problem
]with the richland architecture.
Your board is probably crashing at line 252 of file:
mrnuke [mailto:mr.nuke...@gmail.com] wrote:
]On Thursday, January 23, 2014 10:59:21 PM Paul Menzel wrote:
] Do you also know if GRUB 2 does not fulfill one of these requirements?
]
]GRUB2 doesn't meet several requirements that vendors usually have:
]* must be crappily coded (ignoring the GNU
https://intel.taleo.net/careersection/1/jobdetail.ftl?job=725464
Thanks,
Scott
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
the job done. Microsoft has UEFI.
Thanks,
Scott
]If you are not at liberty to discuss these kinds of details, it's fine.
]
]David
]
]On Thu, Jan 9, 2014 at 7:37 AM, Scott Duplichan sc...@notabs.org wrote:
]
]https://intel.taleo.net/careersection/1/jobdetail.ftl?job=725464
]
]Thanks,
]Scott
ron minnich [mailto:rminn...@gmail.com] wrote:
]A number of us used bochs years ago for coreboot debugging. IIRC it
]just worked when we tried it.
]
]ron
I remember in 2008 when a guy named Kevin proposed changing the
bochs bios from asm code to C code because the build environment
for the asm
Scott Duplichan [mailto:sc...@notabs.org] wrote:
]The UEFI payload project I have been working on is usable now,
]though it has been tested on a single board only (ASRock E350M1).
I updated this payload project so that coreboot modifications are
no longer needed. Now the payload is added using
mrnuke [mailto:mr.nuke...@gmail.com] wrote:
]Hi all,
]
]Following some recent discussions on IRC, we've see that some people
]just don't like us shipping microcode in the main repository. OK,
]microcode is a blob, so it belongs in blobs. Let's leave that at that.
De-blobing agesa is going to be
The UEFI payload project I have been working on is usable now,
though it has been tested on a single board only (ASRock E350M1).
In a few days I will setup an AMD family 10h board and try it there.
Though true flash-backed NVRAM support has not been added yet,
it is quite usable with the emulated
]Patrick Georgi wrote:
]
]Am Freitag, den 06.12.2013, 10:04 -0600 schrieb Scott Duplichan:
] The payload has been tested with major UEFI capable operating systems
] (Ubuntu 13.10, Windows 7, Windows 8.1) on real E350M1 hardware and
] it is working well.
]
] http://notabs.org/coreboot/duet-payload
Anthony Ross wrote:
]Hello There,
]
]There has been no response to my last mentioned problem
](Seabios floppy mechanism) DUET freeze. So also could
]anyone look up the code to execute DUET as a coreboot payload.
]
]Regards...
]
]Neo.
Hello,
The attachment you sent on
Patrick Georgi wrote:
]Am 2013-11-06 14:55, schrieb Scott Duplichan:
] ]We had that 4 years ago or so. Want me to look up the code?
]
] Yes, I would be interested to see how others approach it,
] though I have the payload support working now.
]I'll take a look, but it can take some days
Patrick Georgi wrote:
]Am 2013-11-06 00:28, schrieb Scott Duplichan:
] I am working on a project to allow Duet to run as a
] coreboot payload, and to fix the major Duet problems.
]We had that 4 years ago or so. Want me to look up the code?
Yes, I would be interested to see how others approach
not see its debug messages.
You could would step through the code of PlatformBdsInit
to see why the messages from UpdateMemoryMap() are not displayed.
Thanks,
Scott
]
]
]Neo...
]
]
](Attached serial log)
]
]
]
]
]On Wed, Nov 6, 2013 at 4:58 AM, Scott Duplichan spambuc...@notabs.org wrote
on real hardware though.
Thanks,
Scott
On Sat, Oct 26, 2013 at 8:01 PM, Kevin O'Connor ke...@koconnor.net wrote:
On Thu, Oct 24, 2013 at 12:17:33AM -0500, Scott Duplichan wrote:
Scott Duplichan wrote:
..snip..
]I have no experience with making SeaBIOS boot an embedded floppy
]image. I may
overcome
Windows build problems that have crept into both SeaBIOS and coreboot.
Thanks,
Scott
On Wed, Oct 23, 2013 at 1:00 AM, Scott Duplichan spambuc...@notabs.org wrote:
Neo wrote:
]Hello
]
] There has been no response to my thread [Help required to initialize
]coreboot
Christoph Grenz wrote:
]Hello,
]
]I'm currently experimenting with an Attro G5G100-P industrial board.
]
]According to the documentation the chipset is an Intel i915GM with
]an Intel 82801FBM southbridge (which flashrom shows as ICH6-M).
]Inteltool only shows:
] Northbridge: 8086:2590
Mark Mc wrote:
...
] Is there any way to exclude crossgcc for compiling for armv7?
...
Try launching buildgcc directly with no arguments. i386-elf is the default
target.
Lines 5 and 10 of util/crossgcc/Makefile are where the ARM builds are
triggered.
Thanks,
Scott
--
coreboot mailing list:
]2013/5/6 Wim Vervoorn wvervo...@eltan.com:
] Hello,
]
]
]
] I am trying to build CoreBoot from Windows using MingGW.
]
]
]
] After downloading the latest version of the complete package to enable
] this it is possible to build this without problem.
]
]
]
] As this package contains an old version
Andrew Goodbody wrote:
]
] b) When the board arrives...
] 1) Boot MSDOS and start DOS debug
] 2) At the - prompt, enter these commands:
]-n vga.bin
]-rbx
]-1
]-w
] 3) The option rom is vga.bin in the current directory.
]
] Thanks,
] Scott
]
]a) is
Prakash Punnoor wrote:
]BTW, could you explain what happens after soft_reset? Will coreboot run
]again from start?
Yes, the CF9 soft reset starts execution at the reset vector
same as a cold boot.
] At least the following die(...) statement (romstage.c
]cache_as_ram_main) suggests that
mopz0506 wrote:
]Hi,
]
]My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800.
]
]I want the machine to restart once I connect the power cable to
]it, without press the POWER button on the front panel.
]...
I worked on a similar problem a wile back, though I don't
remember if it was with
Kevin O'Connor wrote:
]On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote:
]
] Hi,
]
] is there any solution for the usb boot issue of the AMD SB800 Persimmon
]platform
] with SeaBIOS 1.6.3 and actual Coreboot version?
]
]I'm unfamiliar with the issue. Can you post the
Peter Stuge wrote:
] // write to AMD 8131 Link Command Register BUID field (bits 16-20)
] // with value 2 so that the 8111 can be accessed:
] -epcid 0 0 0 c0 00420008 // bus 0, dev 0, fun 0, reg 0xc0
]
]Is it safe to blindly write this word in
]src/northbridge/amd/amdfam10/bootblock.c ? I think
Patrick Georgi wrote:
]Am Freitag, 23. September 2011 01:45:09 schrieb Oskar Enoksson:
] As for the dead behaviour in recent versions I bisected my way down
] to commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That
] commit adds TINY_BOOTBLOCK support to AMD-8111 southbridge. I
]
Marshall Buschman wrote:
...
]Hello Kerry:
]
]I have tested your patch set, and it does make the E350M1 boot.
]The bad news is there is now a delay of approximately 5 minutes and 20
]seconds before any serial output is displayed.
]
]The coreboot log is available at
be sure to enable AHCI when building SeaBIOS.
]Regards,
]Carl-Daniel
Am 17.08.2011 01:08 schrieb Scott Duplichan:
Carl-Daniel Hailfinger wrote:
]does anyone have a working ASRock E350M1 coreboot image with SeaBIOS?
]I hope to demo that board this weekend at the FrOSCon conference.
Here
Pete Batard wrote:
]Also, if it's not too much to ask and if the code works without
]FORCE_PANIC, I wouldn't mind finding out where it breaks if not using
]the 48 MHz init (using forced base/type/ldn).
]
]I have now committed your patch to svn. Will still need to figure out
]what the best
Pete Batard wrote:
]Hi Scott,
]
]With my apologies for the delay, I have just pushed an updated version
]of ubrx to svn. It includes SB8x0 48 MHz Clk1 init, the ability to
]provide of SIO base, type and UART LDN, as well as additional DIAG codes
]to help with the troubleshooting.
]
]If you
Pete Batard wrote:
]...
]Right now, I am especially interested in tests being conducted on AMD
]hardware to confirm that the AMD LCP/SouthBridge init works. Again, you
]should be able to test UBRX even if your platform is not supported by
]coreboot, provided of course that you can reflash your
The attached patch moves the AMD SB800 early clock setup code that is
needed for early serial port operation from mainboard/romstage.c to
sb800/bootblock.c. This prevents code duplication and simplifies porting.
Signed-off-by: Scott Duplichan sc...@notabs.org
sb800-bblk.patch
Description
Tadas Slotkus wrote:
] Just to completely rule out the bad SPD idea, can you please dump the
] SPD content when you boot with the production BIOS? i2cdump output
] (ASCII) or raw output from sysfs would be great. Then we can plug it
] into bc and confirm that the checksum is correct. This would
Tadas Slotkus wrote:
]Hi,
]
]just compiled coreboot for e350m1, flashed original flashchip and got
]this (log attached) everytime I power on or reset my system. Any hints?
Hello Tadas,
AMD.h shows EventClass = 2 corresponds to AGESA_BOUNDS_CHK, a warning
that does not prevent booting. This is
Stefan Reinauer wrote:
]On 7/2/11 2:08 PM, Rudolf Marek wrote:
] Hi,
]
] Yes even 486 would be good fit! (It has more closer aligns etc). As
] Stefan mentioned, some CPU might not have SSE enabled failing to
] execute coreboot. Maybe this is a bit broader problem.
]
] Thanks
] Rudolf
]
]Note
Patrick Georgi wrote:
]Am Donnerstag, 23. Juni 2011 03:20:05, Cristian Măgherușan-Stanciu
]schrieb:
] SetEnvIf Request_URI \.gz$ no-gzip
]I had to disable it unconditionally for all of gitweb (REQUEST_URI
]matches the request url without the query string), but it looks okay
]for me now.
]
Stefan Tauner wrote:
] Hello,
]
] Is there a way to download an archived snapshot of recent coreboot source
] code?
]
]gitweb can create snapshots on the fly.
]i am not sure if the gitweb integration is completed so YMMV.
]http://review.coreboot.org/gitweb?p=coreboot.git;a=summary
This is
Marc Jones wrote:
]Hi Scott,
]
]On Fri, Jun 17, 2011 at 10:26 PM, Scott Duplichan sc...@notabs.org wrote:
] The attached patch allows the asrock e350m1 onboard nic to work.
] 1) Update the asrock e350m1 devicetree.cb to match the hardware.
] 2) Change the way the sb800 cimx wrapper code works
Marshall Buschman wrote:
]Hello:
]
]The built-in sound on the ASRock E350M1 works properly.
]Could someone please update the wiki page accordingly?
]
]Also, a wiki account would be nice if possible.
Hello Marshall,
I did the wiki update.
Marshall Buschman wrote:
]Hello:
]
]With Scott's work on PCIe support for the E350M1, the NIC and USB3 are
]now working -- Thanks Scott!
Thanks for testing it on both the boards. Good to hear it works.
]The remaining problems that I know of are:
]
]1) Enabling coreboot serial debugging slows
Marshall Buschman wrote:
]Nevermind, it works - Apparently there are disadvantages to doing things
]that require thought in the very early hours of the morning. :|
]Thanks!
Hello Marshall,
Thanks for the update. I tested Win7 with this change and 4GB and found
it is not happy. Win7 makes a
Peter Stuge wrote:
] If you can send me a binary or otherwise let me recreate the serial
] logging problem, I will take a look.
]
]http://stuge.se/stuge_e350m1_47b3fb_4mb.bin
Hello Peter,
Thanks. This shows the problem on my board. I have not been in
the habit of enabling kconfig option
Marshall Buschman wrote:
]I own both boards - both do work, BUT there are still bugs:
]USB3 and built-in NIC do not work on either by default.
]Memory is only reported as roughly 512mb at this point.
]
]You're welcome to help. :)
Hello Marshall,
Thanks for reporting these problems. Incorrect
. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.
Signed-off-by: Scott Duplichan
Stefan Tauner wrote:
] Hello,
]
] Is there a way to download an archived snapshot of recent coreboot source
] code?
]
]gitweb can create snapshots on the fly.
]i am not sure if the gitweb integration is completed so YMMV.
]http://review.coreboot.org/gitweb?p=coreboot.git;a=summary
Hello Stefan,
Hello,
Is there a way to download an archived snapshot of recent coreboot source
code?
Thanks,
Scott
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Omar-Mohammad Ataya wrote:
]HOSTCC util/romcc/romcc (this may take a while)
]/home/omar/coreboot/util/romcc/romcc.c: In Funktion »raw_next_token«:
]/home/omar/coreboot/util/romcc/romcc.c:4083:7: Warnung: Variable »wchar«
]gesetzt, aber nicht verwendet [-Wunused-but-set-variable]
Hello Omar,
Marshall Buschman wrote:
]Marc:
]
]After taking a quick look through the git log, it looks like we've
]probably applied all of the patches you mentioned to me besides these:
]
]Move SB800 clock init earlier to fix problem where initial serial port
]output is garbled.
]Skip memory clear for boot
Peter Stuge wrote:
]All are either
]
]Acked-by: Peter Stuge pe...@stuge.se
]
]or
]
]Acked-by: Marshall Buschman mbusch...@lucidmachines.com
]
]per IRC. Committed as r6621 to r6636.
]
]Many thanks to Scott for these fixes to amd/persimmon, and to
]Marshall for working on getting them over to
Stefan Reinauer wrote:
] + // early enable of SPI 33 MHz fast mode read
] + if (boot_cpu())
] +{
] +volatile u32 *spiBase = (void *) 0xa000;
] +u32 save;
] +__outdword (0xcf8, 0x8000a3a0);
]
]what's the reason to not use pci_read_config32() here?
Hello Stefan,
It was due
AMD F14 persimmon and e350m1: replace inline cf8/cfc pci config
access with pci_read_config and pci_write_config function calls.
Signed-off-by: Scott Duplichan sc...@notabs.org
Index: src/mainboard/amd/persimmon/romstage.c
Stefan Reinauer wrote:
]Also, enabling Prefetch and 33MHz fast read mode should possibly go in the
]southbridge's bootblock.c so the first cbfs scan does not run with the
]slow settings.
Hello Stefan,
You are probably right. In fact these settings are applied fairly early
even without the
Stefan Reinauer wrote:
] + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot
]time
] + __writemsr (0xc0010062, 0);
] +
]
]why not use writemsr instead of __writemsr?
Hello Stefan,
The wrmsr function is certainly OK. I am in the habit us using the
Intel/MS functions because
Marshall Buschman wrote:
]Hello:
]
]I was instructed to send mail to you by Carebear from #coreboot.
]I have some issues to report based on the Golden Image I received from
]him, which was created for the ASRock E350M1.
]
]After booting, my Linux kernel panics like this:
C.L. wrote:
]Hello, all
]I found that grub could be used as a coreboot payload at coreboot
]website, but no more detail messages.
]Can anyone give me some advices?
]I alse found there were great resource at http://grub.enbug.org, but I
]can not open it, the other people around me
]can not open it
Stefan Reinauer wrote:
] + .align 4
] Shouldn't this be .align 16 then?
] The as(1) info page says it's in bits on x86.
]
] Jonathan Kollasch
]
]Oh does it? This used to be only the case for i386 + a.out. It seems at
]least the coreboot reference compiler assumes those are bytes.
It's
Stefan Reinauer wrote:
] Why would the resource allocator have to worry about posted vs
] non-posted PCI transactions?
] How else will the northbridge be told to make the region non-posted?
]Why would it have to? Not sure I understand your concern. Your patch
]does not address that issue at all.
Mark Marshall wrote:
] +__outdword (0xcf8, 0x8000a3b8);
] +__outdword (0xcfc, __indword (0xcfc) | 0 24);
]
]Isn't this a no-op (or'ing 0 into the read value and writing it back)?
]
]MM
Hello Mark,
Thanks for point this out. You are certainly correct. This
was left over from a test of
,
of one of the ACPI tables.
Tested on Persimmon. Others abuild tested only.
Signed-off-by: Scott Duplichan sc...@notabs.org
]It looks like src/mainboard/amd/mahogany/acpi_tables.c has a double
]paste issue. Fix that and it looks good.
]
]Acked-by: Marc Jones marcj...@gmail.com
]
]
]Marc
Hello Marc
.
Tested on Persimmon. Others abuild tested only.
Signed-off-by: Scott Duplichan sc...@notabs.org
Detailed explanation: The error message is displayed when a 1024 dword
page table array used by setupldr runs out of space. This table is used
for mapping various physical addresses, such as those
Idwer Vollering wtote:
]Have you though of using an USB flash drive, to install Windows from?
]http://www.windowsvalley.com/install-windows-2000-xp-2003-using-usb-]storag
e-device-pen-drive/
Hello Idwer,
Thanks for the suggestion and information. That could be useful in
situations where no CD
Anders Jenbo wrote:
]You could use http://driverpacks.net/ to incorporate the AHCI driveres
]on your cd.
Hello Anders,
Thanks for the suggestion. I did find that site the other day. At first
it looked like what I needed. But when I went to choose a download, I
I could find x64 packs only for
Marc Jones wrote:
]Hi Scott,
]
]I'm acking and committing all except the LTO patch, which should wait
]for the crossgcc changes for gcc4.6. i only made a minor tweak to the
]AHCI patch to add a #define for the PCI DID.
Thanks Marc. I noticed the PCI ID also, how embarrassing! I will test
Peter Stuge wrote:
] +__outdword (0xcf8, 0x8000a3b8);
] +__outdword (0xcfc, __indword (0xcfc) | 0 24);
] +}
]
]PCI function? And maybe this, as well as the 33MHz setup, is good to
]have in the chipset code, as opposed to duplicated per mainboard?
Hello Peter,
I will try improve
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