[coreboot] Re: There is a python in our toolchain?!?

On Wed, Sep 29, 2021 at 7:44 AM Jack Rosenthal wrote: > Overall I think introducing Python to the build would provide net benefit, > mainly from Kconfiglib, but could also find other good uses in e2e tests > like Ricardo was working on. Most people's Linux distros ship with a Python >

[coreboot] Re: What should we do about freenode IRC services?

On Tue, May 25, 2021 at 6:01 AM Patrick Georgi via coreboot < coreboot@coreboot.org> wrote: > Hi everybody, > > you might have heard that freenode.org recently changed management under > weird circumstances. Given that we use their services for our project > chat, this concerns us as well. > > In

[coreboot] Re: Native RAM init

Alif, you will need the System Agent source code from Intel to produce a mrc.bin for Cedarview. Given that the platform is from 2011, there's not much point in spending the effort though. Stefan On Fri, Oct 30, 2020 at 3:21 AM Alif Ilhan wrote: > hello, > Is there a way to extract mrc.bin

[coreboot] Re: What are splitted / several flash ROMs about?

Yes, this is often done as a cost reduction method. The habit started with the arrival of the ME and the firmware descriptor allowing you to spread your different firmware regions across one or both chips. The tool ifdtool will help you analyze images for Intel firmware descriptors. Sounds like in

[coreboot] Re: Does NSA contribute to Coreboot?

Remember that the project was started by Los Alamos National Labs (LANL), the guys that also brought you the Manhattan Project.Contributions have also been made by the BSI (German version of the NSA) and their contractors.On 22 Jun 2019 21:30, Anac wrote:Dear all, Is it true that there's code

[coreboot] Re: More coding style change proposals

On 20 Jun 2019 08:26, ron minnich wrote:clang-format is not a textual preprocessor. It is basically the ast builder of followed by output. So in your case, I just tried it main() {   if (foo)     bar();     baz(); } and got the right thing, i.e. braces around bar but not baz. The

[coreboot] Re: Chainloading Windows from a Linux Payload

* ron minnich [190611 07:13]: > if you boot windows 12 would you need tianocore? Need is a harsh word, but the simple answer to a simple question is yes, you do. You can use SeaBIOS, but Windows does not officially support legacy BIOS since at least Windows 7, so whatever works today might stop

[coreboot] Re: coreboot leadership meeting minutes for May 8 & May 22

Guys, it is a bit tricky to prevent discussions in a call when someone brings up a topic, and I'm not sure that blocking that is useful. The meetings are open and particularly people commenting here have been invited to the calls. Please make use of that opportunity and join, if you think that you

[coreboot] Re: Can't build (for g505s) with crossgcc-x64 toolchain, builds fine with crossgcc-i386

64bit builds are not supported at this time.StefanOn 15 May 2019 22:27, Mike Banon wrote:Here's a final part of coreboot build log for crossgcc-x64 build attempt. This does not happen while building with crossgcc-i386, so seems to be x64-only problem.     CC romstage/lib/stack.o    

[coreboot] Re: Syntax highlighting screwed up (orange function parameters)?

On 29 Apr 2019 17:46, Julius Werner wrote:> Wanna file a bug at https://bugs.chromium.org/p/gerrit/issues/list ? Are we sure this is a general Gerrit bug? I've not seen the same thing on the Chromium Gerrit so I'm assuming it's specific to the coreboot installation. I've opened a coreboot

[coreboot] Re: Question regarding 7th generation Intel CPUs

Hi Coins, I'm not coreboot, but I'm a part of it, so I will try to answer your question. CCing the coreboot mailing list for more input, as I can only assume that that list was the intended recipient for your email. It is unproven that Intel deliberately builds in backdoors into their CPUs.

[coreboot] Re: mailing list changes

Great work, Patrick. And thank you for spending your holidays on this special gift for all of us in the coreboot community!StefanOn Dec 25, 2018 07:40, Patrick Georgi via coreboot wrote:Hi everybody,I took the opportunity of the slow season to make some changes to the mail server configuration:

Re: [coreboot] Why do we have FSP-S

* Timothy Pearson [180501 04:58]: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA256 > > All the ARM64 boards I've seen that are desktop or higher class ship > with AMI UEFI and AMI BMC. Plus they contain their own magic blobs, > some akin to the ME. ARM64 is

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

* Paul Menzel [171006 09:43]: > Dear Martin, > > > Am Dienstag, den 03.10.2017, 08:07 -0600 schrieb Martin Roth: > > I'd say that it doesn't make sense to require that coreboot builds > > with anything other than the coreboot toolchain. > > Additionally, It

Re: [coreboot] vboot/futility: Two Clang 5 warnings: address-of-packed-member and enum-conversion

Dear Paul, * Paul Menzel [171007 11:05]: > Dear coreboot folks, > > > Clang 5.0 shows the warnings below. I don’t know if Clang 4.0 also > warns about these. > > ``` > CCfirmware/lib/vboot_api_kernel.o >

Re: [coreboot] AGESA fam15 code removals

* Martin Roth via coreboot [171005 19:00]: > I've got very mixed feelings about pushing the changes that we know aren't > going to work, especially right before we abandon the boards to a branch. We are not abandoning any boards. The whole reason we are doing branches and

Re: [coreboot] Does coreboot table still exist in F000 segment?

* WANG FEI [171013 20:20]: > Hi, all > > Beside placing coreboot table (lb_header) in low RAM (0x0-0x1000), I remember > a > copy of coreboot table should be placed at F000 segment and it can be > controlled with a Kconfig flag, does this feature still exist? I just

Re: [coreboot] Discussion about fixing dead code / ACPI TRAP

On 01-Jul-17 06:20, Patrick Rudolph wrote: Hello community, I'll want to start a discussion about fixing dead code. How it all started: I tried to run docking code on Lenovo T400 and found it's not working. While investigation it turns out that the ACPI TRAP mechanism is being used, and that

Re: [coreboot] question on SMM

On 30-Jun-17 10:46, ron minnich wrote: Thanks for the good explanations. So I have a question for you all. We've been doing some testing of linux-as-ramstage. We've done a proof of concept that linux can set up the SMM handler at 0xa, the relocate stub at 0x38000, run the relocate

Re: [coreboot] more smm questions

On 03-Jul-17 10:01, ron minnich wrote: I've got a question right at this code: https://github.com/coreboot/coreboot/blob/fec0328c5f653233859d4aec7dae0b94acb67e97/src/cpu/x86/smm/smmrelocate.S#L101 /* Check revision to see if AMD64 style SMM_BASE * Intel Core Solo/Duo: 0x30007 * Intel

Re: [coreboot] FILO 0.6.0 payload bootloader - Bug Reports!

On Tue, Jun 13, 2017 at 10:33 AM Ivan Ivanov wrote: > === If you have some ideas about one or more of FILO problems, please tell > === > > %%% 1st problem - FILO is impossible to build on the modern x86_64 > system (Ubuntu 16.04.2 LTS with gcc 5.4.0) : > ... > CC

Re: [coreboot] Please revert change of List-Id

On 04/07/2017 01:01 AM, Paul Menzel via coreboot wrote: > Dear coreboot server list administrators, > > > It looks like the List-Id of the lists provided by the coreboot server > – at least coreboot, flashrom, SeaBIOS – changed from > > List-Id: coreboot project mailing list > > to > > List-Id:

Re: [coreboot] How come the community meeting is hosted by proprietary software?

* Peter Stuge [170317 14:27]: > Patrick Georgi via coreboot wrote: > > 2017-03-17 13:17 GMT+01:00 Dumitru Ursu : > > > I never tried the web interface. > > > > We did, it failed us. > > I wish someone would have mentioned that sooner. > > What problems did

Re: [coreboot] How come the community meeting is hosted by proprietary software?

* taii...@gmx.com [170317 23:35]: > I believe it needs fixing - It is a philosophical issue, I mean you have to > draw the line or you get the slippery slope for "just a little non-free here > for convenience just this once" has lead to most of the community thinking > that a

Re: [coreboot] SPI Flash Writeprotect

* John Lewis [170227 10:38]: > Hi Naveed, > > It's probably the MRC cache or something like that, which IIRC you can > disable. This is correct. Unfortunately, if you disable the MRC cache you will lose functionality like the ability to resume from S3 suspend, and your

Re: [coreboot] No external PCIe GPU possible/working on Gigabyte g41m-es2l

* i1w5d7gf38...@tutanota.com [170226 21:59]: > Hardware: Gigabyte g41m-es2l, latest coreboot git, latest seabios git, two > nvidia gpu cards tested > > I tried to use some external GPU on a g41m-es2l to get some digial screen > output. It does not seem to work. When

Re: [coreboot] payload coreinfo - no button press works

Hello anonymous, * i1w5d7gf38...@tutanota.com [170226 21:23]: > Hardware: g41m-es2l, latest coreboot git, latest seabios git, native vga, ps2 > keyboard + usb keyboard > > I liked to try out coreinfo. It show the CPU Information page at start. When i > then press

Re: [coreboot] How to reduce formal issues with new contributions from corporations?

* Paul Menzel via coreboot [170226 14:37]: > Dear coreboot folks, [..] > My impression is though, that a lot of these contributions have formal > issues in the beginning. As the coding style and the commit message > guide lines are well documented in our Wiki [1][2], and

Re: [coreboot] REACTS Pricing Changes

* Timothy Pearson [170111 23:38]: > When you purchase a REACTS license, you are helping us continue to > maintain and improve the only publicly available CI hardware testing > solution for coreboot. The only other one besides this one, which has been available

[coreboot] PSA: abandoning old patches (again)

Hi, we're planning (as we have done in the past), to abandon patches that have been crowding up gerrit without any update in the last 18 months. The list of patches in question is https://review.coreboot.org/#/q/status:open+age:18months If you want to preserve any of those patches, please

Re: [coreboot] Stops at 0xD2

* Riko Ho [161026 03:36]: > Everyone, > > I tried to initialize UART on IT8718F and it stopped at 0xD2... > Here's the complete function, any clues ? Yes, there is a halt() right after the post_code(0xd2); so that is where your last post code is coming from. use

Re: [coreboot] i946GZ test

* Riko Ho [161019 06:29]: > Hello everyone.. > >  I've put W39F040FCPZ on the board...but I can not see any messages on > serial... > I can hear tuck tuck on motherboard buzzardrepeatedly > > command : sudo putty /dev/ttyUSB0 -serial -sercfg 115200,8,n,1,N on the

Re: [coreboot] Microcode question ?

* Riko Ho [161017 02:18]: > Is it ok if I'm not including microcode updates ? It might, or might not. On the i945/946 it probably is ok. A lot of modern CPUs can't boot successfully anymore without loading microcode. Stefan -- coreboot mailing list:

Re: [coreboot] WY1200LE with coreboot

* Riko Ho [161018 09:31]: > Everyone, > > Does coreboot suport WY1200LE? it's using AMD geode, and I can't access its > BIOS...directly to windows and no BIOS key access .. AMD Geode GX support has been dropped a while ago. Older versions of coreboot will support the

Re: [coreboot] ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ?

* Riko Ho [161018 14:29]: > Everyone, > Does this line use port on 0x3F8 ? It uses whatever you configured for CONFIG_TTYS0_BASE in your .config. Stefan -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] W39V040FB and W39V040FC?

* Antonius Riko [161016 07:38]: > Everyone, > > Is W39V040FB compatible with W39V040FC ? > Cheers That depends on your uyse case. They have different erase block sizes. >From the data sheets: The W39V040FC is a 4-megabit, 3.3-volt only CMOS flash memory organized as

Re: [coreboot] [coreboot-announce] SHORT NOTICE: coreboot.berlin next weekend, Oct. 7-9

Have fun, folks! Wish I could be there. Send updates and pictures! Stefan * ron minnich [161001 05:23]: > See you there! I just registered and am really looking forward to seeing > everyone! Thanks Peter! > > ron > > On Fri, Sep 30, 2016 at 9:41 AM Peter Stuge

[coreboot] Welcome to the new coreboot.org!

Hi! As some of you might already have noticed, our new web presence has gone live on https://www.coreboot.org/ today! I want to use this chance to send a big shout out to Philipp Deppenwiese and Martin Roth, and all the others that have been involved in making this moment happen, for their great

Re: [coreboot] initrd in 4.4 versus head

* Trammell Hudson [160727 13:58]: > I see a difference in the way 4.4 handles initrd images for linux > payloads versus the way it is done in head. With 4.4 my Linux > kernel can not find the external initrd, so it is necessary to > build it as part of the kernel. With head it

Re: [coreboot] What is the best way to treat warnings reported by checkpatch.pl

* Julius Werner [160727 23:41]: > > typedef struct dmar_atsr_entry { > >u16 type; > >u16 length; > >u8 flags; > >u8 reserved; > >u16 segment; > > } __attribute__ ((packed)) dmar_atsr_entry_t; > > Looking at the

Re: [coreboot] What is the best way to treat warnings reported by checkpatch.pl

* ron minnich [160727 02:26]: > A couple of questions preceded by the usual curmudgeonly comment :-) > > I'm not a big fan of checkpatch.pl. It's 5965 lines of dense perl spaghetti > code, continues to grow, and is attempting to achieve that which I understand > may be

Re: [coreboot] ARM Trusted Firmware build issue

On 20-Jul-16 16:19, Julius Werner wrote: Well... honestly, isn't it our fault for uprevving to a buggy toolchain? If there was a way to write this code such that it will result in the binary output ARM wants and works on all versions, submitting a patch to them would be reasonable... but

Re: [coreboot] TXE and Descriptor bin management in Coreboot

* Mayuri Tendulkar [160714 00:50]: > Ok, so do we need to ask Intel if we use Intel baytrail processor? How we can > create this descriptor.bin? Please have a look at util/ifdtool and util/ifdfake for our tools dealing with Intel Firmware Descriptors. The most

Re: [coreboot] How to read the gpio status?

* ��?�?��?? [160713 06:39]: > When write 0x7000 write to SC_GP_LVL, Can read the 0x00 from SC_GP_LVL. > everytime. Are you by any chance doing an 8 bit read (0x00) instead of a 16 bit read (0x)? Stefan -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] ARM Trusted Firmware build issue

* Martin Roth [160713 16:57]: > We can't roll the entire toolchain back to binutils 2.25 because of > the RISC-V work. Is it reasonable to roll back to binutils 2.25 for > just the ARM toolchain builds? No, that is not feasible. The cross toolchain builder has seen a fair

[coreboot] A word on releases

Hi people, we have had a great first year with regular coreboot releases. Exactly 12 months ago, we released coreboot 4.1, the first release after the 4.0 release in 2011 and our "classic" branch in 2014. Since then we have had 4 successful releases, both Patrick and Martin went through the

Re: [coreboot] RFC: implementing a way to force external EDID use.

Hi Arthur, * Arthur Heymans [160622 23:34]: > Hi > > In Linux it is possible to load an EDID externally. Coreboot can > currently not do this. Do you think it is worth implementing this > feature? So far we have not come across devices without an EDID or with a bad EDID,

Re: [coreboot] kgpe-d16

* ron minnich [160620 20:19]: > I have a kgpe-d16 with coreboot and it *was* working with linux. I now have a > linux kernel that won't boot on fuctory bios or coreboot. I can't recall > changing anything ... > > If somebody's got a known good .config for linux I could sure

[coreboot] PSA: old coreboot versions now available via git

Hi, the ancient coreboot versions coreboot v1 and coreboot v3 have been recovered from some old svn trees and are now available in the coreboot repository under the branch names "coreboot-v1" and "coreboot-v3". Enjoy, Stefan signature.asc Description: OpenPGP digital signature -- coreboot

[coreboot] Say hi to avatars on review.coreboot.org

Hello coreboot folks, I've played around with gerrit's avatar feature this weekend and as a little gimmick, I have turned on avatars for our gerrit instance at https://review.coreboot.org/ In a never-ending effort to make it harder for everybody in the community to be mad at each other, you will

Re: [coreboot] coreboot specific ACPI table

On 04/18/2016 08:17 PM, Julius Werner wrote: > For comparison, the coreboot device tree interface on ARM > (https://lkml.org/lkml/2014/6/16/622, unfortunately never picked up by > the maintainers but still used on Chromebooks today) only exports > start address and size of the coreboot table and

Re: [coreboot] coreboot specific ACPI table

On 04/22/2016 02:35 PM, Aaron Durbin via coreboot wrote: > 1. coreboot tables base address and size. > 2. console base address and size. > 3. ramoops info. Since ramoops already has its own object in the DSDT, do we want to mention it here? What about other cbmem entries? coverage, timestamps...?

[coreboot] coreboot toolchain update after 4.4 release

Hi folks! We're planning to update the coreboot reference toolchain very soon now, right after the coreboot 4.4 release which will roughly happen at the end of this month. We have fixed a few issues with the new toolchain already, and I am building and running coreboot images with the new

Re: [coreboot] How to deal with Coverity reports?

On 03/14/2016 04:05 PM, Julius Werner wrote: > Is our general goal just to triage or to actually fix (as in: change > code so that they disappear) all Coverity errors? I think it's a great > tool that occasionally really finds that one odd bug, but most of the > issues I've looked at so far seem

Re: [coreboot] Missing Coverity reports

On 03/12/2016 01:51 PM, Paul Menzel wrote: > Dear coreboot folks, > > > does Coverity still check the coreboot code base or have there been > changes? It’d be great to get it going again and to have the errors > fixed in code that is currently committed. > > > Thanks, > > paul There are no

Re: [coreboot] Member list of coreboot leadership

On 03/12/2016 02:02 PM, Paul Menzel wrote: > Dear coreboot folks, > > > neither in the coreboot Wiki [1] nor the repository I was able to find > a list of the members of the so called coreboot leadership. Stefan’s > blog post from May 2015 [2] lists the people below. The group that I get my

Re: [coreboot] Query

Hi Damany, On 03/08/2016 12:00 PM, Damany Reid wrote: Good Day, My name is Damany and I’m new to the area of open source software contributing. I learnt of the opportunities afforded through Google Summer of Code and I’m just wondering if I’m qualified enough to participate in your project.

Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port

y soon) . Let me know how to get started on the same. Regards, Saket Sinha On Mon, Mar 7, 2016 at 4:10 AM, Stefan Reinauer <stefan.reina...@coreboot.org> wrote: Hi Saket! Welcome to coreboot! Please check out our GSoC page at https://www.coreboot.org/GSoC and have a look at our three

Re: [coreboot] Fwd: Aspirant for GSOC 2016 with coreboot for ARM64 qemu port

Hi Saket! Welcome to coreboot! Please check out our GSoC page at https://www.coreboot.org/GSoC and have a look at our three sub projects this year: coreboot, flashrom and SerialICE. If you have specific questions, please don't hesitate to ask. Stefan On 02/29/2016 11:38 AM, Saket Sinha

Re: [coreboot] GSoC 2016

On 03/06/2016 10:35 AM, Tahir Ramzan wrote: Respected Sir, I am a MS CS scholar of Virtual University of Pakistan, I want to participate in GSoC 2016 for coreboot. Data Science, Networks, Information security, digital forensics and ethical hacking are my core areas of interest.

Re: [coreboot] Timestamp

On 03/06/2016 10:36 AM, daoud yessine wrote: Hi how we can get the timestamp from coreboot ? what's the name of table in the source code in which the timestamps are saved ? What is the configuration needed to obtain the timestamp table ? thanks ᐧ TThe timestamps live in an area at the end

Re: [coreboot] Coreboot table

On 03/06/2016 07:50 AM, daoud yessine wrote: Hi I need your help please :) About coreboot table , where is its location in memory ? Its size ? Its contents ? Is it saved in buffer ? The coreboot table typically lives at the end of physical memory in the 4G space (e.g. in "cbmem space").

Re: [coreboot] explore Coreboot,with Doxygen

On 25-Feb-16 08:16, ron minnich wrote: We tried to do Doxygen starting in 2000, but the experiment never seemed to work out. I still like the idea. One result was that you could make documentation and get a manual for the board you were working on at the time. That actually did work for a

Re: [coreboot] [ANNOUNCEMENT] PS/2 devices working on ASRock E350M1

That's great news! Congratulations! Stefan On 13-Feb-16 02:23, Paul Menzel wrote: Dear coreboot folks, just a short thank you to Timothy Pearson from Raptor Engineering [1] for implementing auxiliary channel PS/2 device presence detection in coreboot [2] in commit 448e3863 (drivers/pc80: Add

Re: [coreboot] [RFC] Proposal for policy for changing the development guidelines

* Alex G. [160131 00:05]: > I conclude from these, that your assertion that this has been an > unspoken rule, is not true. Furthermore, I believe that this arbitrary > change was done as an act of spite towards a set of engineers. Also, > since you, and the rest of the

Re: [coreboot] Long boot delay with a large CBFS

* Ben Gardner [151116 19:32]: > [The previous email got chopped. This is a re-send.] > > Hi all, > > I have a 16 MB BIOS flash on a fsp_baytrail based design. > > I tried expanding the CBFS to fill the whole space, but found that to > cause a 10-15 sec boot delay.

Re: [coreboot] setting up a bug tracker

* Alexander Couzens [151110 05:30]: > @Stefan/Patrick Can you create a CName for ticket.coreboot.org -> > coreboot.dtn10.de Done. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Fwd: sgabios ans grub2 payload (without SeaBIOS)

* maxime de Roucy [151105 10:32]: > -- Forwarded message -- > From: maxime de Roucy > Date: 2015-11-05 10:25 GMT+01:00 > Subject: Re: [coreboot] sgabios ans grub2 payload (without SeaBIOS) > To: Gerd Hoffmann

Re: [coreboot] setting up a bug tracker

* Timothy Pearson [151103 20:55]: > Is Bugzilla out of the question? I would like Bugzilla, too. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] setting up a bug tracker

* Patrick Georgi [151105 19:00]: > 2015-11-04 16:57 GMT+01:00 Martin Roth : > > - Are there any required login methods? Does it need to support the > > login types that review.coreboot.org supports? > redmine has an omniauth plugin that should allow OpenID

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

* Stefan Reinauer <stefan.reina...@coreboot.org> [151027 21:39]: > I want to add the following boards (and their chipsets and super ios) > that have been in the tree and basically unmaintained for 10+ys: > > * arima/hdama > * digitallogic/adl855pc > * ibm/e325 >

Re: [coreboot] [RFC] Remove empty mainboard.c files up for review

* Paul Menzel [151109 23:42]: > Dear coreboot folks, > > I pushed change set I379e4b1e1b1725648c6231bc6954ac3cc655a596 > (mainboard: Remove empty mainboard.c files) [1] for review. > > ``` > mainboard: Remove empty mainboard.c files > > All the deleted

Re: [coreboot] A case for branching AGESA

* Alex G. [151101 21:29]: > Except for VX900 and sandybridge, every chipset implements its own SPD > parsing routines. Gee, let's keep VX900 around then, it's one of the few good examples ;) > Alex Stefan -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Coreboot hackaton 2016 (proposal in Paris)

* David Hendricks [151102 21:00]: > Piggybacking on other conferences can certainly help overseas travellers. Are > there other major conferences later in the year? > > Hosting after FOSDEM 2016 actually seems ideal and it will be in Brussels (<2 > hours away by train, or <1

Re: [coreboot] coreboot binary policy

* Alex Gagniuc [151030 18:59]: > On Fri, Oct 30, 2015 at 9:03 AM, Marc Jones wrote: > > It might be a good idea, but that might be too limiting > > I think historically, it has been assumed that everything in blobs is > open up for RE and modification.

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

* Aaron Durbin [151028 14:52]: > > Various improvements and important bug fixes, that will be introduced to a > > master branch and affect all the coreboot boards, will not be automatically > > applied to that separate AMD branch. Those coreboot developers which have > > AMD

Re: [coreboot] GPL license headers

>From my previous discussions with lawyers on the topic, the third paragraph is unproblematic to remove. With resolutions of today's monitors and keyboards often having a page down key, keeping the second paragraph seems like a good compromise to stay friends with the legal experts and err on the

Re: [coreboot] steps before screen mods

* Mario Goljak [150925 16:06]: > Hi guys, > > I just came across thinkpad forum thread where people are discuss about > hardware mods for getting FHD screen on lenovo x220/x230 laptops. > http://forum.thinkpads.com/viewtopic.php?f=43=106919=90 >   > What do you guys think, will

Re: [coreboot] Broadwell IGD (on Auron_Paine)

* Georg Wicherski [151019 17:39]: > Hi, > > thanks to Marc Jones' SGD patch for the Auron board > (f3214d02482a4104d7276f06d6b326b2a54c4262), I was able to get my > Auron_Paine up to ramstage. > > Unfortunately, the IGD code in soc/intel/broadwell/ appears to be > somewhat

Re: [coreboot] [help]build cbfstool fail with cygwin64

I think switching to c99 per default is a great idea. The problem below should be fixed by http://review.coreboot.org/#/c/11666/ and the following patch. Stefan On Oct 19, 2015, Julius Werner wrote: >> is there anyway to dynamic define std to gnu99 when detect build with

Re: [coreboot] Acer Chromebook 15 debug

* John Lewis [150830 18:43]: > Hi Guys, > > Coolstar Organisation wants to do his Windows thang with one of the > Broadwell Chromebooks, so I'm trying to build a working ROM with > chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B > to give

Re: [coreboot] i855GM on laptop - possible or not?

Hi Andrey, * Andrey Korolyov and...@xdel.ru [150802 22:22]: I am trying to estimate amount of effort to make an old military Getac to work with coreboot (currently it runs Insyde with computrace-style code). All currently supported boards, lanner/em8510 and digitallogic/adl855pc are desktops,

Re: [coreboot] cbfs alignment

* ron minnich rminn...@gmail.com [150717 21:45]: riscv is taking alignment traps reading cbfs. The issue is that 64-bit fields are 32-bit aligned, which fails many places. Thaminda found this comment:    * Since coreboot is usually compiled 32bit, gcc will align 64bit   types to 32bit

Re: [coreboot] How to trigger SMI and implement SMM

* Yu-Cheng Liu peter90...@gmail.com [150721 11:04]: Hello, I purpose to trigger SMI event and do something in SMM mode .   I trace the coreboot source code and found that, during the coreboot environment setup, the file locate at southbridge/intel/i82801ix/smi.c  will be excute. Is

Re: [coreboot] Finding whether the BIOS is coreboot or not

* ron minnich rminn...@gmail.com [150718 18:10]: Could you also look for LBIO in the e and f segments? Since we moved the coreboot tables out of e and f you won't find anything like that anymore. 1. Use cbmem tool 2. Dump coreboot table with nvramtool 3. dmidecode 4. ACPI table vendor 5.

Re: [coreboot] No code in SMM handler address (0xa0000)

* Yu-Cheng Liu peter90...@gmail.com [150724 09:13]: hello, Here I have some questions in smi.c file (coreboot/src/southbridge/intel/ i82801ix/smi.c) in smm_install function, one statement is to copy handler to SMRAM(0xa): 1.I can't find copy source data ( _binary_smm_start ),where is it

Re: [coreboot] Flashrom won't work with DediProg SF100 fw 6.5.03

* Steve Goodrich steve.goodr...@se-eng.com [150602 20:38]: I got the Chromium version of flashrom to work, but it takes 20 minutes to flash/verify the 8 MB device.  So, while working is far better than not working, it is a bit sluggish.  :-) I seem to remember there are two ways flashrom can

Re: [coreboot] Cbfstool compilation error with gcc 5.1

* Anatol Pomozov anatol.pomo...@gmail.com [150531 08:49]: Hi I am trying to compile coreboot cbfstool on Arch where gcc 5.1 is used. And I see following compilation error. I wonder if it is coreboot or gcc issue. == Starting build()... make: Entering directory

Re: [coreboot] coreboot community chat (request for feedback)

we can improve the meeting. Thanks, Stefan On 2015-05-06 21:05, Stefan Reinauer wrote: Hi coreboot community! In order to have more face time and a more personal connection with each other than it is possible on the coreboot IRC channel, I would like to invite you to participate in a monthly

Re: [coreboot] coreboot community chat

Quick reminder: This is coming up tomorrow (about 18h from now) Looking forward to seeing you all Stefan * Stefan Reinauer stefan.reina...@coreboot.org [150507 06:05]: Hi coreboot community! In order to have more face time and a more personal connection with each other than it is possible

Re: [coreboot] [poll] device_t

* ron minnich rminn...@gmail.com [150507 21:35]: one counter-question: is romcc ever going away, or at least is the usage gong to change such that no code would ever use the uint32 version of device_t?  If it's *never* going away then I think the change makes no sense. If romcc

[coreboot] [poll] device_t

Since Edward started hijacking patches on gerrit to push his agenda of getting rid of device_t without prior discussion, I would like to start a poll on how people think about this, and maybe find reasons for why it might be a good idea. Edward wrote: The issue of 'device_t' has many heads. The

[coreboot] coreboot community chat

Hi coreboot community! In order to have more face time and a more personal connection with each other than it is possible on the coreboot IRC channel, I would like to invite you to participate in a monthly video conference to discuss the up and coming projects, ideas and issues that all of us are

Re: [coreboot] [Announcement] Please rebuild utility cbmem after new addition of time stamps

* Paul Menzel paulepan...@users.sourceforge.net [150423 22:43]: With old cbmem: 15:starting LZMA decompress (ignore for x86) 238,557 (211) 16:finished LZMA decompress (ignore for x86) 255,012 (16,454) After rebuilding cbmem: 12 entries total: 15:unknown

Re: [coreboot] Question on VGA BIOS extraction

* Iru Cai mytbk920...@gmail.com [150330 18:24]: Hi, I'm trying to build Coreboot for ThinkPad X220. I first backup the vendor BIOS, then use UEFITool to extract a VBIOS. The romheader program detects the ROM's PCI data structure and reports the device id is 8086:0106, but the VGA

Re: [coreboot] GCC update broke AMD Fam10h boot

* Aaron Durbin adur...@chromium.org [150316 22:44]: A quick hack is add ALIGN(32) to the linker script before _bs_init_begin: src/arch/x86/ramstage.ld But I think we'll need to store pointers to the structures in order to properly handle the situation where the compiler is effectively making

Re: [coreboot] Hello coreboot

Hi Łukasz, * Łukasz Dmitrowski lukasz.dmitrow...@gmail.com [150314 10:23]: My name is Lukasz and I am a Computer Science student at West Pomeranian University of Technology in Szczecin. Main area of my interests are embedded systems and for me coreboot is the most interesting organization in

[coreboot] coreboot meeting this summer!

Hey folks! the coreboot meeting in Prague last year was a great success, and I suggest that we have a get together this year. To alternate between continents, I would like to organize a coreboot project meeting in San Jose, California this summer. I have talked to a few people, and it seems that

Re: [coreboot] questions about google/samus

Hi Anthony, * Anthony Martin al...@pbrane.org [150312 23:27]: - Does it use the usual depthcharge payload with an internal write-protect switch for flashing the firmware? There's no boot guard shenanigans going on, correct? That is correct. Like all Chrome OS devices, Samus (Pixel2) uses

Re: [coreboot] Unifying IO accessor macros

* Julius Werner jwer...@chromium.org [150218 00:12]: I'd like to propose an API change/cleanup for a long-standing problem with architecture-independent code that people have hit and privately discussed/cursed multiple times already, but no one really had time to make the big change/fix yet.

  1   2   3   4   5   6   7   8   9   10   >