* She, Kerry kerry@amd.com [110422 05:13]:
Hello,
RS780 DDI Lanes configure support
Signed-off-by: Kerry She kerry@amd.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
With this list getting longer, it might be nice to:
a) make it a case (eax) { ... } construct
* She, Kerry kerry@amd.com [110422 05:14]:
Hello,
RS780 PCIE GEN2 Software Compliance support
Signed-off-by: Kerry She kerry@amd.com
+ /* set automatic Gen2 support, needs mainboard config option as Gen2
can cause issues on some platforms. */
Yes, I suggest to add
-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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See patch
Add (partly) support for Nuvoton NCT6776F
nuvoton.c | 193 +-
superiotool.h |2
2 files changed, 191 insertions(+), 4 deletions(-)
Signed-off-by: Stefan Reinauer reina...@google.com
Index: nuvoton.c
On 4/21/11 12:53 AM, Bao, Zheng wrote:
Hi, All,
Since we can only access the code tree via a firewall, I need to give
the IP address I need to access to the administrator. But the seabios
git server just seems to have changed, hasn't it? Actually I am pretty
sure it has and I can resolve the IP
See patch
The UART divider should be calculated based on the base frequency
and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/include/uart8250.h
===
--- src
* Jiang Wang jwang...@gmail.com [110422 01:33]:
I am trying to understand how the power button pressing event triggers
the machine to shutdown. From the ACPI spec 4.7.2.2.1, it mentioned
that the power button can be implemented either as a fixed hardware or
a generic hardware programming
On 4/21/11 4:43 PM, Peter Stuge wrote:
Stefan Reinauer wrote:
The UART divider should be calculated based on the base frequency
and baudrate, not hardcoded in addition to that.
Signed-off-by: Stefan Reinauerstefan.reina...@coreboot.org
With some changes pointed out below it's:
Acked
Revised version. See patch.
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.
This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.
Signed-off-by: Stefan Reinauer reina
* Philippe LeCavalier supp...@plecavalier.com [110420 15:07]:
Excerpts from Stefan Reinauer's message of Tue Apr 19 21:30:35 -0400 2011:
* Philippe LeCavalier supp...@plecavalier.com [110419 20:22]:
[..]
If your BIOS works for you, you should consider keeping it.
Porting coreboot to a
* Peter Stuge pe...@stuge.se [110420 18:03]:
+++ trunk/src/mainboard/lenovo/t60/cmos.layout Wed Apr 20 11:12:17
2011(r6530)
@@ -107,6 +107,7 @@
1048 4 r 0C0DRT1
1052 4 r 0C1DRT1
+1060 1 e 1
See patch.
Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an example.
Signed-off-by: Stefan Reinauer reina...@google.com
Index: src/Kconfig
===
--- src/Kconfig (revision 6533)
+++ src/Kconfig (working copy
On Wed, Apr 20, 2011 at 4:59 PM, David Hendricks dhend...@google.com wrote:
On Wed, Apr 20, 2011 at 3:49 PM, Stefan Reinauer reina...@google.com
wrote:
See patch.
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Very cool -- Serial debug
* Jiang Wang jwang...@gmail.com [110419 23:56]:
Hi,
I tried to use an external PCI network card ( 8254pi) with m2v-mx se
mother board. However, the booting process hangs. On the screen, it
shows, Chrome VGA textmode initialized, and stops there.
The serial console output is attached. Is
* Boris Shpoungin wmk...@yahoo.com [110419 23:31]:
Could you recommend any manual which describe coreboot porting process to new
not supported platform? Does it exist at all?
The Wiki is an excellent source of information.
Could you provide rough effort estimate to port coreboot to new
* Philippe LeCavalier supp...@plecavalier.com [110419 20:22]:
Hi All.
Just joined the list to find out your opinion on whether or not I should
put coreboot on my laptop.
First off, what do I gain? I read it's faster but I don't really think
my BIOS is slow. OR is it? Perhaps seeing is
*conf = dev-chip_info;
You should check if dev or conf is actually set before accessing it.
I believe if the device is not mentioned in devicetree.cb conf will be
NULL.
See some i82801gx drivers for an example.
Other than that:
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
* Sven Schnelle sv...@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Sven Schnelle sv...@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
Will that also need a change in the nokia IP530 board's devicetree.cb?
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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http
* Sven Schnelle sv...@stackframe.org [110419 21:47]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
What's the difference?
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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effects to eliminating another indirection.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/include/console/console.h
===
--- src/include/console/console.h (revision 6523)
+++ src/include/console/console.h
* Sven Schnelle sv...@stackframe.org [110418 10:00]:
Stefan Reinauer stefan.reina...@coreboot.org writes:
Can you please put these in a .c or .h file in the mainboard
directory? I don't think we should add configuration variables
for single registers in Kconfig.
Actually i've copied
similar should happen to the uart init:
* uart_init() can go into console.c right now
* superio init should go into a function local_uart_init() defined in
romstage.c and be called from console_init, too.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/southbridge/amd/sb600
* Jiang Wang jwang...@gmail.com [110418 23:38]:
Hi,
I want to use the rtc wake up function on coreboot and Linux on ASUS
M2V MX-SE. I used rtcwake command (ver 2.19) from
ftp://ftp.kernel.org/pub/linux/utils/util-linux-ng/ to automatically
wake up the machine after an S3 sleep. This works
* Peter Stuge pe...@stuge.se [110419 01:15]:
Going forward the question is if a new step should be added to
configuration, where the user can choose the architecture they are
interested in, and that will limit the list of mainboards that can be
selected.
The advantage of this would be that a
Hi
as you probably know, we are using a slightly modified Kconfig that
emits #define CONFIG_FOO 0 for all unset bools in our Kconfig files in
order to avoid nasty checks a la
#if defined(CONFIG_FOO) CONFIG_FOO
However, this modification to Kconfig was incomplete, and so only some
but not
. The following change
bypasses the Do not use global variables in romstage check for
the AMD reference code only.
Signed-off-by: Scott Duplichansc...@notabs.org
I think AMD is working on a fix for this problem. However, until then:
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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On 4/17/11 6:07 AM, Sven Schnelle wrote:
Hi List,
the attached patch adds support for the ThinkPad T60 to
coreboot. it is diffed against the existing X60 port.
Signed-off-by: Sven Schnellesv...@stackframe.org
Index: t60/Kconfig
* Stefan Reinauer stefan.reina...@coreboot.org [110414 23:46]:
See patch
- include usbdebug.c where appropriate
- don't do ne2k_transmit()s without actual output
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Rudolf, you wrote some of the code initially. Can you please take
* Marc Jones marcj...@gmail.com [110415 20:34]:
Can you put something about this card on the wiki. It would be handy
for others that don't have a legacy serial port.
will try to do so
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See patch.
Allow libpayload to use an OXPCIe 952 card on systems without
onboard serial port
Signed-off-by: Stefan Reinauer reina...@google.com
Index: libpayload/include/sysinfo.h
===
--- libpayload/include/sysinfo.h (revision
See patch
- include usbdebug.c where appropriate
- don't do ne2k_transmit()s without actual output
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/include/console/console.h
===
--- src/include/console
* Peter Stuge pe...@stuge.se [110414 23:41]:
repository service wrote:
Date: Thu Apr 14 22:30:21 2011
Log:
- drop remaining CONFIG_ROM_IMAGE_SIZE
Yeah!! I have been looking forward to this for a long long time! :)
Well done!
Thank you! I originally had a much more agressive patch
CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
Build Log:
Compilation of a-trend:atc-6220 has been broken
See the error log at
http://qa.coreboot.org/log_buildbrd.php?revision=6496device
, devicetree.cb cleanup and init_uart8250() removal
will follow once this patch is comitted
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/superio/fintek/f71805f/superio.c
===
--- src/superio/fintek/f71805f/superio.c
See patch
bootblock updates:
- allow CPU to define bootblock code, too.
- drop unneeded __PRE_RAM__ define
- move CBFS specific code out of bootblock_common.h into cbfs.h
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/arch/x86/include/bootblock_common.h
Hi,
just a heads up, I got romcc to segfault with the following sample program:
- 8 snip 8 --
typedef unsigned int u32;
#define DEFAULT_RCBA 0xfed1c000
#define GCS 0x3410
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
void
On 4/12/11 10:05 PM, Russell Whitaker wrote:
On Tue, 12 Apr 2011, Stefan Reinauer wrote:
Hi,
just a heads up, I got romcc to segfault with the following sample
program:
- 8 snip 8 --
typedef unsigned int u32;
#define DEFAULT_RCBA
* Ruud Schramp (DT) schr...@holmes.nl [110411 16:00]:
Hello guys,
I am looking in the sourcecode of the dl145_g3 and noticed IPMI
initialisation there (commented out). It refers a ipmi.c Does anyone
have this code around?
I suggest you get in contact with the original authors.
Stefan
--
* Sven Schnelle sv...@stackframe.org [110410 21:05]:
diff --git a/src/mainboard/emulation/qemu b/src/mainboard/emulation/qemu
new file mode 100644
index 000..d9275b5
--- /dev/null
+++ b/src/mainboard/emulation/qemu
...
+#include southbridge/intel/i82801gx/nvs.h
...
+
* Joesph Czerniak joseph.czern...@gmail.com [110411 22:22]:
Hi,
I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It
has the following specs:
Here are the quick specs (the more detailed specs are at the bottom):
CPU: Intel Atom N550 with an integrated northbridge
see patch
In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: Makefile.inc
* Devel dev...@pas-world.com [110407 16:21]:
Hello,
(Murphy's Law in action!)
Well, I tried to use Coreboot + Seabios in old hp e-vectra.
- Download coreboot.
- Compile coreboot.
- Flash with flashrom.
Seems to be that is not easy, because old e-vectra do not boot.
Please send the
* Ruud Schramp (DT) schr...@holmes.nl [110408 10:21]:
Hi guys,
Do not know how to handle the unknown devices (LDN's) yet. For now I
dump all IO base registers etc for information purposed.
I have identified two LDN's as Serial port; (LDN 0x01 and LDN 0x02)
Best regards,
Ruud
Please stop sending LinkedIn invitations to the coreboot mailing list.
On 4/6/11 11:51 PM, QingPei Wang via LinkedIn wrote:
LinkedIn
QingPei Wang requested to add you as a connection on LinkedIn:
Jerome,
I'd like to add you to my professional network on LinkedIn.
- QingPei Wang
* Paul Menzel paulepan...@users.sourceforge.net [110406 16:25]:
Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo:
Add WIP_ARM config entry so that we can make all ARM-related
entries depend on this now.
We need to make all the ARM-related code available to ALL so that we
can attract
* Hamo hamo...@gmail.com [110406 16:33]:
On Wed, Apr 6, 2011 at 10:25 PM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Am Mittwoch, den 06.04.2011, 20:20 +0800 schrieb Hamo:
Add WIP_ARM config entry so that we can make all ARM-related
entries depend on this now.
We need to make
* Gregg Levine gregg.drw...@gmail.com [110406 18:17]:
On Wed, Apr 6, 2011 at 12:14 PM, Joseph Smith j...@settoplinux.org wrote:
On 04/06/2011 10:46 AM, Alex G. wrote:
On 04/06/2011 05:25 PM, Paul Menzel wrote:
PPS: Is this a good time to move to Git altogether? A mirror already
* Joseph Smith j...@settoplinux.org [110404 01:26]:
On 04/03/2011 02:49 PM, Tadas Slotkus wrote:
Hello,
This is my first patch, so please don't throw stones to me :)
config USB_DISK should somehow depend on libpayload's config USB at
least, but I don't know how to hardcode it, so I make USB
Sven, could you put this in a separate function called by mainboard
enable? e.g. print_ec_version() or some such.
* repository service s...@coreboot.org [110404 14:33]:
Modified: trunk/src/mainboard/lenovo/x60/mainboard.c
* Marc Jones marcj...@gmail.com [110401 21:37]:
Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This
fixes 4GB memory issues.
Signed-off-by: Marc Jones marcj...@gmail.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Idwer Vollering vid...@gmail.com [110401 20:29]:
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
===
--- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474)
* y...@klacno.sk y...@klacno.sk [110401 20:59]:
Hi, I'm working on port coreboot to Asus Eee Box B202
(http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on
Intel d945gclf target.
So far I have console running. Boot halts on sdram initialization before
Extended Mode
* Idwer Vollering vid...@gmail.com [110401 23:00]:
V2.
Signed-off-by: Idwer Vollering vid...@gmail.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
* y...@klacno.sk y...@klacno.sk [110401 20:59]:
Hi, I'm working on port coreboot to Asus Eee Box B202
(http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on
Intel d945gclf target.
So far I have console running. Boot halts on sdram initialization before
Extended Mode
...
Signed-off-by: Stefan Reinauer stefan.reina...@coreboot.org
Index: src/northbridge/intel/i945/early_init.c
===
--- src/northbridge/intel/i945/early_init.c (revision 6474)
+++ src/northbridge/intel/i945/early_init.c (working copy
* y...@klacno.sk y...@klacno.sk [110402 00:13]:
Setting Graphics Frequency...
FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz
Hm.. FSB supports up to 667
Atom N270 supports just 533Mhz
And that's apparently what it is trying to use, too.
Setting Memory Frequency...
/intel/i82801gx/acpi/ich7.asl | 46 ++---
2 files changed, 39 insertions(+), 33 deletions(-)
Thanks for finding this.
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Nathan Williams nat...@traverse.com.au [110331 07:42]:
This patch adds the device id for the Hynix HY27UF081G2A 128MB
NAND flash IC.
Signed-off-by: Nathan Williams nat...@traverse.com.au
thanks. r143
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* Hamo hamo...@gmail.com [110330 02:19]:
Add build instructions for coreinfo, specially pointing out installing
gcc-multilib on a 64bit system.
Signed-off-by: Yang Hamo Bai hamo...@gmail.com
This is the very first time I send a patch to coreboot, any comment is
welcome. Thanks.
Thank
* Nils njaco...@hetnet.nl [110329 21:11]:
Update repo path in libpayload readme.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Thanks, Nils.
Thanks. r6469
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* Keith Hui buu...@gmail.com [110329 06:11]:
+ if ((edosd 0x84) == 0x84) {
+ edosd = 0x10; // Registered SDRAM
+ } else {
+ // Clear [4:3] in case it's EDO.
+ edosd = 0x07;
+// } else if (edosd 0x02) {
Besides being commented out, this piece of code
* Corey Osgood corey.osg...@gmail.com [110328 11:58]:
Sorry, I don't know the specifics on Sandy Bridge, if CAR from the
Core 2s would work or not. You can take a look at other chipsets in
the coreboot source tree to get an idea of what would be required.
Also make sure to read up on Intel's
* sharib khan sharib4...@gmail.com [110328 11:36]:
It is possible for us to get the boot sequence and other required documents
for
these processors.
You will have to get NDAed information from Intel about this.
Could you highlight what are the necessary changes required in coreboot while
On 3/27/11 5:36 AM, Keith Hui wrote:
Adds support for initializing registered SDRAM modules on Intel 440BX
northbridge.
Signed-off-by: Keith Hui buu...@gmail.com
Index: src/northbridge/intel/i440bx/raminit.c
===
---
* Sven Schnelle sv...@stackframe.org [110321 21:52]:
Hi List,
one of the last remaining problems with the ThinkPad X60 port is that
coreboot does a full reset on ACPI S3 wakeup. There's an explicit check
that the DRAM self refresh bits in PMSTS (MCHBAR offset 0xf14) are set.
For (yet)
* Hongyuan Zhu zhuhongy...@gmail.com [110321 12:13]:
When I make, the error messages got below,
src/arch/x86/coreboot_ram.ld:129 cannot move location counter backwards (from
00118000 to 4000)
collect2: ld returned 1 exit status
make: *** [build/coreboot_ram] Error 1
:= $(CONFIG_CMC_FILE)
+cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))
cmc.bin-type := 0xaa
cmc.bin-position := 0xfffd
---
best regards,
2011/3/15 Stefan Reinauer stefan.reina...@coreboot.org:
* Anish Patel anish.mailing.l...@gmail.com [110314 20:42]:
On 03/14/11 15:19
* Bao, Zheng zheng@amd.com [110316 09:38]:
I have \_S4 in my dsdt.asl. But the dmesg only reports:
ACPI: (supports S0 S1 S2 S3 S5)
So what else is needed?
I think you also need to add S4BIOS_REQ in the FADT and implement an SMM
handler to handle it.
You don't need that for software
* Anish Patel anish.mailing.l...@gmail.com [110314 20:42]:
On 03/14/11 15:19, Anish Patel wrote:
Hi All,
I am trying to get coreboot running on my PC/104+ atom board.
I think i have everything pretty much good to go, except for one
problem.
When i try to build, it says it can't find my
* Peter Stuge pe...@stuge.se [110314 10:11]:
repository service wrote:
Added:
trunk/macosx/patches/msrtool-r6440.diff
svn rm:ed this but could not commit to DirectHW. Patch has been
applied upstream.
Commit permissions added.
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line
(eg. make KERNELVERSION='11.03$(REV)') or dropping it entirely if having
that information in the coreboot binary is not desired.
Signed-off-by: Patrick Georgi patrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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* Andrey Zonov and...@zonov.org [110313 16:05]:
Hi,
I'm making FreeBSD port of nvramtool and I don't want to download
full coreboot snapshot to build only nvramtool. Where can I find
snapshots of nvramtool only? If you don't separate that things,
don't you mind if I will make snapshots by
On 3/13/11 8:30 PM, Kevin O'Connor wrote:
Here is how the
how the problem was overcome for coreboot:
http://tracker.coreboot.org/trac/coreboot/changeset/4952
When I add the UNLINK_IF_NECESSARY part of this change, the rename succeeds.
Could seabios adopt this change?
It's possible, but I'd
* Sven Schnelle sv...@stackframe.org [110312 09:23]:
Stefan Reinauer stefan.reina...@coreboot.org writes:
* Sven Schnelle sv...@stackframe.org [110312 01:18]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/ec/acpi/ec.c | 23 ---
src/ec/acpi/ec.h
* Sven Schnelle sv...@stackframe.org [110312 09:16]:
Stefan Reinauer stefan.reina...@coreboot.org writes:
* Sven Schnelle sv...@stackframe.org [110312 01:18]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/mainboard/lenovo/x60/mainboard.c |5 +
1 files changed, 5
On 3/11/11 8:14 PM, Gregg Levine wrote:
Hello!
I imagine it would not practical to throw a Coreboot based event here
in NYC? I've been to the Google NYC Offices before, and it looks, well
good to me.
Although off list I can relate some issues I can't make public.
I don't know of any NYC
* Alex G. mr.nuke...@gmail.com [110310 02:45]:
On 03/10/2011 03:43 AM, Joseph Smith wrote:
Sorry to say Alex, unless someone can with the hardware (at least one
board can confirm) I will have to sit this one out. I know from
developing CAR for both i830 and i810 that things can got wrong
* Sven Schnelle sv...@stackframe.org [110312 01:18]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/mainboard/lenovo/x60/mainboard.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/x60/mainboard.c
* Sven Schnelle sv...@stackframe.org [110312 01:18]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/mainboard/lenovo/x60/mainboard.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/lenovo/x60/mainboard.c
* Sven Schnelle sv...@stackframe.org [110312 01:18]:
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/ec/acpi/ec.c | 23 ---
src/ec/acpi/ec.h |1 +
2 files changed, 17 insertions(+), 7 deletions(-)
I wonder if you want two sets of access functions, like on
* Alex G. mr.nuke...@gmail.com [110312 00:32]:
Umh, the same CAR code is used for all supported Intel CPUs.
No, it's not. It just happens to live in a directory that seems to imply
this. There are quire a number of Intel CPUs that don't work with that
code (Intel Core/Core 2 and Atom being some
* Alex G. mr.nuke...@gmail.com [110309 21:59]:
While the previous two patches were innocently trivial and abuild
tested, this one _will_ break the build for several Socket 604 boards.
We want the build to be broken until we can port those to CAR.
Please provide a patch that does that. Actually
* Keith Hui buu...@gmail.com [110306 02:43]:
Tonight I observed that on my P2B-LS board, my nvidia geforce fx5200
AGP card with 128MB ram, after the first initialization run showing
128MB RAM, reset again showing only 64MB RAM. Is this as simple as a
AGP graphics aperture problem? Or is it
Signed-off-by: Sven Schnellesv...@stackframe.org
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
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http://www.coreboot.org/mailman/listinfo/coreboot
works on CAR boards.
- Always build in cmos.default support on boards that USE_OPTION_TABLE.
Signed-off-by: Patrick Georgipatrick.geo...@secunet.com
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
with some optional comments below
index 895a185..a808cec 100644
--- a/src/arch/x86/include
* Vitaly Chertovskih chert...@gmail.com [110303 20:08]:
Hi!
I'm experiencing some troubles with VGA on notebook Roda RF8. That
notebook's
motherboard and other specification is exact to Roda RK886EX, only the screen
is larger (17'' WXGA 1440x900).
On that week I installed coreboot on
, as I am not subscribed to the coreboot list. Thanks.
Regards,
Michael Karcher
Add National Semiconductors PC87364.
Signed-off-by: Michael Karcher flash...@mkarcher.dialup.fu-berlin.de
Acked-by: Stefan Reinauer stefan.reina...@coreboot.org
--
coreboot mailing list: coreboot@coreboot.org
On 3/3/11 9:46 PM, zxy__1127 wrote:
Hi
I think it's a issue about lvds setting in VGA rom.
You can get the vbios from Intel's web site, and you need to modify it
to fit your screen.
8086/27ae 8086/27a2 just different ID,because your have let the VGA
rom run, so it doesn't matter :-)
It
* Alex G. mr.nuke...@gmail.com [110226 02:35]:
Index: src/include/console/post_codes.h
===
--- src/include/console/post_codes.h (revision 0)
+++ src/include/console/post_codes.h (revision 0)
@@ -0,0 +1,350 @@
+/*
+ * This
* Peter Stuge pe...@stuge.se [110216 14:43]:
Alex G. wrote:
Extended K8T890 driver to include the K8T800 and K8M800 northbridges.
The K8T800 is almost identical to the K8T800Pro, also added to this
patch. The K8T800_OLD is also defined, which is an older version of
the K8T800, but which
* repository service s...@coreboot.org [110301 20:58]:
Author: svens
Date: Tue Mar 1 20:58:15 2011
New Revision: 6420
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6420
Modified: trunk/src/include/device/device.h
* Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net [110302 01:05]:
Auf 02.03.2011 00:40, Joseph Smith schrieb:
On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
* Peter Stugepe...@stuge.se [110216 14:43]:
Alex G. wrote:
Extended K8T890 driver to include the K8T800 and K8M800
Thanks to Peter Stuge for his hint, we are moderating Trac posts now for
all anonymous posts so this should no longer be an issue.
* Joseph Smith j...@settoplinux.org [110302 00:39]:
On 03/01/2011 02:24 PM, coreboot wrote:
#178: Life Insurance - How To Buy Life Insurance Policies
* ali hagigat hagigat...@gmail.com [110301 09:58]:
What is the difference between tiny and big boot block?
In big boot block mode, romstage (and thus ram init) is part of the
boot block. In tiny boot block mode, romstage is an extra file in CBFS.
My second question is that the code of
* Joseph Smith j...@settoplinux.org [110301 10:08]:
On Mon, 28 Feb 2011 18:17:34 -0700, Marc Jones marcj...@gmail.com wrote:
GSoC mentoring org signup starts this week and is due by March 11. I
can take the lead this year, unless someone else would like to do it.
If we are accepted (I
* Anders Jenbo and...@jenbo.dk [110301 07:27]:
Wondered if you guys have seen this:
http://www.h-online.com/open/news/item/Intel-releases-GRUB-based-BIOS-test-suite-1197828.html
Did anyone work on getting this to work on coreboot?
Stefan
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coreboot mailing list: coreboot@coreboot.org
On 3/1/11 11:05 PM, Carl-Daniel Hailfinger wrote:
Auf 02.03.2011 01:08, Stefan Reinauer schrieb:
* Carl-Daniel Hailfingerc-d.hailfinger.devel.2...@gmx.net [110302 01:05]:
Auf 02.03.2011 00:40, Joseph Smith schrieb:
On 03/01/2011 04:14 PM, Stefan Reinauer wrote:
* Peter Stugepe
On 3/1/11 8:30 PM, Keith Hui wrote:
---
First, Mysterious breakage on experimental i82371eb ACPI stuff
Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
series of boards:
I'm seeing mysterious compiler breakge after updating my local copy to
r6424. I copied that from P2B to
On 3/1/11 5:47 PM, zxy__1127 wrote:
*发 件人：* Keith Hui
*发 送时间：* 2011-03-02 00:32:50
*收 件人：* coreboot@coreboot.org
*抄 送：*
*主 题：* Re: [coreboot] how to deal with large romstage size?
Hi all,
After I add some memory initialisize code, the romstage is over 64K
byte,and tne code can't run
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