Re: [coreboot] [commit] r5600 - in trunk/src: cpu/x86/smm southbridge/intel/i82801dx southbridge/intel/i82801gx

On 6/1/10 8:41 AM, Peter Stuge wrote: We don't want the value at *(number of bytes), which is what we'd get without the dereference. Without the *reference* - right? How about this then? Maybe both for start and size. extern unsigned char _binary_smm_size[]; Might work... It would

[coreboot] [PATCH] superiotool support for Fintek F81216

NA NA NA -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On 6/1/10 2:54 PM, Alex Buell wrote: I've just downloaded and built SeaBIOS ready to use with CoreBoot on my old MSI 6119 motherboard. Unfortunately, CoreBoot is stopping with a build error in src/lib/uart8250.c with an undeclared CONFIG_TTYS0_BASE error on line 83. I have checked and serial

Re: [coreboot] Trying to build MSI 6119 coreboot BIOS

On 6/1/10 5:47 PM, Alex Buell wrote: OK, thanks for that one, I've now built CoreBoot and flashed it onto my MSI 6119 motherboard. Using serial console I can see the following core-boot-4.0-r5601 Tue Jun 1 14:41:35 BST 2010 starting... SMBus controller enabled Nothing else? Can you

Re: [coreboot] nVidia CK804 + AMD Fam 10 + Winbond Super I/O

/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Selfboot error checking fix

Watson myle...@gmail.com Thanks, Myles Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [PATCH] MCP55 azalia driver

for all of them. Stefan Fix for Azalia/HDA on MCP55, this time for all boards. Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/southbridge/nvidia/mcp55/Makefile.inc === --- src/southbridge/nvidia/mcp55/Makefile.inc

Re: [coreboot] SIS630ET coreboot challenge

On 5/31/10 2:38 AM, Tiago Marques wrote: SiS is mostly dead nowadays. Might be hard, no? Looks very much alive ...? http://www.sis.com/contact/contact.htm Stefan Tiago On Mon, May 24, 2010 at 9:04 PM, Stefan Reinauer stefan.reina...@coresystems.de mailto:stefan.reina...@coresystems.de

Re: [coreboot] Patch for Nokia-IP530, now with working PIRQ table, patch on 5591

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Re: [coreboot] Intel microcode update script

On 5/27/10 3:50 AM, Keith Hui wrote: A question. How is one supposed to make use of this script? $ cd src/cpu/intel/microcode $ sh update-microcode.sh Then you cd to your CPU model directory and check what's there. As part of my effort to re-enable L2 cache on SECC Pentium 2/3s I'd also

Re: [coreboot] Wyse S10 Information

On 5/26/10 6:34 PM, Oliver Schinagl wrote: Strings was interesting enough. I changed the IP, something that might seem like a password and hostnames; just in case. So to me a big portion of the ICA information is still located in the flashrom; e.g. WyseOS definitely resides in the bios area

Re: [coreboot] [PATCH] Improve i82830 MBI SMI Handler - take 2

reading your patch and it seems the name fields need to be properly aligned. I created this patch. Can you try and see if it helps, please? Stefan MBI name field alignment Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/northbridge/intel/i82830/i82830_smihandler.c

Re: [coreboot] [PATCH] AMD MMCONF Support

: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] AMD MMCONF Support

these changes. Comments? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr

Re: [coreboot] [PATCH] Support for HP DL165g6 Fam10

/dl165_g6_fam10/bootblock.inc] Error 1 -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr

Re: [coreboot] SeaBIOS and hp dl145g3

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[coreboot] [PATCH] wipe GPL incompatible code

until someone writes a free version. Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656

Re: [coreboot] [PATCH] AMD MMCONF Support

-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] AMD MMCONF Support

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[coreboot] [PATCH] update microcode script

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Update

Re: [coreboot] Patch for Nokia-IP530, now with working PIRQ table

Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] Wyse S10 and coreboot

On 5/23/10 11:38 PM, Peter Stuge wrote: Oliver Schinagl wrote: Ah, I thought GPLvsa would be the sameas OpenVSA; I don't think I'll want AMD vsa I guess, so I'll go with gplvsa for now :) The file named amd is just a slightly older version of the same code. It used to be redistributable

Re: [coreboot] [commit] r5586 - in trunk/src: console cpu/intel/model_106cx cpu/intel/model_6bx cpu/intel/model_6ex cpu/intel/model_6fx include lib mainboard/getac/p470 mainboard/gigabyte/ga_2761gxdk

Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Patch for Nokia-IP530, now with working PIRQ table

Marc, something went very wrong with this patch. Please try again. See comments below. On 5/25/10 6:20 PM, mbertens wrote: Index: src/mainboard/Kconfig === --- src/mainboard/Kconfig (revision 5583) +++ src/mainboard/Kconfig

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

• http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Welcome coreboot developer blogs

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Re: [coreboot] [PATCH] Fix typo in r5543 Change real mode API...

On 5/23/10 10:55 PM, Michael Marineau wrote: The value of AX magically transformed from 0x4f14 to 0x4f1f Doh! The attach patch fixes the three new C functions back to the original value, this fixes VGA for me. Hi Michael, thanks a lot for finding my mistake :-) I committed your fix.

Re: [coreboot] SIS630ET coreboot challenge

-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] [PATCH] Improve i82830 MBI SMI Handler

On 5/21/10 7:25 AM, Joseph Smith wrote: This patch improves the i82830 MBI SMI Handler. It is now able to load Intel vbios VBT and Flexaim modules. Build and boot tested. Signed-off-by: Joseph Smith j...@settoplinux.org God catch... However, please don't commit this... it breaks the

Re: [coreboot] sony vgn-fz21n support

On 5/20/10 4:09 AM, ahmet alper parker wrote: I know it is still not easy to support laptops, but is it possible to support coreboot on my vaio vgn-fz21m now? Best Regards... Details: Probably the motherboard is cited as: PCG-391M

Re: [coreboot] [commit] r5571 - trunk/util/crossgcc

On 5/19/10 12:01 PM, repository service wrote: Author: stepan Date: Wed May 19 12:01:37 2010 New Revision: 5571 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5571 Log: The AMD Fam10 code breaks with coreboot 4.5.0. Potentially caused by reordering. Going back to 4.4.4 which is

Re: [coreboot] [PATCH] mkelfImage: set kernel_alignment so 2.6.31+ work

Awesome! Acked-by: Stefan Reinauer ste...@coresystems.de On 19.05.2010, at 13:42, ebied...@xmission.com (Eric W. Biederman) wrote: The kernel initialization code as of boot protocol 2.10 is now reading the kernel_alignment field. With the field left the kernel attempts to align

Re: [coreboot] gPXE not found?!

Knut, try putting the southbridge on bus 0 On 19.05.2010, at 15:15, Myles Watson myle...@gmail.com wrote: On Wed, May 19, 2010 at 1:30 AM, Knut Kujat kn...@gap.upv.es wrote: Hi, using genroms/gpxe.rom makes gPXE start but then gPXE isn't able to find the network devices. When I'm using

Re: [coreboot] Will coreboot work on this system?

Hi Unfortunately no(t yet).. New chipsets are usually a few person months development effort, so it will probably not happen unless someone makes it a business case. Stefan On 19.05.2010, at 13:05, Maarten van Malland maarte...@flowtraders.com wrote: Hello, We're looking into

Re: [coreboot] Ãf¥ââ,¬ÂºÃ ¾ÃfÂ¥Ã,¤ : Advice how to install Linux to get it w orking with FILO

On 5/19/10 4:31 PM, Joop Boonen wrote: On Wed, May 19, 2010 3:54 pm, Myles Watson wrote: On Wed, May 19, 2010 8:52 am, Qing Pei Wang wrote: hi Joop, From the log, the filo worked fine. it can detect the hard disk,load kernel. But the kernel crashes. i do not not much about why

[coreboot] [PATCH] FILO 2.6.31

Hi, I cleaned up the structures used for Linux booting in FILO, to match what Linux uses these days and moved the structure definitions to a separate (include) file. Also fill in 16MB alignment to fix 2.6.31.. untested... Best regards, Stefan Signed-off-by: Stefan Reinauer ste...@coresystems.de

[coreboot] [PATCH] iasl fixes

Latest iasl has a lot more checks on the asl code than previous versions. This hits our code mostly in those parts that are changed on the fly by the asl itself. So most of the code didn't really cause issues. Stefan This patch fixes compilation with the latest iasl. Signed-off-by: Stefan

Re: [coreboot] Advice needed about payload when only usingLinux. (FILO, GRUB2?)

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Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH][again] 440BX raminit cleanup

? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list

Re: [coreboot] libpayload on systems without TSC

On 5/17/10 1:04 PM, bifferos wrote: Hi, I specifically asked if there might be any interest in this patch: http://www.mail-archive.com/coreboot@coreboot.org/msg21191.html I got some feedback on the implementation: http://www.mail-archive.com/coreboot@coreboot.org/msg21196.html Then I

Re: [coreboot] [PATCH] update reference tool chain

On 5/17/10 3:00 AM, Carl-Daniel Hailfinger wrote: On 16.05.2010 21:45, Patrick Georgi wrote: Am 14.05.2010 19:19, schrieb Stefan Reinauer: See patch +GCC_VERSION=4.4.4 +GCC_VERSION=4.5.0 # enable for Link Time Optimization Co That's supposed to be a user option

Re: [coreboot] [PATCH] Enable compatible mod on SIL3114

: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Enable compatible mod on SIL3114

should rename the directory, then so that it's easier for people to match the option with the directory? Anyways, it helps solve the issue, so it should go in... Acked-by: Stefan Reinauer ste...@coresystems.de Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [PATCH] Support for TI xx12 cardbus bridge

On 5/14/10 10:13 PM, Myles Watson wrote: It looks like the generic cardbus ops would have worked for you (a little less debugging output, though). Are you planning on adding more later, or should we consider just using the default? Acked-by: Myles Watson myle...@gmail.com The device

Re: [coreboot] [PATCH] make AMD CAR disable a C function

as it is in Linux Kernel. Seems that if this is missing, GCC is too smart and messes the order of reads/writes to CR0 (not tested if really a problem here, but be safe for future users of this function ;) Signed-off-by: Rudolf Marek r.ma...@assembler.cz Acked-by: Stefan Reinauer ste

Re: [coreboot] [PATCH] make AMD CAR disable a C function

On 5/16/10 7:50 PM, Kevin O'Connor wrote: The AMD disable_cache_as_ram can be C code, but the other architectures can not. It would be nice if there was a single calling convention for this capability across architectures. Maybe something like: void __regparm(3) __noreturn disable_car(void

Re: [coreboot] [commit] r5525 - in trunk: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/a

On 5/14/10 11:42 PM, Uwe Hermann wrote: On Wed, May 05, 2010 at 03:12:42PM +0200, repository service wrote: Modified: trunk/src/mainboard/a-trend/atc-6220/devicetree.cb == ---

[coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

This patch should fix the hda interrupt lost problem on the Wyse S50 Move CS5535 specific setup from GX2 driver to CS5535. To apply this patch you need to cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/ Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src

Re: [coreboot] [PATCH] watchdog mcp55's codec initialization loops

.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo

[coreboot] [PATCH] update reference tool chain

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Update

Re: [coreboot] License changes

On 5/14/10 7:17 PM, Uwe Hermann wrote: On Fri, May 14, 2010 at 11:48:07AM +0200, repository service wrote: Author: stepan Date: Fri May 14 11:48:05 2010 New Revision: 5545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 Log: license header fixes Please don't do

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

On 5/14/10 7:57 PM, Nils wrote: Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50 Hi Stefan, Thanks for making this patch. :) Unfortunately i have no time today to test it, maybe tomorrow evening. I quickly browsed the

Re: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

On 5/14/10 8:09 PM, Peter Stuge wrote: repository service wrote: Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The whitespace changes in this commit made it difficult to see what was actually changed. :\ Check out the link that comes with the mails:

[coreboot] [PATCH] Support for TI xx12 cardbus bridge

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add TI

[coreboot] [PATCH] support for two SMSC superios

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add two

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

• http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [ANNOUNCE] Getac P470 notebook support

) A big thank you also goes to everyone who worked with coresystems on this project. Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht

Re: [coreboot] [PATCH] watchdog mcp55's codec initialization loops

• http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 (Potential) Fix for Azalia/HDA on MCP55 Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/mainboard/supermicro/h8dme/hda_verb.h

Re: [coreboot] [PATCH] watchdog mcp55's codec initialization loops

On 5/13/10 5:08 PM, Joe Korty wrote: On Thu, May 13, 2010 at 10:42:40AM -0400, Stefan Reinauer wrote: the MCP55 azalia init code is kind of crude. I fixed the code for ICH7 a while ago and now I ported my version of the Azalia code to MCP55 / H8DME (assuming that's the board target you use

Re: [coreboot] problem compiling Coreboot+SeaBIOS+VGA BIOS

Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where?

On 5/9/10 7:33 AM, Keith Hui wrote: Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly. Question is: Where should I port this code

Re: [coreboot] PATCH: IT8671F Select CLKIN

On 5/9/10 1:49 AM, Anders Jenbo wrote: Ok done. -Anders Please send a Signed-off-by: so we can commit this http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]Move includes to files that actually use them

for this patch), making it easier to support new boards. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many

On 5/8/10 11:48 PM, Patrick Georgi wrote: Am 08.05.2010 23:40, schrieb Stefan Reinauer: On 5/8/10 10:59 PM, Patrick Georgi wrote: Index: src/include/lib.h === --- src/include/lib.h (Revision 5532) +++ src/include

Re: [coreboot] FILO bug disk not seen at ata-0 (Doesn't try to detect on ATA only SIL3114)

On 5/7/10 10:37 PM, Joop Boonen wrote: On Thu, May 6, 2010 11:56 am, Joop Boonen wrote: On Thu, May 6, 2010 11:35 am, Joop Boonen wrote: All, I have an issue with FILO the disk at ata-0 isn't seen. I've been trying some more. I've used the old IDE in FILO. It now

Re: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many

in. But how should we handle things in case of other conditions? Acked-by: Stefan Reinauer ste...@coresystems.de Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [commit] r5530 - trunk

On 5/8/10 5:50 PM, repository service wrote: Modified: trunk/Makefile == --- trunk/MakefileSat May 8 13:17:24 2010(r5529) +++ trunk/MakefileSat May 8 17:50:44 2010(r5530) @@ -368,12 +368,12

Re: [coreboot] [PATCH]Include headers instead of sources in romstage, part 1/many

On 5/8/10 5:56 PM, Kevin O'Connor wrote: I think coreboot should try to avoid using .a files. The latest version of gcc (v4.5) contains the -flto feature. This can provide significant benefits to coreboot code generation because it allows the entire romstage (and ramstage) to be analyzed as

[coreboot] [PATCH] improve realmode api

. Factor out and improve BDA setup, do some rom segment setup for those option roms that need it. Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/devices/oprom/x86.c === --- src/devices/oprom/x86.c (revision 5530

Re: [coreboot] [PATCH]Include headers instead of sources in romstage, part 2/many

On 5/8/10 10:59 PM, Patrick Georgi wrote: Index: src/include/lib.h === --- src/include/lib.h (Revision 5532) +++ src/include/lib.h (Arbeitskopie) @@ -49,5 +49,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long

Re: [coreboot] [PATCH] improve realmode api

Hey Nils, can you confirm r5470 works with your board? If so, could you send me a complete boot log with that revision, please? Which board was that again? Which VSM module are you using? Stefan On 5/8/10 11:15 PM, Nils wrote: Hi Stefan, I tested your patch in the hope that my Geode GX2

Re: [coreboot] GX2 problems

On 5/1/10 1:58 AM, Nils wrote: Index: src/northbridge/amd/gx2/northbridgeinit.c === --- src/northbridge/amd/gx2/northbridgeinit.c (revision 5520) +++ src/northbridge/amd/gx2/northbridgeinit.c (working copy) @@ -672,7 +672,7 @@

Re: [coreboot] [PATCH] improve realmode api

On 5/8/10 11:59 PM, Nils wrote: Hi Stefan, After trying all VSA`s i could find on the net back in last December, no one was working. So i hacked up my own. How? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] improve realmode api

On 5/9/10 12:46 AM, Nils wrote: I brought back the GX2 code in to the code at: svn://coreboot.org/vsa/trunk/gplvsa2 The biggest chunk of code doesn`t affect the LX code. The resulting LX image is binary compatible with the old one. But a few lines have to be selected for GX2 only. I wanted

Re: [coreboot] Warnings

On 5/9/10 12:52 AM, Nils wrote: Op zondag 9 mei 2010 00:36:49 schreef u: On 5/1/10 1:34 AM, Nils wrote: Hi Stefan, First of all thanks for the great improvements in Geode (GX2). On 4/30/10 7:50 PM, Stefan Reinauer wrote: src/northbridge/amd/gx2/chipsetinit.c:271: warning

Re: [coreboot] [PATCH] improve realmode api

On 5/9/10 12:57 AM, Nils wrote: Op zondag 9 mei 2010 00:41:06 schreef u: Attached a log from rev5470. cool thanks... could you send one for 5471 too, please? Due to a bug in the code there were two functions called chipsetinit() and coreboot was using the wrong one but

Re: [coreboot] [PATCH]Make parser state local to parser

results for all boards. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]Improve sconfig parser

sconfig. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH]rename apic to lapic in device trees

...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards

On 5/4/10 10:07 AM, Nathan Williams wrote: Signed-off-by: Nathan Williams nat...@traverse.com.au - device pci 1.0 on end - device pci 1.1 on end + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device

Re: [coreboot] H8QME-2+ boot problems on different machines.

On 5/3/10 12:59 AM, Rudolf Marek wrote: Hi, There is a plenty of bugs as in all modern CPUs ;) http://support.amd.com/us/Processor_TechDocs/41322.pdf Quick look to coreboot shows they are not handled? Some are easy to fix just to set some MSR, some are microcode fixes. Thanks Rudolf I

Re: [coreboot] [PATCH] Fix coreboot qemu RAM size detection

On 5/2/10 6:23 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. Fix attached. Tested from 16 MiB to 2047 MiB Signed-off-by: Valdimir 'φ-coder'

Re: [coreboot] [PATCH] Fix coreboot qemu RAM size detection

On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. Fix attached. Tested from 16 MiB to 2047 MiB Hi Vladimir, please sign off your patch so we can commit it:

Re: [coreboot] r5511 broke my compile

On 4/30/10 6:25 AM, Keith Hui wrote: $ make GENbuild.h ROMCC romstage.inc GENcrt0.S CC mainboard/asus/p2b-ls/crt0.s CC mainboard/asus/p2b-ls/crt0.initobj.o LINK coreboot OBJCOPYcoreboot.bootblock make: *** No rule

Re: [coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems

Hi Edwin, I know it's a while back but it looks like this patch is not really doing what it says because c - f were ram_resource'd before, too. Just with a separate call. Did this not work? I think we do this in many places. Stefan On 1/27/10 6:17 PM, Edwin Beasant wrote: This patch

Re: [coreboot] H8QME-2+ boot problems on different machines.

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Re: [coreboot] Warnings

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Re: [coreboot] Warnings

casts. So I guess I was wrong. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Stefan Reinauer ste...@coresystems.de -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http

Re: [coreboot] I'm not able to extract the VGA BIOS from phoenix BIOS

• Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot

Re: [coreboot] [PATCH] RAMTOP fixes

On 10/16/09 7:33 PM, Myles Watson wrote: I think we should clean up memory allocation. There are multiple places in the code where RAMTOP is used as an offset into ram and cast to a struct. Maybe that's because the author of that code assumed that this area of memory would be free to use. And

Re: [coreboot] [PATCH] RAMTOP fixes

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Re: [coreboot] [PATCH] RAMTOP fixes

On 4/27/10 6:50 PM, Myles Watson wrote: For suspend/resume I think we like to keep RAMTOP-RAMBASE = 1M. Last time I checked, some of the fam10 boards are using RAMBASE=2M and RAMTOP=16M. Once you start allowing 48 cores and you want page tables on all of their stacks, it gets big quickly.

Re: [coreboot] Patch for enableing 440BX NB to use large memory modules

on the other. Becomes two sides with 128MB (a 256MB module). This is also enabled in at least some BIOSs (GA-BXC). The patch also cleans up some whitespace. Signed-off-by: Anders Jenbo and...@jenbo.dk I like this... no hardware to test though... Acked-by: Stefan Reinauer ste...@coresystems.de

Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)

On 4/26/10 3:55 AM, Idwer Vollering wrote: Generally your fadt looks a bit off, still: +fadt-sci_int = 9; // APM_CNT This is not APM control but the sci interrupt +fadt-smi_cmd = 0; smi_cmd means smi command port ? yes -- coreboot mailing list:

Re: [coreboot] EP80579 reference platform

Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org

Re: [coreboot] EP80579 reference platform

-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] EP80579 reference platform

Eric, do you have a hint what could cause romcc to produce incorrect code without -fno-simplify-phi ? Stefan On 4/26/10 4:23 PM, Myles Watson wrote: On Mon, Apr 26, 2010 at 7:43 AM, Stefan Reinauer ste...@coresystems.de wrote: On 4/26/10 3:34 PM, Myles Watson wrote: The problem

Re: [coreboot] Patch for enableing 440BX NB to use large memory modules

. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] [commit] r5503 - trunk

• Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot

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