Hi!
Things should settle down some after Christmas, so I'll see what I can
do to pull the old D16 dev platform back out at that time and start
testing / merging patches. Are there any others that I should also help
take a look at?
Arthur pushed a new version of your patch #19820 and since it
petecb via coreboot wrote:
> Well the good news is that I have now got this board to work with
> Coreboot v4.6 with the CMOS options and SeaBIOS! :-)
>
> The bad news is that this obviously means a bug has crept in on the
> way up to 4.8
The best news is that you can track that down, since you h
Well the good news is that I have now got this board to work with Coreboot v4.6
with the CMOS options and SeaBIOS! :-)
The bad news is that this obviously means a bug has crept in on the way up to
4.8 that prevents this board from working properly whenever the CMOS options
are enabled. :-(
Tha
On 12/07/2018 02:14 PM, petecb via coreboot wrote:
>
> Hi Taiidan,
>
> Thanks for your message.
>
>
>> I am using v4.6 on my system FYI (no reason for me to update) and the
>> only options I have changed are the ones I told you about before...all I
>> can figure is perhaps I have a different ve
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On 12/03/2018 04:35 AM, Felix Held wrote:
> Hi!
>
>
>> No idea why combined mode is the default, it's only useful for OSes from
>> the '90s. It's not about the type of drives (SATA vs PATA) connected but
>> how the SATA controller identifies itself
Hi Taiidan,
Thanks for your message.
> I am using v4.6 on my system FYI (no reason for me to update) and the
> only options I have changed are the ones I told you about before...all I
> can figure is perhaps I have a different version of the SP5100 that
> doesn't have the erratum or something
Maybe try installing a SATA drive to test things?
Worse case maybe disabling the SATA controller would fix it? as you say
you don't need it.
I hope timothy pearson sees this and replies as he would know what to do
to fix it.
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Please keep replies on the list - I will notice them - and like I said I
won't give up until it works :D
I wish you had OpenBMC installed so that I could access your system
remotely and try stuff myself (via VPN and a router IP whitelist for
security ofc)
Did your D16 come with an ASMB4 or ASMB5
Hi Nico
‐‐‐ Original Message ‐‐‐
On Tuesday, December 4, 2018 9:18 AM, Nico Huber wrote:
> On 03.12.18 19:50, petecb via coreboot wrote:
>
> > I have attached a text file with an overview of all the options I have
> > selected with the nconfig utility, on the off-chance someone spots
> >
On 03.12.18 11:35, Felix Held wrote:
>> No idea why combined mode is the default, it's only useful for OSes from
>> the '90s. It's not about the type of drives (SATA vs PATA) connected but
>> how the SATA controller identifies itself to the OS.>
> I agree that the combined mode isn't the best defau
On 03.12.18 19:50, petecb via coreboot wrote:
> I have attached a text file with an overview of all the options I have
> selected with the nconfig utility, on the off-chance someone spots
> something I have done wrong.
Best way to find out is to disable USE_OPTION_TABLE again and leave
everything
Hi Nico,
‐‐‐ Original Message ‐‐‐
On Sunday, December 2, 2018 10:30 PM, Nico Huber wrote:
> Hi Pete,
>
>
> did you have CONFIG_USE_OPTION_TABLE before? If not you potentially have
> changed all settings. The defaults in the cmos.default file don't have
> to be the same defaults that are
Hi!
No idea why combined mode is the default, it's only useful for OSes from
the '90s. It's not about the type of drives (SATA vs PATA) connected but
how the SATA controller identifies itself to the OS.
I agree that the combined mode isn't the best default, but I can't say
that it's totally
On 12/02/2018 05:30 PM, Nico Huber wrote:
> Hi Pete,
>
> On 02.12.18 23:13, petecb via coreboot wrote:
>> As the default SATA setting already appeared correct, I modified the 3
>> additional settings that Taiidan had already indicated worked
>> (memory_speed_boost, 1394 controller and SATA ALPM) s
Hi Pete,
On 02.12.18 23:13, petecb via coreboot wrote:
> As the default SATA setting already appeared correct, I modified the 3
> additional settings that Taiidan had already indicated worked
> (memory_speed_boost, 1394 controller and SATA ALPM) so in my mind I was
> only adjusting one additional
Hi Peter,
Thanks for your message.
I certainly did not mean to waste anyone's time.
The SATA setting that I was initially looking to enable was already set this
way in the default file. Presumably it's only disabled if you don't enable CMOS
settings in the nconfig. As I never came across any d
petecb via coreboot wrote:
> Thank you for all those details. I've now compiled a version with
> the default CMOS settings apart from the following changes
>
> Minimum memory voltage = 1.35v
> experimental_memory_speed_boost enabled
> 1394 controller disabled
> SATA ALPM enabled.
Please do not ev
On 12/02/2018 10:43 AM, Angel Pons wrote:
> Hello,
>
> On Sun, Dec 2, 2018 at 4:07 PM petecb via coreboot
> wrote:
>> Thank you for all those details. I've now compiled a version with the
>> default CMOS settings apart from the following changes
>>
>> Minimum memory voltage = 1.35v
>> experiment
Hello,
On Sun, Dec 2, 2018 at 4:07 PM petecb via coreboot
wrote:
> Thank you for all those details. I've now compiled a version with the default
> CMOS settings apart from the following changes
>
> Minimum memory voltage = 1.35v
> experimental_memory_speed_boost enabled
> 1394 controller disable
Hi,
I never saw any documentation about those CMOS settings so didn't realize they
were available to modify! :-)
Thank you for all those details. I've now compiled a version with the default
CMOS settings apart from the following changes
Minimum memory voltage = 1.35v
experimental_memory_speed
On 12/01/2018 11:56 AM, Nico Huber wrote:
> Hi Pete,
>
> On 01.12.18 17:21, petecb via coreboot wrote:
>> I'm wondering if my problem is related to not having any SATA drives
>> installed? (I just have a PCI-E SSD). It may be the case that the logic
>> to disable combined mode is not getting trigg
Hi Pete,
On 01.12.18 17:21, petecb via coreboot wrote:
> I'm wondering if my problem is related to not having any SATA drives
> installed? (I just have a PCI-E SSD). It may be the case that the logic
> to disable combined mode is not getting triggered in my scenario, yet it
> would do if there was
In addition to the previous info, I have found this code in sata.c, located at
src/southbridge/amd/sb700 :
/* Below is CIM InitSataLateFar */
if (sata_ahci_mode) {
/* Disable combined mode */
byte = pci_read_config8(sm_dev, 0xad);
by
No worries, please find it attached.
This output looks a little more helpful as it contains the line:
AMD-Vi: SP5100 erratum 28 detected, disabling IOMMU.
I've discovered this thread that refers to it:
https://mail.coreboot.org/pipermail/coreboot/2017-November/085440.html
It appears to be an iss
Oops sorry forgot I also need "sudo xl dmesg" from dom0!
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On 11/29/2018 12:33 PM, petecb wrote:
>
> I followed these instructions and found that "ucode=scan" was already present.
But was it actually present in the grub.cfg you are using?
> I also noticed that it had "iommu=no-igfx"
That is an intel thing
> so I changed this to "iommu=on" and rebooted
Hi,
Thank you for your reply. Please see below for my responses to some of your
points.
‐‐‐ Original Message ‐‐‐
On Tuesday, November 27, 2018 10:59 PM, taii...@gmx.com wrote:
> On 11/27/2018 12:12 PM, petecb via coreboot wrote:
>
>
> Looks to be there now.
>
> Here from your serial lo
On 11/27/2018 12:12 PM, petecb via coreboot wrote:
> Hi,
>
> Thanks for your reply.
>
> I have built a version of coreboot with the “use binary only repo” and
> “generate microcode updates from tree”. I presume by selecting “from tree” I
> do not need to fill in the “Mircrocode binary path and
Hi,
Thanks for your reply.
I have built a version of coreboot with the “use binary only repo” and
“generate microcode updates from tree”. I presume by selecting “from tree” I do
not need to fill in the “Mircrocode binary path and filename”.
The output of the make command to build the rom provid
On 11/26/2018 09:15 AM, petecb via coreboot wrote:
> Hi,
>
> I have an Asus KGPE-D16 motherboard I am trying to get working with Coreboot
> and use with Qubes 4. It has a single AMD 6386 CPU and 128Gb DDR3 ECC RAM.
>
> I have successfully cloned the git repository and built the coreboot.rom.
>
Hi,
I have an Asus KGPE-D16 motherboard I am trying to get working with Coreboot
and use with Qubes 4. It has a single AMD 6386 CPU and 128Gb DDR3 ECC RAM.
I have successfully cloned the git repository and built the coreboot.rom.
However when I flash it on to the board and then run the Qubes in
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