Hello Shreesh,
03.05.19 11:35, Shreesh Chhabbi wrote:
> MRC inside FSP is designed this way for reason that Soldered Memory
> will not be replaced on a particular design,
I have little experience with memory-down configurations. But still,
all the boards I know from the coreboot tree, they have
Hello Alexey,
On 02.05.19 22:22, Alexey Borovikov wrote:
> If I understand correctly, when setting up a FSP with memory down, FSP
> does not read the SPD, but waits for the setting as a function parameter.
> If I set memory as DIMM in the FSP, then the FSP will read the SPD from
> the specified
-Original Message-
From: Alexey Borovikov
Sent: Thursday 2 May 2019 21:23
To: coreboot@coreboot.org; Nico Huber
Subject: [coreboot] Re: FSP 1.0: How to configure soldered memory with spd
Hello Nico, thank!
If I understand correctly, when setting up a FSP with memory down, FSP does
?
-Исходное сообщение-
From: Nico Huber
Sent: Thursday, May 02, 2019 5:18 PM
To: Alexey Borovikov ; coreboot@coreboot.org
Subject: Re: [coreboot] FSP 1.0: How to configure soldered memory with spd
Hello Alexey,
On 02.05.19 10:20, Alexey Borovikov wrote:
How to configure the board with soldered
Hello Alexey,
On 02.05.19 10:20, Alexey Borovikov wrote:
> How to configure the board with soldered memory where spd?
> Is there any difference when using a memory controller with soldered memory
> with spd and DIMM?
this really depends on your board design. If the board with SPD follows
the
Thanks.
But it works if the memory down on board and board not have chip SPD. However,
if the board has a SPD, this code does not work.
From: Ranga Rao
Sent: Thursday, May 02, 2019 12:54 PM
To: Alexey Borovikov ; coreboot@coreboot.org
Subject: RE: [coreboot] FSP 1.0: How to configure soldered
Hi Alexey,
For memory down configuration ensure below are enabled/filled in FSP
When a DIMM is having its SPD, the smbus reads the SPD and configures the DIMM
channels
For Memory down below changes are expected
1. UpdData->MemoryDownEnable is enabled
2)
MEMORY_DOWN_DATA
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