Vaibhav,
Thanks for the reply.
I have selected intenal clk sources for both ACLKXCTL and AHCLKXCTL
ACLKXCTL=0x0061
AHCLKXCTL=0x8033
PDIR=0x0A00
ACLKX1 is not produced. The above settings should produce ACLKX1, so that
GBLCTLX can be set. Am I correct?
What are th
Hello All,
I have a EVM6446 board set-up and configured according to the Getting
Started Users Guide.
I am booted from the NAND and mounted to my shared NFS directory on
Linux Host. My question is: how can I copy files from my host to the
EVM hard drive? I want to run an updated Encode demo
Hello,
I want to use the IMGLIB library to implement a basic edge detection
algorithm. The problem is I am not using CCS, and I'm not sure how to
build, or where to include the .lib files for the linker to pick them
up.
So far I have downloaded the library, unzipped and have the imglib_v201
d
Samuel Ortiz writes:
> Hi Kevin,
>
> On Wed, Apr 21, 2010 at 11:23:09AM -0700, Kevin Hilman wrote:
>> Todd Fischer writes:
>>
>> > Add MFD driver for TPS6507x family of multi-function chips. Move TPS6507x
>> > regulator driver from being stand-alone driver to using the MFD TPS6507x
>> > driv
Jayakrishnan,
The bit field in GBLCTL register that you are trying to set is synchronized and
latched by the corresponding clock(ACLKX in your case).
Since you want to use AHCLKX1 as master clk for another device I suspect the
ACLKX is not already running. If you don't have ACLKX externally ge
Hi,All,
I am using the webserver thttpd 2.25b on my DM6446 board, and I found that a
problem abouth it:
When I use the configuration file like this:
*/thttpd -c /opt/dvevm/thttpd.conf *
but the webserver could not
use the config file thttpd.conf and the web page dir could not be set
in the config
Hi Guys,
I'm getting this Warning littered everywhere in my Kernel Bootlog...
(arago-2.6.32-rc2 dm365)
Does anyone understand why the GPIO lib thinks it needs to WARN_ON?
WARN_ON(extra_checks && chip->can_sleep);
Is this just overkill warnings ? or are they legitimate?
--
Kieran
[1.
I want to use AHCLKX1 (from port 1) to be used as master clk for
another device in the system.
But I am not able to set GBLCTL. for port 1
bit= 1<<9;
bit &= 0x1f00;
mcasp_port[port].mcasp_vregs->gblctlx |= bit;
while ((mcasp_port[port].mcasp_vregs->gblctlx & bit) != bit);
In the edma driver, most of the long lines in 'if condition' are
broken after the logical operator '&&' except two instances.
This patch fixes that to bring consistency across the file.
Signed-off-by: Sekhar Nori
---
arch/arm/mach-davinci/dma.c | 12 ++--
1 files changed, 6 insertions
This patch replaces occurences of (1 << x) with
BIT(x) as it makes for much better reading.
Signed-off-by: Sekhar Nori
---
v2: no functional changes from v1, just rebased to latest master
arch/arm/mach-davinci/dma.c | 42 +-
1 files changed, 21 insertio
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