Hi:
Customer want to develop their NFV app based on LTS version. How about
back-porting the mmio patches to LTS version, like 20.11?
On 2021/3/15 22:16, David Marchand wrote:
v10 changes:
- trival fixes in commit message, like > 75 chars
v11 changes:
- commit message fix and change
Aligned Sob and Author to fix the last checkpatch warning.
Series applied to the main branch.
Thanks Huawei and thanks too to revie
On 2021/3/15 18:19, David Marchand wrote:
#else
#define IO_COND(addr, is_pio, is_mmio) do { \
is_mmio; \
} while (0)
#endif
We should not just copy/paste kernel code.
Plus here, this seems a bit overkill.
And there are other parts in thi
With I/O BAR, we get PIO(port-mapped I/O) address.
With MMIO(memory-mapped I/O) BAR, we get mapped virtual address.
We distinguish PIO and MMIO by their address range like how kernel does,
i.e, address below 64K is PIO.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on a
virtio PMD assumes legacy device only supports PIO(port-mapped) BAR
resource. This is wrong. As we need to create lots of devices, adn PIO
resource on x86 is very limited, we expose MMIO(memory-mapped I/O) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and
for all other p
Currently virtio PMD assumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
1) under igb_uio, get PIO address from uio/uio# sysfs attribute, for
instance: /sys/bus/pci/devices/:00:09.0/uio/uio0/portio/port0/start
2) under uio_pci_ge
On 2021/3/6 0:17, chris wrote:
On 2021/3/4 2:47, 谢华伟(此时此刻） wrote:
Actually, igb_uio sysfs attribute exports exactly the same thing as
standard
PCI sysfs, i.e, pci_dev->resource[] in kernel source code
This patch refactors these messy things, and uses standard PCI sysfs
attribute.
On 2021/3/4 2:47, 谢华伟(此时此刻） wrote:
Actually, igb_uio sysfs attribute exports exactly the same thing as standard
PCI sysfs, i.e, pci_dev->resource[] in kernel source code
This patch refactors these messy things, and uses standard PCI sysfs attribute.
Hi David:
My fault. I set vim cc=80,
On 2021/3/4 2:24, Stephen Hemminger wrote:
On Thu, 04 Mar 2021 01:46:50 +0800
"谢华伟(此时此刻）" wrote:
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose MMIO(memo
From: "huawei.xhw"
With I/O BAR, we get PIO(port-mapped I/O) address.
With MMIO(memory-mapped I/O) BAR, we get mapped virtual address.
We distinguish PIO and MMIO by their address range
like how kernel does, i.e, address below 64K is PIO..
ioread/write8/16/32 is provided to access PIO/MMIO.
By th
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address from uio/uio# sysfs attribute
under uio_pci_generic:
for X86, get PIO address from /proc/ioport
virtio PMD assumes legacy device only supports PIO(port-mapped) BAR resource.
This is wrong. As we need to create lots of devices, as PIO resource on x86 is
very limited, we expose MMIO(memory-mapped I/O) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all
other p
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address
like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on arch
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address from uio/uio# sysfs attribute
under uio_pci_generic:
for X86, get PIO address from /proc/ioport
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose MMIO(memory IO) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all
other pci devices. This pa
On 2021/3/2 21:14, David Marchand wrote:
This change is a fix/optimisation.
This is a separate topic from adding MMIO support with x86 ioport.
I would split as a separate patch.
Hi David:
Maybe there is confuse? There is no change. The out/in is added. I don't
remove _p on purpose.
Looking a
Hi David and ferru:
Any other issue integrating this patch?
On 2021/3/2 0:01, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose M
On 2021/2/25 1:52, David Marchand wrote:
On Wed, Feb 24, 2021 at 4:29 PM 谢华伟(此时此刻） wrote:
Did you check that virtio devices bound to uio_pci_generic still works
with legacy mode + PIO?
I had verified PIO, might under igb_uio driver.
Well, if you are unsure, please retest both cases
From: "huawei.xhw"
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose MMIO(memory IO) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all
other p
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address
like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on arch
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address from uio/uio# sysfs attribute
under uio_pci_generic:
for X86, get PIO address from /proc/ioport
On 2021/2/25 1:52, David Marchand wrote:
On Wed, Feb 24, 2021 at 4:29 PM 谢华伟(此时此刻） wrote:
Did you check that virtio devices bound to uio_pci_generic still works
with legacy mode + PIO?
I had verified PIO, might under igb_uio driver.
Well, if you are unsure, please retest both cases
On 2021/2/25 17:52, David Marchand wrote:
On Thu, Feb 25, 2021 at 5:00 AM 谢华伟(此时此刻） wrote:
Is the 'outb_p' to 'outb' conversion intentional? And if so why?
Same of the all 'outb_p', 'outw_p', 'outl_p'.
There is no need to delay for virtio d
On 2021/2/24 23:45, Ferruh Yigit wrote:
On 2/23/2021 2:20 PM, 谢华伟(此时此刻） wrote:
On 2021/2/23 1:25, Ferruh Yigit wrote:
On 2/22/2021 5:15 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We disti
On 2021/2/24 20:49, David Marchand wrote:
On Sun, Feb 21, 2021 at 4:58 PM 谢华伟(此时此刻） wrote:
On 2021/2/18 17:33, David Marchand wrote:
On Fri, Jan 29, 2021 at 4:19 AM 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three w
On 2021/2/23 1:25, Ferruh Yigit wrote:
On 2/22/2021 5:15 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their
address like how k
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address
like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on arch
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address from uio/uio# sysfs attribute
under uio_pci_generic:
for X86, get PIO address from /proc/ioport
From: "huawei.xhw"
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose MMIO(memory IO) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all
other p
On 2021/2/18 17:33, David Marchand wrote:
On Fri, Jan 29, 2021 at 4:19 AM 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address fr
On 2021/2/19 16:52, Ferruh Yigit wrote:
On 2/9/2021 2:51 PM, Ferruh Yigit wrote:
On 1/29/2021 3:18 AM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(mem
On 2021/2/17 17:06, David Marchand wrote:
On Fri, Jan 29, 2021 at 4:19 AM 谢华伟(此时此刻） wrote:
@@ -517,6 +525,60 @@
}
#endif
+static inline uint8_t ioread8(void *addr)
+{
+ uint8_t val;
+
+ val = (uint64_t)(uintptr_t)addr >= PIO_MAX ?
+ *(volatile uint8_t *)a
On 2021/2/3 17:37, Maxime Coquelin wrote:
Hi Huawei,
On 2/1/21 8:43 AM, 谢华伟(此时此刻） wrote:
On 2021/1/29 11:25, chris wrote:
Hi ferruh and maxime:
v6 changes:
send v6. Let us discuss if merge in this or early next release.
Ping.
The -rc2 was released on the 29th, so I think it is too late
On 2021/1/29 11:25, chris wrote:
Hi ferruh and maxime:
v6 changes:
send v6. Let us discuss if merge in this or early next release.
Ping.
Sorry that forget to reply to previous message id.
- change to DEBUG level for IO bar detection in pci_uio_ioport_map
- rework the code in
Hi ferruh and maxime:
v6 changes:
send v6. Let us discuss if merge in this or early next release.
Sorry that forget to reply to previous message id.
- change to DEBUG level for IO bar detection in pci_uio_ioport_map
- rework the code in iobar branch
- fixes commit message forma
From: "huawei.xhw"
With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address
like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on arch
From: "huawei.xhw"
Currently virtio PMD asssumes legacy device uses PIO bar.
There are three ways to get PIO(PortIO) address for virtio legacy device.
under igb_uio, get pio address from uio/uio# sysfs attribute
under uio_pci_generic:
for X86, get PIO address from /proc/ioport
From: "huawei.xhw"
virtio PMD assumes legacy device only supports PIO BAR resource. This is wrong.
As we need to create lots of devices, as PIO resource on x86 is very limited,
we expose MMIO(memory IO) BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all
other
On 2021/1/28 0:45, Ferruh Yigit wrote:
On 1/27/2021 2:43 PM, 谢华伟(此时此刻） wrote:
On 2021/1/27 18:32, Ferruh Yigit wrote:
I was waiting for clarification if this can be solved in virtio,
which seems clarified and decided to go with this patch, I am OK to
proceed with patch 1 & 2.
But f
On 2021/1/27 18:40, Ferruh Yigit wrote:
On 10/22/2020 4:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
If IO BAR, we get PIO address.
If MMIO BAR, we get mapped virtual address.
We distinguish PIO and MMIO by their address like how kernel does.
ioread/write8/16/32 is provided to acces
On 2021/1/27 18:32, Ferruh Yigit wrote:
I was waiting for clarification if this can be solved in virtio, which
seems clarified and decided to go with this patch, I am OK to proceed
with patch 1 & 2.
But first patch changes how PIO address get, it changes the Linux
interface used to get the
On 2021/1/26 20:35, Maxime Coquelin wrote:
On 1/26/21 1:30 PM, 谢华伟(此时此刻） wrote:
On 2021/1/22 15:25, chris wrote:
On 2021/1/21 23:38, Maxime Coquelin wrote:
Do you mean we apply or abandon patch 3? I am both OK. The first
priority to me is to enable MMIO bar support.
OK, so yes, I think we
On 2021/1/22 15:25, chris wrote:
On 2021/1/21 23:38, Maxime Coquelin wrote:
Do you mean we apply or abandon patch 3? I am both OK. The first
priority to me is to enable MMIO bar support.
OK, so yes, I think we should abandon patch 2 and patch 3.
For patch 1, it looks valid to me, but I'll le
On 2021/1/24 23:22, Xueming(Steven) Li wrote:
+ } else if (flags & IORESOURCE_MEM) {
+ iobar = 0;
+ base = (unsigned long)dev->mem_resource[bar].addr;
+ RTE_LOG(INFO, EAL, "%s(): MMIO BAR %08lx detected\n",
__func__, base);
Same here, INFO level
On 2021/1/21 23:38, Maxime Coquelin wrote:
Do you mean we apply or abandon patch 3? I am both OK. The first
priority to me is to enable MMIO bar support.
OK, so yes, I think we should abandon patch 2 and patch 3.
For patch 1, it looks valid to me, but I'll let Ferruh decide.
For your device,
"
I think that using inb/outb in the case of VFIO with IOMMU enabled won't
work without cap_sys_rawio, and using it in the case of VFIO with IOMMU
disabled just bypasses VFIO and so is not correct.
Get your concern.
PIO bar:
HW virtio on HW machine: any vendor implements hardware virti
On 2021/1/21 16:29, Maxime Coquelin wrote:
On 1/20/21 3:54 PM, 谢华伟(此时此刻） wrote:
On 2021/1/13 0:58, Maxime Coquelin wrote:
On 1/12/21 10:37 AM, Maxime Coquelin wrote:
bus/pci: ...
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
VFIO should use the same way to map/
On 2021/1/21 16:47, Maxime Coquelin wrote:
On 1/21/21 5:12 AM, 谢华伟(此时此刻） wrote:
On 2021/1/13 1:37, Maxime Coquelin wrote:
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to
create lots of
virtio devic
On 2021/1/12 16:23, Maxime Coquelin wrote:
Title should be something like:
"bus/pci: support MMIO in PCI ioport accessors
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
If IO BAR, we get PIO address.
If MMIO BAR, we get mapped virtual address.
We distinguish
On 2021/1/13 1:37, Maxime Coquelin wrote:
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO
On 2021/1/13 0:58, Maxime Coquelin wrote:
On 1/12/21 10:37 AM, Maxime Coquelin wrote:
bus/pci: ...
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
VFIO should use the same way to map/read/write PORT IO as UIO, for
virtio PMD.
Please provide more details in the commit
On 2021/1/12 16:07, Maxime Coquelin wrote:
Hi Huawei,
The title should be under the form:
"bus/pci: use PCI standard sysfs entry to get PIO address"
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Previously with igb_uio we get PIO address from igb_u
On 2021/1/13 1:37, Maxime Coquelin wrote:
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO
Hi Maxime and David:
Could we start to review this patch?
/Thanks, huawei
On 2020/11/10 20:42, David Marchand wrote:
On Tue, Nov 10, 2020 at 1:35 PM 谢华伟(此时此刻） wrote:
Previously there are different ways to get port address based on
different DPDK uio driver(IGB_UIO/UIO_PCI_GENERIC/VFIO
On 2020/11/10 20:42, David Marchand wrote:
On Tue, Nov 10, 2020 at 1:35 PM 谢华伟(此时此刻） wrote:
Previously there are different ways to get port address based on
different DPDK uio driver(IGB_UIO/UIO_PCI_GENERIC/VFIO), which is
actually not necessary.
This patch makes IO/MMIO port map/RW API
necessary.
This patch makes IO/MMIO port map/RW API more generic, which also
supports MMIO. It also fixes performance issue with vfio.
Could you spare some time to have time to review this?
Thanks
On 2020/10/22 23:51, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci onl
Hi Ferruh:
Comments to this v5 version?
On 2020/10/22 23:51, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO an
mbols, not
tested).
igb_uio with PIO bar is also tested.
Weird igb_uio doens't have Makefile.
On 2020/10/22 23:51, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to
create lots of
virtio devices and PIO resource on x86 i
io doens't have Makefile.
On 2020/10/22 23:51, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for
From: "huawei.xhw"
VFIO should use the same way to map/read/write PORT IO as UIO, for
virtio PMD.
Signed-off-by: huawei.xhw
---
drivers/bus/pci/linux/pci.c | 8
drivers/bus/pci/linux/pci_uio.c | 4 +++-
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/bus/pci
From: "huawei.xhw"
If IO BAR, we get PIO address.
If MMIO BAR, we get mapped virtual address.
We distinguish PIO and MMIO by their address like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
BTW, for virtio on arch other than x86, BAR flag indicates PIO but is mapped.
Signe
From: "huawei.xhw"
Previously with igb_uio we get PIO address from igb_uio sysfs entry, with
uio_pci_generic, we get PIO address from /proc/ioports.
Signed-off-by: huawei.xhw
---
drivers/bus/pci/linux/pci.c | 77 -
drivers/bus/pci/linux/pci_uio.c | 6
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We handles
different type of BAR in the similar way.
On 2020/10/22 17:44, Ferruh Yigit wrote:
On 10/22/2020 10:15 AM, 谢华伟(此时此刻） wrote:
On 2020/10/22 1:24, Ferruh Yigit wrote:
On 10/21/2020 1:32 PM, 谢华伟(此时此刻） wrote:
On 2020/10/21 19:49, Ferruh Yigit wrote:
On 10/13/2020 9:41 AM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virti
On 2020/10/22 1:24, Ferruh Yigit wrote:
On 10/21/2020 1:32 PM, 谢华伟(此时此刻） wrote:
On 2020/10/21 19:49, Ferruh Yigit wrote:
On 10/13/2020 9:41 AM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to
create lots of
virtio devic
On 2020/10/21 19:49, Ferruh Yigit wrote:
On 10/13/2020 9:41 AM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to
create lots of
virtio devices and PIO resource on x86 is very limited, we expose
MMIO BAR.
Kernel supports bot
the performance issue with VFIO port write(virtio
only).
Besides, next thing we could do is to move some of those PCI codes to
virtio PMD as they are for virtio
PMD only.
/huawei
On 2020/10/13 16:41, 谢华伟(此时此刻） wrote:
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BA
switch (p->dev->kdrv) {
#ifdef VFIO_PRESENT
case RTE_PCI_KDRV_VFIO:
- pci_vfio_ioport_read(p, data, len, offset);
+ pci_uio_ioport_read(p, data, len, offset);
break;
#endif
case RTE_PCI_KDRV_IGB_UIO:
- pci_uio
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We handles
different type of BAR in the similar way.
From: "huawei.xhw"
v2 changes:
- add more explanation in the commit message
v3 changes:
- fix patch format issues
v4 changes:
- fixes for RTE_KDRV_UIO_GENERIC -> RTE_PCI_KDRV_UIO_GENERIC
huawei.xhw (1):
pci: support both PIO and MMIO BAR for legacy virtio on x86
On 2020/10/5 17:11, Maxime Coquelin wrote:
On 10/5/20 10:57 AM, Thomas Monjalon wrote:
24/09/2020 07:41, Stephen Hemminger:
On Fri, 11 Sep 2020 17:54:48 +0200
Thomas Monjalon wrote:
As decided in the Technical Board in November 2019,
the kernel module igb_uio is moved to the dpdk-kmods re
From: "huawei.xhw"
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We handles
different type of BAR in the similar way.
On 2020/10/1 18:22, Burakov, Anatoly wrote:
On 30-Sep-20 3:59 PM, 谢华伟(此时此刻） wrote:
From c13f981e287254cd0877cc7b98ee2dd7b80c3b69 Mon Sep 17 00:00:00 2001
From: "huawei.xhw"
Date: Wed, 30 Sep 2020 22:37:03 +0800
Subject: [PATCH v2] pci: support both PIO and MMIO BAR for legacy
From c13f981e287254cd0877cc7b98ee2dd7b80c3b69 Mon Sep 17 00:00:00 2001
From: "huawei.xhw"
Date: Wed, 30 Sep 2020 22:37:03 +0800
Subject: [PATCH v2] pci: support both PIO and MMIO BAR for legacy virtio on
x86
Legacy virtio-pci only supports PIO BAR resource. As we need to create
lots of
virti
On 2020/9/25 2:02, Ferruh Yigit wrote:
On 9/15/2020 4:21 PM, 谢华伟(此时此刻） wrote:
Hi Ferruh:
Legacy virtio only supports PIO BAR resource. As we need to create
lots of virtio devices and PIO resource on x86 is very limited, we
expose MMIO BAR.
Kernel support both PIO and MMIO BAR for legacy
:18, 谢华伟(此时此刻） wrote:
From d0138f24037d8df14cac04c2c24831e4b5d27b8c Mon Sep 17 00:00:00 2001
From: "huawei.xhw"
Date: Mon, 14 Sep 2020 23:44:56 +0800
Subject: [PATCH] pci: support both PIO and MMIO BAR for legacy virtio on x86
In previous implementation, with igb_uio we get PIO ad
From d0138f24037d8df14cac04c2c24831e4b5d27b8c Mon Sep 17 00:00:00 2001
From: "huawei.xhw"
Date: Mon, 14 Sep 2020 23:44:56 +0800
Subject: [PATCH] pci: support both PIO and MMIO BAR for legacy virtio on x86
In previous implementation, with igb_uio we get PIO address from igb_uio
sysfs entry; with
In previous implementation, with igb_uio we get PIO address from igb_uio
sysfs entry; with uio_pci_generic, we get PIO address from
/proc/ioports.
For PIO/MMIO RW, there is different path for different drivers and arch.
For VFIO, PIO port RW is through syscall, which has big performance issue.
On
In previous implementation, with igb_uio we get PIO address from igb_uio
sysfs entry; with uio_pci_generic, we get PIO address from
/proc/ioports.
For PIO/MMIO RW, there is different path for different drivers and arch.
For VFIO, PIO port RW is through syscall, which has big performance issue.
On
Hi Ferruy:
Resent the patch.
This patch is to support both MMIO and PIO bar for legacy virtio. We use MMIO
bar for legacy virtio on x86 because we create lots of virtio devices as PIO
resource is very limited.
virtio is the only PMD which might use PIO. kernel virtio-pci driver supports
both P
Signed-off-by: huawei.xhw
---
drivers/bus/pci/linux/pci.c | 71 --
drivers/bus/pci/linux/pci_uio.c | 154 +++-
2 files changed, 106 insertions(+), 119 deletions(-)
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
Signed-off-by: huawei.xhw
---
drivers/bus/pci/linux/pci.c | 71 --
drivers/bus/pci/linux/pci_uio.c | 154 +++-
2 files changed, 106 insertions(+), 119 deletions(-)
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.
Hi Ferruh:
This patch is to support both MMIO and PIO bar for legacy virtio. We use MM bar
for legacy virtio on x86 because we create lots of virtio devices as PIO
resource is very limited.
virtio on x86 is the only PMD which might use PIO. kernel virtio-pci driver
supports both PIO bar and MMI
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