[AMD Official Use Only - General]
Hi Sunil,
I think you don't have to address the CI issues at the moment, however you can
run the minimum check such as PatchCheck and Uncrustify locally before sending
patches.
This is a big series of patch set, I will help to go through all patches. You
can ad
>
> Can OsIndicationsSupported UEFI variable provide the similar functionality?
>
Similar, but not the same. If we use a UEFI variable, its value will
persist across boots. This can be fine if you only boot one OS, but if
you have two where one supports unaccepted memory and the other
doesn't then
On Fri, Oct 14, 2022 at 06:50:35PM +0200, Ard Biesheuvel wrote:
> Can you please stop spamming me and the list with two versions of this
> series per day?
>
Very sorry Ard. I thought it was important to fix CI found issues and
folder name before others start reviewing. But I understand the pain.
W
Can you please stop spamming me and the list with two versions of this
series per day?
On Fri, 14 Oct 2022 at 18:48, Sunil V L wrote:
>
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
>
> Add support for RISC-V qemu virt machine. Most of the changes are migrated
> from
> edk2-platf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)
diff
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add infrastructure files to build edk2 for RISC-V qemu virt machine.
- EDK2 will boot as S-mode payload of opensbi.
- It supports building
either code and variables in unified flash or in two separate drives
via build time option UNIFIE
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RiscVVirt is created to support EDK2 for RISC-V qemu
virt machine platform. Add maintainer entries.
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Signed-off-by: Sunil V L
---
Maintainers.txt | 4
1 file changed, 4 inserti
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from ArmVirtPkg since it is required for
other architectures also. It uses OVMF specific PCD variables.
Also add the instance for single flash drive which has
both code and variables. This is copied from SbsaQemu.
Cc:
Currently, when dealing with small updates that can be written out
directly (i.e., if they only involve clearing bits and not setting bits,
as the latter requires a block level erase), we iterate over the data
one word at a time, read the old value, compare it, write the new value,
and repeat, unle
Switching to array mode (i.e., ROM memory mode rather than NOR flash
programming mode) is rather costly when running under KVM emulation, as it
involves setting up the read-only memslot in the hypervisor's stage 2
page tables. So let's avoid jumping between modes unnecessarily, and
only switch back
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V needs NorFlashDxe driver for qemu virt machine. The
ArmPlatformPkg has this driver but migrating it to generic
package like MdeModulePkg introduces circular dependencies.
So, add NorFlashDxe driver in OvmfPkg which is mostly the
copy
The NvVarStoreFormattedLib library is moved to MdeModulePkg.
So, updates its users with the new location.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
ArmVirtPkg/ArmVirtKvmTool.dsc| 2 +-
ArmVirtPkg/ArmVirtQemu.dsc | 2 +-
Arm
This library is required by NorFlashDxe. Since it will be used by
both virtual and real platforms, migrate this library to
MdeModulePkg.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Abner Chang
Cc: Daniel Schaefer
Cc: Jian J Wang
Cc: Liming Gao
Cc: Andrew Fish
Cc: Michael D Kinney
Signed-off-b
Migrate NorFlashPlatformLib.h to MdePkg and add a Null
instance of the NorFlashPlatformLib library in MdePkg.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Andrew Fish
Signed-off-by: Sunil V L
---
ArmPlatformPkg/ArmPlatformPkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformBootManagerLib has been moved to OvmfPkg so that other
CPU architectures can reuse. So, update existing paths with the
new location.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-off-by: Sunil V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformBootManagerLib in ArmVirtPkg is required for RISC-V
also. So, move it to OvmfPkg.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Jordan Justen
Signed-off-by: Sunil V L
---
OvmfPkg/
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add the support for this protocol which is defined in the spec:
https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf
Cc: Eric Dong
C
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
PlatformHasAcpiDtDxe is required by other architectures also.
Hence, it is moved to OvmfPkg. So, update the consumers of this
module with the new location.
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-o
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This module is required by other architectures like RISC-V.
Hence, move this to OvmfPkg.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
ArmVirtPkg/ArmVirtPkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/UefiCpuPkg.dsc| 3 +
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/CpuDxe/CpuDxe.inf | 8 +
UefiCpuPkg/CpuDxe/Ri
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, CpuDxe supports only X86 architecture. To add
support for other architectures like RISC-V, this need to
be refactored.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/CpuDxe/CpuDxe.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf|
7 +-
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptio
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the CpuExceptionHandlerLib library supports only X86.
Refactor the library to allow adding other CPU architectures.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/Library/CpuExceptionHandler
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, CpuTimerLib library supports only X86 architecture.
Refactor to allow other CPU architectures.
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: Sunil V L
---
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Daniel Schaefer
Signed-off-by: Sunil V L
---
OvmfPkg/PlatformPe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is mostly copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Library/ResetSystemLib
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Rebecca Cran
Cc: Peter Grehan
Cc: Daniel Schaefer
Signed-off-by: S
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, PlatformPei supports only X86 architecture. So,
refactor it to allow other CPU architectures.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
OvmfPkg/PlatformPei/PlatformPe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add the SEC module for RISC-V. EDK2 is launched as the payload
for machine mode firmware in RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Min X
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the Sec module supports only X86 architecture.
Refactor the module to allow other CPU architectures.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomle
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, the ResetSystemLib library supports only X86 architecture.
Refactor it to allow adding other CPU architectures like RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Rebecca Cran
Cc: Peter Gre
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is copied from
edk2-platforms/Platform/RISC-V/PlatformPkg/Universal/FdtPeim
but added as part of library instead of a separate module.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Daniel Schaefer
Signe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Currently, PlatformInitLib supports only X86 architecture. So,
refactor to allow adding other architectures like RISC-V.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Sunil V L
---
OvmfPkg/Librar
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This library is required to make SBI ecalls from the S-mode EDK2.
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Daniel Schaefer
Signed-off-by:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition and the header file required.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
---
MdePkg/MdePkg.dec
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.
Cc: Daniel Schaefer
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Sunil V L
Acked-by: Abner Chang
---
MdePk
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Add support for RISC-V qemu virt machine. Most of the changes are migrated from
edk2-platforms repo and followed the latest guidelines for EDK2 code
structuring.
The changes at a high level are,
1) MdePkg:
- Add RISC-V register
[AMD Official Use Only - General]
Acked-by: Abner Chang
However, this patch has the dependency with patch 7/34.
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Sunil V L
> via groups.io
> Sent: Thursday, October 13, 2022 5:58 PM
> To: devel@edk2.groups.io
> Cc: Ard Biesh
[AMD Official Use Only - General]
No problem with this change. Just we will use Ia32X64 for the arch folder (no
"_" in between) as the discussions we had in another thread.
We will have to wait until the File Naming and Directory naming sections are
firmed and published in edk2 coding standard s
Hi Oliver,
Thank you for the updated patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 14/10/2022 01:34 pm, Oliver Steffen wrote:
ArmVirtXen.dsc initializes
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER".
Move that functio
ArmVirtXen.dsc initializes
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER".
Move that functionality to ArmVirt.dsc.inc to make it available
to all ArmVirt packages, and make it conditional: only set the
PCD string if FIRMWARE_VER is actual
Initialize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
with with the value of the variable "FIRMWARE_VER", if
is is defined.
Applies to all flavors of OvmfPkg.
This behavior is already implemented in ArmVirtXen.dsc.
It allows specifying the firmware version string on the
build command
ArmVirtXen.dsc allows setting the firmware version
string in gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
via FIRMWARE_VER variable conveniently on the build command line.
These two patches add this behavior to all .dsc files in ArmVirtPkg
and OvmfPkg.
PR: https://github.com/tianocore/
Reviewed-by: Ray Ni
> -Original Message-
> From: Tan, Dun
> Sent: Friday, October 14, 2022 5:19 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R
> Subject: [Patch V3 2/4] UefiCpuPkg: Add Unit tests for
> PeiCpuExceptionHandlerLib
>
> The previous change add
Reviewed-by: Ray Ni
> -Original Message-
> From: Tan, Dun
> Sent: Friday, October 14, 2022 5:19 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R
> Subject: [Patch V3 1/4] UefiCpuPkg: Add Unit tests for
> DxeCpuExceptionHandlerLib
>
> Add target based unit t
Ok, I'll try to add this format code for R8/R9/etc.
"ExceptionList": [
"", ""
],
Thanks,
Dun
-Original Message-
From: Ni, Ray
Sent: Friday, October 14, 2022 5:40 PM
To: Tan, Dun ; devel@edk2.groups.io
Cc: Dong, Eric ; Kumar, Rahul R
Subject: RE: [Patch V3 4/4] UefiCpuP
Can we use BaseTools/Source/Python/Ecc/exception.xml to mark exceptions of
R8/R9/etc.
instead of ignoring the entire H file?
Thanks,
ray
> -Original Message-
> From: Tan, Dun
> Sent: Friday, October 14, 2022 5:20 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul
Add CpuExceptionHandlerTest.h in EccCheck IgnoreFiles of
UefiCpuPkg/UefiCpuPkg.ci.yaml to pass ECC check. The
GENERAL_REGISTER.R8 in this file triggers EccCheck failure
since no lower case characters in R8/R9/R10.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
---
UefiCpuPkg/
Add Pei/DxeCpuExceptionHandlerLibUnitTest module in UefiCpuPkg.dsc
Signed-off-by: Dun Tan
Cc: Eric Dong
Reviewed-by: Ray Ni
Cc: Rahul Kumar
---
UefiCpuPkg/UefiCpuPkg.dsc | 7 +++
1 file changed, 7 insertions(+)
diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index f694
The previous change adds unit test for DxeCpuExeptionHandlerLib
in 64bit mode. This change create a PEIM to add unit test for
PeiCpuExceptionHandlerLib based on previous change.It can run
in both 32bit and 64bit modes.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
---
UefiCp
Add target based unit tests for the DxeCpuExceptionHandlerLib.
A DXE driver is created to test DxeCpuExceptionHandlerLib.
Four test cases are created in this Unit Test module:
a.Test if exception handler can be registered/unregistered
for no error code exception.In the test case, only no error
cod
In V3 1/4 patch:
Remove uunneeded CPU_INFO_IN_HOB and IA32_GDT structure.
Use R8/R9 as the register name instead of R8Register.
Return a Boolean flag for FindPFAddressInPageTable.
In V3 2/4 patch:
Use same global variable name for IA32 mExpectedContextInHandler/AfterException.
In the new 4/4 patc
On Fri, 14 Oct 2022 at 04:14, SteveX Li wrote:
>
> It would cause compiler error.
>
Which compiler and which error?
> Signed-off-by: SteveX Li
> Cc: Leif Lindholm
> Cc: Ard Biesheuvel
> Cc: Abner Chang
> Cc: Daniel Schaefer
> ---
> EmbeddedPkg/GdbStub/GdbStubInternal.h| 32
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