Reviewed-by: Ray Ni
Thanks,
Ray
> -Original Message-
> From: Chao Li
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Ni, Ray ; Kumar, Rahul R ;
> Gerd Hoffmann ; Leif Lindholm
> ; Ard Biesheuvel ;
> Sami Mujawar
> Subject: [PATCH v6 18/36] UefiCpuPkg: Add a new
Thanks Saloni. PR for getting this merged is available at
https://github.com/tianocore/edk2/pull/5150
Thanks
Ashish
From: Kasbekar, Saloni
Sent: Saturday, January 6, 2024 1:31 AM
To: Ashish Singhal ; devel@edk2.groups.io
; Clark-williams, Zachary
; Jeff
//
// Check whether we need to create Tls child and open the TLS protocol.
//
+if (HttpInstance->UseHttps && !HttpInstance->TlsAlreadyCreated) {
+ // Create TLS child for this HTTP instance.
+ Status = TlsCreateChild (HttpInstance);
+ if (EFI_ERROR (Status)) {
Pushed as 9cf1d03
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Nate
> DeSimone
> Sent: Friday, September 29, 2023 3:12 PM
> To: devel@edk2.groups.io
> Cc: Andrew Fish ; Ni, Ray ; Kinney,
> Michael D ; Chiu, Chasel
>
> Subject: [edk2-devel] [PATCH v2] EmulatorPkg: Add
Reviewed-by: Saloni Kasbekar
-Original Message-
From: abner.ch...@amd.com
Sent: Friday, January 5, 2024 12:37 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni ; Clark-williams, Zachary
; Michael Brown ; Nickle Wang
; Igor Kulchytskyy
Subject: [PATCH 2/5] NetwokrPkg/HttpDxe: Consider
Yes, SetData does reset the previous configuration.
Reviewed-by: Saloni Kasbekar
Thanks,
Saloni
From: Ashish Singhal
Sent: Friday, January 5, 2024 2:34 AM
To: Kasbekar, Saloni ; devel@edk2.groups.io;
Clark-williams, Zachary ; Jeff Brasen
Subject: Re: [PATCH] NetworkPkg/Ip4Dxe: Fix Reset To
Pushed as b46ecad
> -Original Message-
> From: Huang, Li-Xia
> Sent: Monday, December 25, 2023 11:56 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Desimone, Nathaniel L
>
> Subject: [PATCH v1 1/1] BoardModulePkg\Library\BiosIdLib: Support
> Standalone MM
>
> Add Standalone Mm
Hi Li,
It looks like the standalone MM version of this library is missing the search
for the BiosId file. I suspect the issue you ran into is that standalone MM
only has support for 1 FV, and it is highly likely that the BiosId file is not
in the standalone MM FV. This is understandable;
On Wed, Jan 3, 2024 at 1:59 PM Sunil V L wrote:
>
> This series adds the support for RISV-V Sstc extension in EDK2 timer
nit: RISC-V
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
>
> Currently, PCD variable is used to detect
On 1/5/2024 9:22 AM, levi.yun wrote:
Hi Ard :)
So now we will always initialize the serial port in the entrypoint
only because DebugLib might use it later with doing the
initialization.
That doesn't sound quite correct to me.
Could you explain why we cannot rely on DebugLib to call the
Hi Ard :)
So now we will always initialize the serial port in the entrypoint
only because DebugLib might use it later with doing the
initialization.
That doesn't sound quite correct to me.
Could you explain why we cannot rely on DebugLib to call the
initializer / constructor at the right
On 05/01/2024 08:41, Chang, Abner wrote:
We are not aware there is a TlsConnectSession() for TLS handshake using the
default TLS configuration data and it returns a failure as expected because the
default TLS configuration is TLS_VERIFY_HOST without certificate installed on
system.
This
On 05/01/2024 08:37, abner.ch...@amd.com wrote:
+ ///
+ /// The Status of Event to configure TLS configuration data.
+ /// EventStatus:
+ /// EFI_SUCCESSThe TLS is configured successfully with the
default value.
+ /// EFI_INVALID_PARAMETER One or more input parameters to
On 05/01/2024 08:37, abner.ch...@amd.com wrote:
We still return EFI_SUCCESS to the caller when TlsConfigCertificate
returns error, for the use case the platform doesn't require
certificate for the specific HTTP session. This ensures
HttpInitSession function still initiated and returns
On 05/01/2024 08:37, abner.ch...@amd.com wrote:
From: Abner Chang
- Use HTTP instance as the parameter for TlsCreateChild function.
- Install TLS protocol on the HTTP instance thats create TLS child.
Logic looks good to me, just some minor cosmetic comments.
Commit title has "NetwokrPkg"
RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Prabin CA
---
Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set
the desired performance.
Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Signed-off-by: Prabin CA
---
The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file
Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.
Signed-off-by: Prabin CA
---
From: Shriram K
RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation
In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.
From: Vivek Gautam
On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.
Signed-off-by: Vivek Gautam
Signed-off-by: Prabin CA
This patch series introduce support for RD-Fremont reference design
platform. This platform includes 32 CPUs, but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. Each of the CPUs
include 64KB L1
On Fri, 5 Jan 2024 at 12:49, levi.yun wrote:
>
> Serial port used by the DEBUG macro is initialised in StandaloneMmMain
> by the DebugLib constructor.
>
> When we use a serial port initialised by TF-A it is not a problem.
> However, if we use a serial port that is not initialised by TF-A,
> the
On 1/5/2024 1:26 AM, Ard Biesheuvel via groups.io wrote:
On Fri, 5 Jan 2024 at 06:15, Rebecca Cran
wrote:
Fixes and improvements to GenericWatchdogDxe.
What is the difference between v2 and v3?
Sorry, I should have said that. I forgot to build v2 and it had a bug in
the exit boot
Looks reasonable to me.
Reviewed-by: Andrei Warkentin
> -Original Message-
> From: Yang Wang
> Sent: Wednesday, December 27, 2023 8:57 PM
> To: Warkentin, Andrei ; devel@edk2.groups.io
> Cc: Yang Wang ; Ran Wang ;
> Bamvor Jian ZHANG ; Gao, Liming
> ; Kinney, Michael D
> ; Sunil V L ;
From: Pranav Madhu
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration and reuse rest of the RD-N2 SMBIOS configuration for the
From: Pranav Madhu
Add RD-V2 platform identification values including the part number
and configuration number. This information will be used in populating
the SMBIOS tables.
Signed-off-by: Pranav Madhu
Signed-off-by: Prabin CA
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7
The Neoverse RD-N2-Cfg3 platform is a variant of RD-N2 platform with a
different mesh size and GIC ITS count. As part of the initial platform
support, add the corresponding platform and flash description files.
Use PcdPlatformVariant for the RD-N2-Cfg3 platform to specify the
platform variant.
A new PCD named PcdPlatformVariant is introduced to specify the variant
number of a platform. This PCD can be used to select platform variant
specific configurations. The default value of this PCD is 0 which
selects the base variant.
Signed-off-by: Prabin CA
---
From: Vijayenthiran Subramaniam
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3479
A recent change in MdeModulePkg [1] introduced VariableFlashInfoLib as a
dependency to support dynamic variable flash information. Add an
instance for the library class VariableFlashInfoLib in
Add the no-stack-protector compiler flag to allow StandaloneMM builds
on both AArch64 and x86 host. Without this flag, the link stage fails
with the following errors on multiple files when built with gcc
(Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0:
undefined reference to `__stack_chk_guard'
undefined
From: Omkar Anand Kulkarni
The software executing at a higher privileged level on the reference
design platforms have been updated to allow software executing at EL1
and EL0 to access the Advanced SIMD and floating-point registers (FPEN
field of CPACR_EL1 system register is programmed to allow
Changes since V1:
- Addressed comments from Sami
This patch series introduces support for two reference design platforms-
RD-N2-Cfg3 and RD-V2. The RD-N2-Cfg3 FVP platform is a variant of RD-N2
platform with a different mesh size and GIC ITS count. It is based on
the Neoverse N2 CPUs and includes
On 1/5/24 13:56, Ni, Ray wrote:
> Laszlo,
> Good suggestion.
>
> Your solution will not work if in future some extra fields might require to
> be set to non-zero.
> But future is not coming yet. I agree with your approach.
Well, if we need to set some fields to nonzero, manual assignments will
On 1/5/24 13:55, Ni, Ray wrote:
>>> - if (ProcessorNumber != 0) {
>>> + //
>>> + // Lower 24 bits contains the actual processor number.
>>> + //
>>> + if ((ProcessorNumber & (CPU_V2_EXTENDED_TOPOLOGY - 1)) != 0) {
> I suggest we explicitly use BIT24 instead of CPU_V2_EXTENDED_TOPOLOGY.
>
On 1/5/24 13:52, Ni, Ray wrote:
> Reviewed-by: Ray Ni
Thanks, please feel free to merge this!
Laszlo
>
>
> Thanks,
> Ray
>> -Original Message-
>> From: Jin, Zhi
>> Sent: Friday, January 5, 2024 10:54 AM
>> To: devel@edk2.groups.io
>> Cc: Jin, Zhi ; Ni, Ray ; Laszlo Ersek
>> ; Kumar,
On 1/4/24 16:46, Sunil V L wrote:
> On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote:
>> On 1/3/24 14:58, Sunil V L wrote:
>>> Sstc extension allows to program the timer and receive the interrupt
>>> without using an SBI call. This reduces the latency to generate the timer
>>>
On 1/4/24 16:01, Sunil V L wrote:
> Hi Laszlo,
>
> Thank you very much for the review!.
>
> On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote:
>> On 1/3/24 14:58, Sunil V L wrote:
>>> Sstc extension allows to program the timer and receive the interrupt
>>> without using an SBI call.
On 1/4/24 16:06, Gerd Hoffmann wrote:
> Hi,
>
- if the StartId is 0x55aa, then we need to look further, beause we
can't decide yet. For example, if State is VAR_HEADER_VALID_ONLY (0x7f),
then it might be fine for the variable header (at the very end of the
varstore) *not* to
Laszlo,
Good suggestion.
Your solution will not work if in future some extra fields might require to be
set to non-zero.
But future is not coming yet. I agree with your approach.
Thanks,
Ray
> -Original Message-
> From: Tan, Dun
> Sent: Friday, January 5, 2024 5:25 PM
> To: Laszlo
> > - if (ProcessorNumber != 0) {
> > + //
> > + // Lower 24 bits contains the actual processor number.
> > + //
> > + if ((ProcessorNumber & (CPU_V2_EXTENDED_TOPOLOGY - 1)) != 0) {
I suggest we explicitly use BIT24 instead of CPU_V2_EXTENDED_TOPOLOGY.
Using BIT24 clearly tells that processor
Acked-by: Ray Ni
Thanks,
Ray
> -Original Message-
> From: Chao Li
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Baoqi Zhang ; Dongyan Qian
> ; Xianglai Li ; Bibo Mao
>
> Subject: [PATCH v6 13/36]
Reviewed-by: Ray Ni
Thanks,
Ray
> -Original Message-
> From: Jin, Zhi
> Sent: Friday, January 5, 2024 10:54 AM
> To: devel@edk2.groups.io
> Cc: Jin, Zhi ; Ni, Ray ; Laszlo Ersek
> ; Kumar, Rahul R ; Gerd
> Hoffmann ; Wu, Jiaxin
> Subject: [PATCH v2 1/1] UefiCpuPkg/PiSmmCpuDxeSmm:
Reviewed-by: Ray Ni
Thanks,
Ray
> -Original Message-
> From: Chao Li
> Sent: Friday, January 5, 2024 5:44 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R ; Gerd Hoffmann ;
> Leif Lindholm ; Ard Biesheuvel
> ; Sami Mujawar ;
> Sunil V L ; Warkentin, Andrei
>
+ ardb+tianoc...@kernel.org
From: levi.yun
Sent: 05 January 2024 11:49
To: devel@edk2.groups.io
Cc: Yeo Reum Yun; ard.biesheu...@linaro.org; Sami Mujawar; ray...@intel.com;
Pierre Gondois; nd
Subject: [PATCH v1 1/1] StandaloneMmPkg: Initialise serial
Serial port used by the DEBUG macro is initialised in StandaloneMmMain
by the DebugLib constructor.
When we use a serial port initialised by TF-A it is not a problem.
However, if we use a serial port that is not initialised by TF-A,
the debug log prints hangs.
Therefore, initialise the serial
Hi Abner,
Thank you for the clarification.
Regards,
Mike.
On Fri, Jan 5, 2024 at 12:03 PM Chang, Abner wrote:
>
> [AMD Official Use Only - General]
>
> Hi Mike,
> This PCD is introduced for the platform that connects to the Redfish service
> which doesn't support ETag.
> We disable the client
Hi Rebecca,
Thank you for this patch.
Please see my feedback inline marked [SAMI].
Regards,
Sami Mujawar
On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:
Update GenericWatchdogDxe to disable watchdog interaction after exiting
boot services. Also, move the
Hi Rebecca,
I have a minor suggestion marked inline as [SAMI], otherwise this patch looks
good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:
The calculation of the timer period was broken.
Hi Rebecca,
Thank you for the updated patch.
Please find my feedback inline marked [SAMI].
Regards,
Sami Mujawar
On 05/01/2024, 05:15, "Rebecca Cran" mailto:rebe...@os.amperecomputing.com>> wrote:
The generic watchdog offset register is 48 bits wide, and can be set by
performing two 32-bit
I do not recommend doing that. Setting policy via SetData does enough to wipe
out any previous manual configuration and that is the goal for reset to default.
From: Kasbekar, Saloni
Sent: Friday, January 5, 2024 2:30 AM
To: Ashish Singhal ; devel@edk2.groups.io
Add self introduction file for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
---
OvmfPkg/LoongArchVirt/Readme.md | 67
Add infrastructure files to build edk2 for LoongArch QEMU virtual
machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Platfrom PEI module for LoongArch platfrom initialization.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo
Add SEC code for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
Co-authored-by: Bibo Mao
---
This library provides interface related to restart and shudown the
LoongArch64 virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc:
Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Xianglai Li
This library is provides real time clock for LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.
This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase,
Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.
LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.
BZ:
This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan
Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Bibo Mao
Cc: Dongyan Qian
Signed-off-by: Chao Li
Moved the PlatformBootManagerLib to OvmfPkg and renamed to
PlatformBootManagerLibLight for easy use by other ARCH.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc:
Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into
OvmfPkg so other ARCh can easily use it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Signed-off-by: Chao Li
---
Move the FdtSerialPortAddressLib to Ovmfpkg so that other ARCH can
easily use it.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Cc: Laszlo Ersek
CpuIo2Dxe is already used by RiscVVirt, so remove it.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 --
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "RiscVVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Chao Li
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +-
CpuMmio2Dxe is supports MMIO, enable it.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
---
ArmVirtPkg/ArmVirtCloudHv.dsc| 2 +-
CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not
implement ports for CPU IO require MMIO to access PCI IO, and they
pretty much put the IO devices under the LPC bus, which is usually under
the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs.
CpuMmio2Dxe depends on
Moved PcdDeviceTreeInitialBaseAddress and PcdDeviceTreeAllocationPadding
to OvmfPkg for easier use by other architectures.
Build-tested only (with "ArmVirtQemu.dsc").
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd
Added LoongArch64 architecture CPU IO width.
https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Abner Chang
Cc: Daniel Schaefer
Signed-off-by: Chao Li
Reviewed-by: Leif Lindholm
---
EmbeddedPkg/EmbeddedPkg.dec | 3 +++
1 file changed, 3
Added a new DXE driver named CpuDxeLoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan Qian
Acked-by: Ray Ni
---
Added a new library named LoongArch64MpInitLib.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Ray Ni
---
.../LoongArch64MpInitLib/DxeMpInitLib.inf | 45 +
Add a new library LoongArch64CpuMmuLib. It provides two-stage MMU library
instances, PEI and DXE.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Co-authored-by: Baoqi Zhang
Co-authored-by: Dongyan
Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc:
Added a new library named LoongArch64CpuExceptionHandlerLib, and
modified the way LoongArch exceptions are expressed.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Add the LoongArch64 CPU Timer library, using CPUCFG 0x4 and 0x5 for
Stable Counter frequency.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
Signed-off-by: Chao Li
Acked-by: Ray Ni
---
.../BaseLoongArch64CpuTimerLib.inf
Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides
setting and getting the PEI service table pointer through the CSR KS0
register.
The idea of this library is derived from
ArmPkg/Library/PeiServicesTablePointerLib/
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc:
Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8,
IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers
of LoongArch architecture.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by:
Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them
to operate the CSR register of LoongArch architecture.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Co-authored-by: Bibo Mao
Add LoongArch gets stable counter ASM function.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
---
MdePkg/Include/Library/BaseLib.h | 12 ++
Add LoongArch AsmCpucfg function and Cpucfg definitions.
Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of
EccCheck.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D
Adding LoongArch local interrupt function set, which is used to control
the opening or closing of the local interrupt when the global interrupt
is enabled.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions
for LoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
---
MdePkg/Include/Library/BaseLib.h
Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and
DisableFloatingPointUnits functions for LoongArch64.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
---
Adding Csr.h for LoongArch64, it is use for accessing the CSR registers.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: Chao Li
Acked-by: Michael D Kinney
---
MdePkg/Include/Register/LoongArch64/Csr.h | 263
This patch set will enable LoongArch virtual machine in edk2, the new
LoongArch virtual machine is located in OvmfPkg/LoongArchVirt/, it is a
generic platform that dose not require any actual hardware.
Patch1-Patch14: Submit the common library and driver for LoongArch
virtual machine and real
Hi Laszlo,
Thanks for your comments. I agree with your solution. It seems simpler and
clearer. Will change the code and keep the additional function comments in next
version patch set.
Thanks,
Dun
-Original Message-
From: Laszlo Ersek
Sent: Thursday, January 4, 2024 10:53 PM
To:
[AMD Official Use Only - General]
Hi Mike,
This PCD is introduced for the platform that connects to the Redfish service
which doesn't support ETag.
We disable the client code that handles ETag with setting this PCD to FALSE. So
client will just consume any Redfish property from service even
Hi Prabin,
There are 2 patches each in this series numbered 4/7, 5/7, 6/7 , 7/7. This is
very confusing.
[edk2-platforms][PATCH v1 7/7] Platform/Sgi: Extend SMBIOS support for RD-V2
platform
[edk2-platforms][PATCH v1 7/7] Platform/Sgi: Add support for RD-N2-Cfg3 platform
[edk2-platforms][PATCH
[AMD Official Use Only - General]
Hi Michael,
We are not aware there is a TlsConnectSession() for TLS handshake using the
default TLS configuration data and it returns a failure as expected because the
default TLS configuration is TLS_VERIFY_HOST without certificate installed on
system.
This
From: Abner Chang
Update Supported function to check it the given
controller handle is already started.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
RedfishPkg/RedfishRestExDxe/RedfishRestExDriver.c | 15 +++
1 file changed, 15 insertions(+)
diff --git
From: Abner Chang
Implement EDKII_HTTP_CALLBACK_PROTOCOL that listens to
HttpEventTlsConfigured event for reconfiguring TLS configuration
data.
Signed-off-by: Abner Chang
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
.../RedfishRestExDxe/RedfishRestExDxe.inf | 2 +
From: Abner Chang
Add HttpEventTlsConfigured HTTP callback event and notify
callback functions when TlsConfigureSession () returns.
Signed-off-by: Abner Chang
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Cc: Michael Brown
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
From: Abner Chang
We still return EFI_SUCCESS to the caller when TlsConfigCertificate
returns error, for the use case the platform doesn't require
certificate for the specific HTTP session. This ensures
HttpInitSession function still initiated and returns EFI_SUCCESS to
the caller. The failure
From: Abner Chang
- Use HTTP instance as the parameter for TlsCreateChild function.
- Install TLS protocol on the HTTP instance thats create TLS child.
Signed-off-by: Abner Chang
Cc: Saloni Kasbekar
Cc: Zachary Clark-williams
Cc: Michael Brown
Cc: Nickle Wang
Cc: Igor Kulchytskyy
---
From: Abner Chang
For the HTTPS connetion that doesn't require TLS peer verification,
We introduce a new HTTP event HttpEventTlsConfigured to notify HTTP callback
functions after TlsConfigureSession(). With this event, the upper layer
HTTP application can listen to HttpEventTlsConfigured HTTP
1 - 100 of 103 matches
Mail list logo
