On 1/4/24 16:46, Sunil V L wrote: > On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote: >> On 1/3/24 14:58, Sunil V L wrote: >>> Sstc extension allows to program the timer and receive the interrupt >>> without using an SBI call. This reduces the latency to generate the timer >>> interrupt. So, detect whether Sstc extension is supported and use the >>> stimecmp register directly to program the timer interrupt. >>> >>> Cc: Gerd Hoffmann <kra...@redhat.com> >>> Cc: Rahul Kumar <rahul1.ku...@intel.com> >>> Cc: Laszlo Ersek <ler...@redhat.com> >>> Cc: Ray Ni <ray...@intel.com> >>> Cc: Andrei Warkentin <andrei.warken...@intel.com> >>> Signed-off-by: Sunil V L <suni...@ventanamicro.com> >>> --- >>> .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + >>> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 ++ >>> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +++++++++++++++++-- >>> 3 files changed, 31 insertions(+), 2 deletions(-) >>> >>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> index aba660186dc0..f2a2cf12caef 100644 >>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf >>> @@ -41,6 +41,7 @@ [Sources.RISCV64] >>> Timer.c >>> >>> [Pcd] >>> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES >>> gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES >>> >>> [Protocols] >>> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> index 9b3542230cb5..5e5071b3f0b2 100644 >>> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h >>> @@ -26,6 +26,8 @@ >>> // >>> #define DEFAULT_TIMER_TICK_DURATION 100000 >>> >>> +#define RISCV_CPU_FEATURE_SSTC_BITMASK 0x2 >> >> (1) Not a bug by any means, but BIT1 might read more idiomatic. >> > I misunderstood your comment. Will use BIT1 instead of 0x2.
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