Hi,
On 11/27/2013 08:03 AM, David Carne wrote:
If mibuild is to be merged into / maintained with migen - could we
consider removing the platforms/ tree from migen (and moving it into
misoc)? It seems to me that most of the contents of the platforms
folder is milkymist-specific.
Not really,
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OK, I'm back after another debugging session.
With the soc-mixxeo-ports23 bitstream I get something like this in console
when connecting to port HDMI3:
dvisampler1: PLL locked
IDELAY busy timeout
dvisampler1: delays calibrated
dvisampler1: phase init OK
dvisampler1: ph: 000 //
Hi,
On 11/27/2013 01:44 PM, Adrian Byszuk wrote:
With the soc-mixxeo-ports23 bitstream I get something like this in console
when connecting to port HDMI3:
dvisampler1: PLL locked
IDELAY busy timeout
dvisampler1: delays calibrated
dvisampler1: phase init OK
dvisampler1: ph: 000
On 11/27/2013 04:27 AM, Robert Jördens wrote:
That sounds good! It makes reusing the soc components much simpler.
But I think misoclib and make.py should become a python package. Then,
one could separate one's own history from that of misoc.
A project using misoc would comprise only the custom
On 27/11/13 13:55, Sébastien Bourdeauducq wrote:
Hi,
On 11/27/2013 01:44 PM, Adrian Byszuk wrote:
With the soc-mixxeo-ports23 bitstream I get something like this in console
when connecting to port HDMI3:
dvisampler1: PLL locked
IDELAY busy timeout
dvisampler1: delays calibrated
On 11/27/2013 03:55 PM, Adrian Byszuk wrote:
Does it keep printing that (it should repeat at ~1Hz), or does it go
into the disconnected state immediately after?
It goes into disconnected state immediately after. Basically screen is
flooded with these messages.
That could be the Spartan-6
Hi,
can we take this discussion to the developer mailing list? You may need
to subscribe at http://lists.milkymist.org so your messages do not go
into the moderation queue and you'll get the possible answers from other
people.
On 11/27/2013 05:49 PM, Victor Lyuboslavsky wrote:
I tried migen,
On 11/27/2013 05:49 PM, Victor Lyuboslavsky wrote:
This would help with having a more streamlined synthesis flow.
Have you tried the Migen tutorial with Mibuild?
http://milkymist.org/3/migen-tutorial.pdf
Do you see improvements for it?
Sebastien
___
Now it looks much better. I'm still not able to get EDID information (will look
into that),
but manually enabling HDMI output seems to work and I can see such output on
console:
dvisampler0: ph: 8 135 // charsync:111 [4 4 4] // WER: 0 0 0 //
chansync:1 // res:1024x768
dvisampler0:
Regarding the streamlined synthesis flow, my primary motivation is figure
out how to add easy-to-use Migen synthesis to EDA Playground.
1. having a script that converts design.py - design.v would be ideal, but
it doesn't exist
2. Ask the user to enter the top level Module class and the list of
On Wed, Nov 27, 2013 at 7:55 AM, Sébastien Bourdeauducq
sebastien.bourdeaud...@lekernel.net wrote:
On 11/27/2013 04:27 AM, Robert Jördens wrote:
That sounds good! It makes reusing the soc components much simpler.
But I think misoclib and make.py should become a python package. Then,
one could
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