Re: [PATCH] docs/user: add docs for riscv/kendrytek210 BSP variant

Hi Alan, > On Wed, 2023-03-29 at 10:32 -0400, Alan Cudmore wrote: > > This patch adds the documentation for building and running RTEMS on > the Kendryte K210 RISC-V SoC. The generic riscv introducion > was re-arranged to list the multilib variants then the specific > hardware targets. In

Re: [PATCH 1/3] bsps/riscv: Make SMP start more robust

> On Thu, 2023-03-16 at 09:59 +0100, Sebastian Huber wrote: > > In SMP configurations, check that we run on a configured > processor. If not, > then there is not much what can be done since we do not have a stack > available > for this processor. Just loop forever in this case. Do this in >

Re: [PATCH v2 0/3] bsps/riscv: Add kendrytek210 riscv BSP variant

I have tested it on the renode.io simulator and working fine. Regards Padmarao > On Wed, 2023-03-15 at 22:04 -0400, Alan Cudmore wrote: > > Version 2 patch updates: Separated the device tree source and encoded > device tree blob into a separate patch, added the license text to > k210.h,

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

> On Tue, 2023-03-14 at 13:37 +0100, Sebastian Huber wrote: > > On 14.03.23 13:31, padmarao.beg...@microchip.com wrote: > > Hi Sebastian, > > > > > On Mon, 2023-03-06 at 14:11 +0100, Sebastian Huber wrote: > > > > > > > > > On 06.03.23 13:00,padmarao.beg...@microchip.com wrote: > > > > > On

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

Hi Sebastian, >On Mon, 2023-03-06 at 14:11 +0100, Sebastian Huber wrote: > > > On 06.03.23 13:00, padmarao.beg...@microchip.com wrote: > > > On Mon, 2023-03-06 at 11:19 +0100, Sebastian Huber wrote: > > > > > > On 06.03.23 10:24,padmarao.beg...@microchip.com wrote: > > > > Hi Sebastian, > > >

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

> On Mon, 2023-03-06 at 14:11 +0100, Sebastian Huber wrote: > > On 06.03.23 13:00, padmarao.beg...@microchip.com wrote: > > > On Mon, 2023-03-06 at 11:19 +0100, Sebastian Huber wrote: > > > > > > On 06.03.23 10:24,padmarao.beg...@microchip.com wrote: > > > > Hi Sebastian, > > > > > > > > > On

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

> On Mon, 2023-03-06 at 11:19 +0100, Sebastian Huber wrote: > > On 06.03.23 10:24, padmarao.beg...@microchip.com wrote: > > Hi Sebastian, > > > > > On Mon, 2023-03-06 at 09:41 +0100, Sebastian Huber wrote: > > > > > > On 06.03.23 09:37, padmarao.beg...@microchip.com wrote: > > > > > Is > > > >

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

Hi Sebastian, > On Mon, 2023-03-06 at 09:41 +0100, Sebastian Huber wrote: > > On 06.03.23 09:37, padmarao.beg...@microchip.com wrote: > > > Is > > > the claim complete message ignored if the interrupt is disabled? > > > > > Yes. > > Is this an intended and documented behaviour of the PLIC?

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

Hi Sebastian, > On Mon, 2023-03-06 at 08:01 +0100, Sebastian Huber wrote: > > Hello Padmarao, > > On 03.03.23 15:55, padmarao.beg...@microchip.com wrote: > > > On Thu, 2023-03-02 at 15:18 +0100, Sebastian Huber wrote: > > > > > > > > > On 27.02.23 16:51, Padmarao Begari wrote: > > > > The

Re: [PATCH] bsps/riscv: Clear interrupt complete before disable

Hi Sebastian, > On Thu, 2023-03-02 at 15:18 +0100, Sebastian Huber wrote: > > > On 27.02.23 16:51, Padmarao Begari wrote: > > The interrupt complete should clear with the interrupt > > number before disabling the interrupt in the PLIC to > > get the next interrupt. > > Which problem does this

Re: [PATCH rtems-libbsd 3/3] freebsd/cgem: Add weak symbol for riscv

Hi will, > On Wed, 2023-03-01 at 08:27 -0600, Will wrote: > > This functionality is ideally implemented in a platform-specific > system level control register (SLCR) driver similar to ZynqMP and > Versal. You could also just leave it as-is since the default does > exactly the same thing.

Re: [PATCH rtems-libbsd 2/3] freebsd/cgem: Read clock frequency from device tree

Hi will, > On Wed, 2023-03-01 at 08:20 -0600, Will wrote: > > On Tue, Feb 28, 2023 at 11:57 PM Padmarao Begari < > padmarao.beg...@microchip.com> wrote: > > Read the clock frequency from the device tree and use it to > > calculate the mdc clock divider for the MII bus if not found > > then

Re: [PATCH rtems-libbsd 1/3] freebsd/cgem: Add phy address to read it from device tree

Hi Will, Thanks for review comments. > On Wed, 2023-03-01 at 08:10 -0600, Will wrote: > > On Tue, Feb 28, 2023 at 11:57 PM Padmarao Begari < > padmarao.beg...@microchip.com> wrote: > > Read the phy address from the device tree and use it to > > find the phy device if not found then search

bsps/riscv: interrupt not occurred

Hi, While testing the Candence GEM driver of RTEMS-FreeBSD with the RTEMS on the PolarFire SoC Icicle Kit found one issue. Issue:The Interrupt is disabled before clearing the interrupt complete in the PLIC because of this the same interrupt is not occurred next time. Resolved: Clear the

Re: bsps/riscv: interrupt number mismatch

> On Mon, 2022-11-21 at 11:20 +0100, Sebastian Huber wrote: > > On 21/11/2022 11:17, padmarao.beg...@microchip.com wrote: > > > To which number would you map the software and timer interrupts? > > > > > The Software and Timer interrupts(numbers 0 & 1) are mapped by > > the Machine cause register

Re: bsps/riscv: interrupt number mismatch

Hi Sebastian, > On Mon, 2022-11-21 at 10:53 +0100, Sebastian Huber wrote: > > On 21/11/2022 10:50, padmarao.beg...@microchip.com wrote: > > The interrupt number(vector) mention in the device tree node is > > working > > when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and > > later

bsps/riscv: interrupt number mismatch

Hi, The interrupt number(vector) mention in the device tree node is working when the driver is used the RISCV_INTERRUPT_VECTOR_EXTERNAL() and later called the RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX() in the RTEMS but the interrupt number is decreased by 2 when registering the interrupt from the

Re: [PATCH v2] zynqmp: Add support for the CFC-400X

Hi Kinsey, > On Thu, 2022-11-10 at 07:55 -0600, Kinsey Moore wrote: > > Hi Padmarao, > More compatibles can be added later if necessary to both the device > tree in RTEMS and the driver in RTEMS-LibBSD, but I don't see the > need for either at the moment since the ethernet portion of the >

Re: [PATCH v2] zynqmp: Add support for the CFC-400X

Hi Kinsey, The ethernet compatible "cdns,gem" is mentioned in the device tree, even I used same for PolarFire SoC BSP but later realised that common compatible for the candence GEM is "cdns,macb" used in U-Boot and Linux. Can we go with compatible "cdns,gem"? or will we update with "cdns,macb"

Re: bsp/riscv: Store/AMO address misaligned trap occured

Hi Sebastian, > On Fri, 2022-11-04 at 14:03 +0100, Sebastian Huber wrote: > On 04/11/2022 10:49, Sebastian Huber wrote: > > On 04/11/2022 10:44, padmarao.beg...@microchip.com wrote: > > > Hi Sebastian, > > > > > > > On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote: > > > > > > > > On

Re: bsp/riscv: Store/AMO address misaligned trap occured

Hi Sebastian, > On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote: > > On 03/11/2022 06:40, padmarao.beg...@microchip.com wrote: > > > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote: > > > > > > t0 contains the address of .Lsecondary_processor_go > > > > > > start.S has: > > >

Re: bsp/riscv: Store/AMO address misaligned trap occured

> On Thu, 2022-11-03 at 05:40 +, padmarao.beg...@microchip.com wrote: > Hi Gedare, > > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote: > > > > t0 contains the address of .Lsecondary_processor_go > > > > start.S has: > > ```asm > > #if __riscv_xlen == 32 > > .align 2 > > #elif

Re: bsp/riscv: Store/AMO address misaligned trap occured

Hi Gedare, > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote: > > t0 contains the address of .Lsecondary_processor_go > > start.S has: > ```asm > #if __riscv_xlen == 32 > .align 2 > #elif __riscv_xlen == 64 > .align 3 > #endif > > .Lsecondary_processor_go: > ``` > Can you confirm

bsp/riscv: Store/AMO address misaligned trap occured

Hi Sebastian, The "Store/AMO address misaligned" trap occured in the "start.S" at "amoswap.w zero, zero, 0(t0)" while testing the sample application with the latest RTEMS master for RISC-V on the Microchip PolarFire SoC. The trap occured after this

RE: [PATCH rtems-docs v2] user/bsps: Update riscv for PolarFire SoC

Hi, The Patch v1 was reviewed by Alan, update few comments, and submitted Patch v2. https://lists.rtems.org/pipermail/devel/2022-October/073469.html - Patch v1 https://lists.rtems.org/pipermail/devel/2022-October/073528.html - Patch v2 Can you please review or merge it to rtems-docs git?

rtems-libbsd support RISC-V or not

Hi, Is the rtems-libbsd support the risc-v architecture BSP or not? Because I am trying to use existing FreeBSD ethernet and mmc driver for Microchip PolarFore SoC(RTEMS RISC-V BSP variant). Regards Padmarao ___ devel mailing list devel@rtems.org

Re: Visibility of RISCV_BOOT_HARTID

> On Thu, 2022-10-13 at 06:27 +0200, Sebastian Huber wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On 12/10/2022 16:36, Joel Sherrill wrote: > > Hi > > > > I was looking at the bsp default settings for sparc/leon3 to show > > someone

Re: Visibility of RISCV_BOOT_HARTID

Hi Joel, We can do like below to remove visibility of RISCV_BOOT_HARTID from other architecture configurations and only visible to RISC-V. Changes in spec/build/cpukits 1. Remove "optboothartid" build-dependency from "cpuotps" 2. Add the "cpuriscvhartid" to generate the "hartid.h" using

Re: [PATCH rtems-docs] user/bsps: Update riscv for PolarFire SoC

Hi Alan, Thank you for review. I will update same in Patch v2. Regards Padmarao From: Alan Cudmore Sent: Wednesday, October 5, 2022 7:52 PM To: Padmarao Begari - I30397 Cc: devel@rtems.org ; Cyril Jean - M31571 Subject: Re: [PATCH rtems-docs] user/bsps:

Re: [PATCH] bsps: Improve riscv console FDT parsing

Hi Alan, I tested this patch and it is working fine on the PolarFire SoC Icicle Kit. Thanks & Regards Padmarao > On Thu, 2022-09-29 at 12:19 -0400, Alan Cudmore wrote: > Hi Padmarao, > Could you try this patch on your Polarfire board? It works on the > generic QEMU BSP and the BSP I am working

Re: [PATCH v2 0/4] Microchip PolarFire SoC support

Hi Chris, Thank You for a tar file build, will try to build same using your repo. Regards Padmarao > On Wed, 2022-09-21 at 14:34 +1000, Chris Johns wrote: > > On 21/9/2022 3:03 am, Joel Sherrill wrote: > > I have pushed this patch set. Please check that the merge is OK and > > follow up > >

Re: [PATCH v2 0/4] Microchip PolarFire SoC support

Hi Joel, > On Tue, 2022-09-20 at 12:03 -0500, Joel Sherrill wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > I have pushed this patch set. Please check that the merge is OK and > follow up with an update to the Users Guide for those looking

Re: [PATCH v2 0/4] Microchip PolarFire SoC support

RTEMS SMP on the Microchip PolarFire Icicle Kit Test Procedure: 1. Create the "config.ini" file with below content at rtems root [riscv/mpfs64imafdc] BUILD_TESTS = True RTEMS_POSIX_API=True RTEMS_SMP = True BSP_START_COPY_FDT_FROM_U_BOOT=False

Re: [PATCH v2 0/4] Microchip PolarFire SoC support

Hi Alan, > On Mon, 2022-09-19 at 12:49 -0400, Alan Cudmore wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > Hi Padmarao, > The patches apply cleanly and build for me. What is the recommended > config.ini file for this BSP? > I used: >