On Sat, Feb 8, 2014 at 1:11 AM, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 12:02 PM, Sudeep Holla wrote:
>> On 07/02/14 17:37, Nishanth Menon wrote:
>>> On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
>>
>> [...]
>>
Yes I think its counter-intuitive as it's visible to the userspace
On Fri, Feb 7, 2014 at 11:32 PM, Sudeep Holla wrote:
> On 07/02/14 17:37, Nishanth Menon wrote:
>> On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
>
> [...]
>
>>> Yes I think its counter-intuitive as it's visible to the userspace(list of
>>> frequencies and the boost parameters are exposed t
On Fri, 7 Feb 2014, Marek Belisko wrote:
> Signed-off-by: NeilBrown
> Signed-off-by: Marek Belisko
> ---
> Based on Neil's patch and extend for documentation and bindings include.
>
> .../bindings/net/rfkill/rfkill-relugator.txt | 28
^
On Fri, Feb 7, 2014 at 9:31 PM, Sudeep Holla wrote:
> On 07/02/14 15:19, Thomas Abraham wrote:
>> From: Thomas Abraham
>>
>> Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
>> support for CPU boost mode. This patch adds support for finding available
>> boost frequencies from
On Sat, Feb 8, 2014 at 12:33 AM, Hans de Goede wrote:
> The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
> through a single set of registers. Besides this there are also some other
> phy related bits which need poking, which are per phy, but shared between the
> ohci and eh
On 02/07, Stanimir Varbanov wrote:
> Add the necessary DT node to probe the rng driver on
> msm8974 platforms.
>
Looks good. We should add it to msm8960-cdp and enable the driver
in the defconfig as well.
> Signed-off-by: Stanimir Varbanov
Acked-by: Stephen Boyd
--
Qualcomm Innovation Cente
On 01/30, Georgi Djakov wrote:
> @@ -75,17 +110,389 @@ struct sdhci_msm_host {
> };
>
> /* MSM platform specific tuning */
> -int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
> +static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
> +{
> + u32 wait_cnt
On 02/04, Andy Gross wrote:
> diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
> new file mode 100644
> index 000..214250c
> --- /dev/null
> +++ b/drivers/dma/qcom_bam_dma.c
> @@ -0,0 +1,1066 @@
> +/*
> + * QCOM BAM DMA engine driver
Can you please move this down into the c
Signed-off-by: Courtney Cavin
---
drivers/mailbox/Kconfig | 1 -
drivers/mailbox/mailbox-omap2.c | 315 +---
2 files changed, 132 insertions(+), 184 deletions(-)
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index ae6b09b..a592a5a 10
This framework is no longer needed, and the users should move over to
the new common framework. Mark the existing implementations as broken,
and deprecate the api, as a stop-gap.
Signed-off-by: Courtney Cavin
---
drivers/mailbox/Kconfig| 19 +-
drivers/mailbox/Makefile | 1 -
d
Signed-off-by: Courtney Cavin
---
.../devicetree/bindings/mailbox/mailbox.txt| 44 ++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt
b/Docum
Signed-off-by: Courtney Cavin
---
drivers/mailbox/Kconfig | 1 -
drivers/mailbox/mailbox-omap1.c | 153 +++-
2 files changed, 73 insertions(+), 81 deletions(-)
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 6befc6e..ae6b09b 1006
We don't remove the legacy methods here, but we mark them as deprecated
in the hopes that people with the ability to properly test modifications
can adapt its users.
Signed-off-by: Courtney Cavin
---
drivers/mailbox/pl320-ipc.c | 258 ++--
include/linux/ma
There is currently no common framework for mailbox drivers, so this is my
attempt to come up with something suitable. There seems to be a need for
making this generic, so I have attempted to do just that. Most of this is
modeled pretty strongly after the pwm core, with some influences from the cl
The mailbox drivers are fragmented, and some implement their own core.
Unify the drivers and implement common functionality in a framework.
Signed-off-by: Courtney Cavin
---
drivers/mailbox/Makefile | 1 +
drivers/mailbox/core.c | 573 +++
include/
On Thu, Feb 6, 2014 at 2:18 AM, Liviu Dudau wrote:
> On Wed, Feb 05, 2014 at 10:26:27PM +, Tanmay Inamdar wrote:
>> Hello Liviu,
>>
>> I did not get the first email of this particular patch on any of
>> subscribed mailing lists (don't know why), hence replying here.
>
> Strange, it shows in th
On 2/7/2014 12:51 PM, Joe Perches wrote:
> On Fri, 2014-02-07 at 11:38 -0800, Frank Rowand wrote:
>> On 2/6/2014 9:11 PM, Joe Perches wrote:
>>> For patch 1, what checkpatch bug might that be?
> []
>> Sorry, it is patch 2, not patch 1 ("[PATCH v5 02/14] clk: Add
>> set_rate_and_parent() op"):
>>
>
Hi,
On 02/07/2014 11:36 PM, Maxime Ripard wrote:
Hi Hans,
It looks very nice, I just have a few comments below though.
On Fri, Feb 07, 2014 at 05:33:21PM +0100, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Bes
Hi,
On 02/07/2014 11:31 PM, Greg Kroah-Hartman wrote:
On Fri, Feb 07, 2014 at 04:36:39PM +0100, Hans de Goede wrote:
Hi Greg,
Here is v9 of my ohci-platform and ehci-platform patchset, It is just a
rebase (with some manual conflict resolution), to make it easier for you
to throw this into usb-
On Mon, Jan 13, 2014 at 4:19 PM, Suman Anna wrote:
> This patch adds three new OF helper functions to use/request
> locks from a hwspinlock device instantiated through a
> device-tree blob.
Nice, I ran in to the problem of needing a probe deferral on a
hwspinlock earlier this week so I implemente
2014-02-05 David Laight :
> From: Florian Fainelli
>> It would be good to explain exactly how your hardware is broken
>> exactly. I really do not think that such a fine-grained setting where
>> you could disable, e.g: 100BaseT_Full, but allow 100BaseT_Half to
>> remain usable makes that much sense.
Hi Hans,
It looks very nice, I just have a few comments below though.
On Fri, Feb 07, 2014 at 05:33:21PM +0100, Hans de Goede wrote:
> The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
> through a single set of registers. Besides this there are also some other
> phy related
On Fri, Feb 7, 2014 at 8:50 AM, Mark Rutland wrote:
> Hi Rob,
>
> On Fri, Feb 07, 2014 at 02:33:27PM +, Rob Herring wrote:
>> On Thu, Feb 6, 2014 at 8:41 AM, James Hogan wrote:
>> > Hi Rob,
>> >
>> > On 06/02/14 14:33, Rob Herring wrote:
>> >> On Fri, Jan 17, 2014 at 7:58 AM, James Hogan
>>
On Fri, Feb 07, 2014 at 04:36:39PM +0100, Hans de Goede wrote:
> Hi Greg,
>
> Here is v9 of my ohci-platform and ehci-platform patchset, It is just a
> rebase (with some manual conflict resolution), to make it easier for you
> to throw this into usb-next, there are no other changes.
I've applied
Hello
The following patchset adds support for the SD/MMC host found in the Allwinner
SoCs.
It contains all the necessary modifications for clock environment and also the
device
tree script modification which add it to all the boards using it.
The clock environment function needed for phase offset
Signed-off-by: David Lanzendörfer
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +
arch/arm/boot/dts/sun7i-a20.dtsi
From: Emilio López
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López
---
drivers/clk/sunxi/clk-factors.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/sunxi/clk-
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one f
Signed-off-by: David Lanzendörfer
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun4i-a10-a1000.dts |8
arch/arm/boot/dts/sun4i-a10-cubieboard.dts |8
arch/arm/boot/dts/sun4i-a10.dtsi | 54
3 files changed, 70 insertions(+)
di
From: Emilio López
Signed-off-by: Emilio López
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sun
Signed-off-by: David Lanzendörfer
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +++
arch/arm/boot/dts/sun5i-a10s.dtsi| 44 ++
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15
arch/arm/b
From: Hans de Goede
Signed-off-by: Hans de Goede
---
include/linux/clk/sunxi.h | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000..1e
The default machine descriptor satisfies our needs now that the
SMP ops are set based on the enable-method in devicetree and we're
part of the multiplatform kernel. Drop this file.
Signed-off-by: Stephen Boyd
---
arch/arm/mach-msm/Makefile | 1 -
arch/arm/mach-msm/board-dt.c | 27
Document the Krait PMU compatible string.
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/pmu.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
b/Documentation/devicetree/bindings/arm/pmu.txt
On Fri, 2014-02-07 at 11:38 -0800, Frank Rowand wrote:
> On 2/6/2014 9:11 PM, Joe Perches wrote:
> > For patch 1, what checkpatch bug might that be?
[]
> Sorry, it is patch 2, not patch 1 ("[PATCH v5 02/14] clk: Add
> set_rate_and_parent() op"):
>
>WARNING: Multiple spaces after return type
>
Signed-off-by: NeilBrown
Signed-off-by: Marek Belisko
---
Based on Neil's patch and extend for documentation and bindings include.
.../bindings/net/rfkill/rfkill-relugator.txt | 28
include/dt-bindings/net/rfkill-regulator.h | 23 +
net/rfkill/rfkill-r
On 2/6/2014 9:11 PM, Joe Perches wrote:
> On Thu, 2014-02-06 at 20:15 -0800, Frank Rowand wrote:
>> On 1/15/2014 10:47 AM, Stephen Boyd wrote:
>>> The first breaks a reset-controller include ordering requirement. It got
>>> an ack so I think we're ok for it to go through the clock tree.
>>>
>>
>> <
On Fri, Feb 7, 2014 at 12:02 PM, Sudeep Holla wrote:
> On 07/02/14 17:37, Nishanth Menon wrote:
>> On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
>
> [...]
>
>>> Yes I think its counter-intuitive as it's visible to the userspace(list of
>>> frequencies and the boost parameters are exposed t
On Wed, Feb 05, 2014 at 02:05:02PM +0100, Maxime Ripard wrote:
> Hi everyone,
>
> This patchset brings support for the SPI controller found in the
> Allwinner A31 SoC.
>
> Even though the controller supports DMA, the driver only supports PIO
> mode for now. This driver will be used to bring up an
On Fri, Feb 07, 2014 at 04:21:50PM +0100, Hans de Goede wrote:
> From: Roman Byshko
>
> Add register definitions for the usb-clk register found on sun4i, sun5i and
> sun7i SoCs.
>
> Signed-off-by: Roman Byshko
> Signed-off-by: Hans de Goede
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime
On Fri, Feb 07, 2014 at 04:21:49PM +0100, Hans de Goede wrote:
> The usb-clk register is special in that it not only contains clk gate bits,
> but also has a few reset bits. This commit adds support for this by allowing
> gates type sunxi clks to also register a reset controller.
>
> Signed-off-by
On Fri, Feb 07, 2014 at 05:52:34PM +, Mark Brown wrote:
> On Fri, Feb 07, 2014 at 11:32:07AM -0600, Andy Gross wrote:
> > On Fri, Feb 07, 2014 at 11:52:33AM +0200, Ivan T. Ivanov wrote:
>
[... snip ...]
> > The platform doesn't have support for PM right now. So it's probably
> > better to
On Fri, Feb 07, 2014 at 01:05:16PM +0800, Sean Cross wrote:
> Novena uses an ES8328 audio codec connected via I2S.
The CODEC looked pretty simple, can this use simple-card?
> + /* Headphone jack detection */
> + if (gpio_is_valid(data->jack_gpio)) {
> + ret = snd_soc_jack_new(
On Fri, Feb 07, 2014 at 01:05:15PM +0800, Sean Cross wrote:
Please use subject likes matching the style for the subsystem. If your
changelog looks different to others in the same area it probably needs
an update.
In general this looks like it should be making much more use of the
framework rathe
On Fri, Feb 07, 2014 at 11:46:43AM -0600, Josh Cartwright wrote:
> On Fri, Feb 07, 2014 at 05:31:08PM +, Mark Brown wrote:
> > That's not ARM only and I thought we were getting generic versions of it
> > anyway? ARMv8, MIPS, Microblaze, Hexagon and SH also define it.
> Okay, that's fair. I'
On Fri, Feb 07, 2014 at 11:32:07AM -0600, Andy Gross wrote:
> On Fri, Feb 07, 2014 at 11:52:33AM +0200, Ivan T. Ivanov wrote:
To repeat what I said in my earlier e-mail please delete irrelevant
context from your mails so any new content you are including is
discoverable.
> > Did you see any parti
On 09:10 Fri 07 Feb , Jason Cooper wrote:
> Hi Sascha,
>
> + Grant Likely, Ian Campbell, devicetree ML
>
> This discussion started on the barebox bootloader mailinglist
>
> On Fri, Feb 07, 2014 at 08:13:32AM +0100, Sascha Hauer wrote:
> > It's becoming more obvious that devicetree maintenanc
On 07/02/14 17:37, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
[...]
>> Yes I think its counter-intuitive as it's visible to the userspace(list of
>> frequencies and the boost parameters are exposed through sysfs)
>
> That will be a different problem -> as curre
On Fri, Feb 07, 2014 at 05:31:08PM +, Mark Brown wrote:
> On Fri, Feb 07, 2014 at 11:20:51AM -0600, Josh Cartwright wrote:
> > On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote:
> > > On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
> > > > config SPI_QUP
> > >
On Fri, Feb 07, 2014 at 07:40:45AM -0300, Ezequiel Garcia wrote:
> Well, this is related to the discussion about the bootloader not
> reseting the watchdog properly, provoking spurious watchdog triggering.
>
> Jason Gunthorpe explained [1] that we needed a particular sequence:
>
> 1. Disable WD
On Fri, Feb 7, 2014 at 11:37 AM, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
>>
>> Yes I thought of exactly similar clock setup, but was not convinced that it
>> should be part of OPP. In that case it looks like we are trying to represent
>> clock internals throug
On Fri, Feb 7, 2014 at 11:31 AM, Sudeep Holla wrote:
>
> Yes I thought of exactly similar clock setup, but was not convinced that it
> should be part of OPP. In that case it looks like we are trying to represent
> clock internals through some OPP bindings.
And this series (rightly) does not make
On Fri, Feb 07, 2014 at 11:52:33AM +0200, Ivan T. Ivanov wrote:
>
> Hi Andy,
>
> On Fri, 2014-02-07 at 01:39 -0600, Andy Gross wrote:
> > On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote:
> > > From: "Ivan T. Ivanov"
> > >
> > > Qualcomm Universal Peripheral (QUP) core is an AHB
On 07/02/14 16:43, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 10:28 AM, Sudeep Holla wrote:
>> On 07/02/14 16:15, Sudeep Holla wrote:
>>> On 07/02/14 15:19, Thomas Abraham wrote:
From: Thomas Abraham
Add a new optional boost-frequency binding for specifying the frequencies
On Fri, Feb 07, 2014 at 11:20:51AM -0600, Josh Cartwright wrote:
> On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote:
> > On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
> > > config SPI_QUP
> > > tristate "Qualcomm SPI Support with QUP interface"
> > >
On Fri, Feb 07, 2014 at 07:28:29PM +0530, Keerthy wrote:
> On Thursday 06 February 2014 11:20 AM, Keerthy wrote:
> If there are no further comments on this could you
> please pull this?
You've sent this mail a day after sending the original patch, don't do
that.
signature.asc
Description: Digit
Hey Mark-
On Fri, Feb 07, 2014 at 05:18:34PM +, Mark Brown wrote:
> On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
>
> > config SPI_QUP
> > tristate "Qualcomm SPI Support with QUP interface"
> > depends on OF
> > depends on ARM
>
> Do
On Fri, Feb 07, 2014 at 10:51:27AM -0600, Josh Cartwright wrote:
> config SPI_QUP
> tristate "Qualcomm SPI Support with QUP interface"
> depends on OF
> depends on ARM
Does this really depend on ARM? If so why?
> depends on ARCH_MSM_
On Fri, Feb 07, 2014 at 04:34:25PM -, dsned...@codeaurora.org wrote:
> > From: "Ivan T. Ivanov"
> >
> > Qualcomm Universal Peripheral (QUP) core is an AHB slave that
> > provides a common data path (an output FIFO and an input FIFO)
Folks, please remember to delete irrelevant context from you
On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote:
This looks mostly good, there's a few odd things and missing use of
framework features.
> Qualcomm Universal Peripheral (QUP) core is an AHB slave that
> provides a common data path (an output FIFO and an input FIFO)
> for serial per
On Fri, Feb 07, 2014 at 01:39:52AM -0600, Andy Gross wrote:
> On Thu, Feb 06, 2014 at 06:57:48PM +0200, Ivan T. Ivanov wrote:
> > From: "Ivan T. Ivanov"
> >
> > Qualcomm Universal Peripheral (QUP) core is an AHB slave that
> > provides a common data path (an output FIFO and an input FIFO)
> > for
On Fri, Feb 07, 2014 at 10:44:53AM -0500, Jason Cooper wrote:
> On Fri, Feb 07, 2014 at 12:17:28PM -0300, Ezequiel Garcia wrote:
> > On Fri, Feb 07, 2014 at 05:38:09AM -0800, Guenter Roeck wrote:
> > > On 02/07/2014 02:40 AM, Ezequiel Garcia wrote:
> > > > On Thu, Feb 06, 2014 at 06:02:56PM -0800,
On Fri, Feb 7, 2014 at 10:28 AM, Sudeep Holla wrote:
> On 07/02/14 16:15, Sudeep Holla wrote:
>> On 07/02/14 15:19, Thomas Abraham wrote:
>>> From: Thomas Abraham
>>>
>>> Add a new optional boost-frequency binding for specifying the frequencies
>>> usable in boost mode.
>>>
>>> Cc: Nishanth Menon
> From: "Ivan T. Ivanov"
>
> Qualcomm Universal Peripheral (QUP) core is an AHB slave that
> provides a common data path (an output FIFO and an input FIFO)
> for serial peripheral interface (SPI) mini-core. SPI in master mode
> support up to 50MHz, up to four chip selects, and a programmable
> dat
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between the
ohci and ehci controllers, so these are also controlled from this new phy
On Thu, Feb 06, 2014 at 06:03:21PM +, Adam Thomson wrote:
> Signed-off-by: Adam Thomson
Applied, thanks.
signature.asc
Description: Digital signature
On Thu, Feb 06, 2014 at 06:03:13PM +, Adam Thomson wrote:
> Signed-off-by: Adam Thomson
Applied, thanks.
signature.asc
Description: Digital signature
Am Freitag, den 07.02.2014, 16:21 +0100 schrieb Hans de Goede:
> The usb-clk register is special in that it not only contains clk gate bits,
> but also has a few reset bits. This commit adds support for this by allowing
> gates type sunxi clks to also register a reset controller.
>
> Signed-off-by
On 07/02/14 16:15, Sudeep Holla wrote:
> On 07/02/14 15:19, Thomas Abraham wrote:
>> From: Thomas Abraham
>>
>> Add a new optional boost-frequency binding for specifying the frequencies
>> usable in boost mode.
>>
>> Cc: Nishanth Menon
>> Cc: Lukasz Majewski
>> Cc: Rob Herring
>> Cc: Pawel Moll
On Fri, Feb 07, 2014 at 04:25:04PM +, Mark Brown wrote:
> On Thu, Feb 06, 2014 at 06:03:09PM +, Adam Thomson wrote:
> > Signed-off-by: Adam Thomson
>
> This doesn't apply against my current for-next or v3.14-rc1, can you
> please check and resend?
Ugh, sorry - it'll be due to patch 1 of
On Thu, Feb 06, 2014 at 06:03:09PM +, Adam Thomson wrote:
> Signed-off-by: Adam Thomson
This doesn't apply against my current for-next or v3.14-rc1, can you
please check and resend?
signature.asc
Description: Digital signature
Add base driver for the ImgTec Infrared decoder block. The driver is
split into separate components for raw (software) decode and hardware
decoder which are in following commits.
Signed-off-by: James Hogan
Cc: Mauro Carvalho Chehab
Cc: linux-me...@vger.kernel.org
Cc: Grant Likely
Cc: Rob Herrin
On 07/02/14 15:19, Thomas Abraham wrote:
> From: Thomas Abraham
>
> Add a new optional boost-frequency binding for specifying the frequencies
> usable in boost mode.
>
> Cc: Nishanth Menon
> Cc: Lukasz Majewski
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc:
Hi,
On 01/15/2014 11:52 PM, Maxime Ripard wrote:
Hi Hans,
Please keep me in CC for all the Allwinner-related patches.
Ok will do.
On Tue, Jan 14, 2014 at 11:58:25PM +0100, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of
On 07/02/14 15:19, Thomas Abraham wrote:
> From: Thomas Abraham
>
> Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
> support for CPU boost mode. This patch adds support for finding available
> boost frequencies from device tree and marking them as usable in boost mode.
>
>
Hi,
On 01/15/2014 04:00 PM, Kishon Vijay Abraham I wrote:
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need po
From: Thomas Abraham
The clock blocks within the CMU_CPU clock domain are put together into a
new composite clock type called the cpu clock. This clock type requires
configuration data that will be atomically programmed in the multiple
clock blocks encapsulated within the cpu clock type when the
On 02/07/2014 09:38 AM, Thomas Abraham wrote:
[...]
>>> diff --git a/drivers/base/power/opp.c b/drivers/base/power/opp.c
>>> index fa41874..b636826 100644
>>> --- a/drivers/base/power/opp.c
>>> +++ b/drivers/base/power/opp.c
>>> @@ -628,7 +628,8 @@ int dev_pm_opp_init_cpufreq_table(struct device *d
Add device tree binding for ImgTec Consumer Infrared block, specifically
major revision 1 of the hardware.
Signed-off-by: James Hogan
Cc: Mauro Carvalho Chehab
Cc: linux-me...@vger.kernel.org
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicetree@vger
On Fri, Feb 07, 2014 at 12:17:28PM -0300, Ezequiel Garcia wrote:
> On Fri, Feb 07, 2014 at 05:38:09AM -0800, Guenter Roeck wrote:
> > On 02/07/2014 02:40 AM, Ezequiel Garcia wrote:
> > > On Thu, Feb 06, 2014 at 06:02:56PM -0800, Guenter Roeck wrote:
> > >> On 02/06/2014 09:20 AM, Ezequiel Garcia wr
On 16/01/2014 16:25, Boris BREZILLON :
> The hclk clock of the ohci node is referencing udphs_clk instead of
> uhphs_clk.
>
> Signed-off-by: Boris BREZILLON
Acked-by: Nicolas Ferre
Added to at91-3.14-fixes
Thanks,
> ---
> arch/arm/boot/dts/sama5d3.dtsi |2 +-
> 1 file changed, 1 inserti
On Fri, Feb 07, 2014 at 11:03:18AM +, Lee Jones wrote:
>
> Can you break this up please.
>
> Bindings should be separate to the binding document.
Right, fine. Figured as they were directly related they should be in one patch
but will separate them.
> Entangling the i2c_device_id table with
On Fri, Feb 7, 2014 at 8:59 PM, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 9:19 AM, Thomas Abraham wrote:
>> From: Thomas Abraham
>>
>> Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
>> support for CPU boost mode. This patch adds support for finding available
>> boost
Currently ehci-platform is only used in combination with devicetree when used
with some Via socs. By extending it to (optionally) get clks and a phy from
devicetree, and enabling / disabling those on power_on / off, it can be used
more generically. Specifically after this commit it can be used for
This uses the already documented devicetree booleans for this, see:
Documentation/devicetree/bindings/usb/usb-ehci.txt
Signed-off-by: Hans de Goede
---
drivers/usb/host/ehci-platform.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using ohci-platform from devicetree in various cases.
Specifically after this commit it can be used for the
On Fri, Feb 7, 2014 at 8:57 PM, Nishanth Menon wrote:
> On Fri, Feb 7, 2014 at 9:19 AM, Thomas Abraham wrote:
>> From: Thomas Abraham
>>
>> Add a new optional boost-frequency binding for specifying the frequencies
>> usable in boost mode.
>>
>> Cc: Nishanth Menon
>> Cc: Lukasz Majewski
>> Cc:
Hi Greg,
Here is v9 of my ohci-platform and ehci-platform patchset, It is just a
rebase (with some manual conflict resolution), to make it easier for you
to throw this into usb-next, there are no other changes.
Thanks & Regards,
Hans
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Note this commit uses the same devicetree booleans for this as the ones
already existing in the usb-ehci bindings, see:
Documentation/devicetree/bindings/usb/usb-ehci.txt
Signed-off-by: Hans de Goede
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 3 +++
drivers/usb/host/ohci-platform.
On Fri, Feb 7, 2014 at 9:19 AM, Thomas Abraham wrote:
> From: Thomas Abraham
>
> Add a new optional boost-frequency binding for specifying the frequencies
> usable in boost mode.
>
> Cc: Nishanth Menon
> Cc: Lukasz Majewski
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Camp
On Fri, Feb 7, 2014 at 9:19 AM, Thomas Abraham wrote:
> From: Thomas Abraham
>
> Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
> support for CPU boost mode. This patch adds support for finding available
> boost frequencies from device tree and marking them as usable in boo
From: Roman Byshko
Signed-off-by: Roman Byshko
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 316cab8..14d9696 100644
--- a/arch/arm/boot/dt
From: Roman Byshko
Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.
Signed-off-by: Roman Byshko
Signed-off-by: Hans de Goede
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +
drivers/clk/sunxi/clk-sunxi.c | 12
From: Roman Byshko
Signed-off-by: Roman Byshko
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 9 +
arch/arm/boot/dts/sun5i-a13.dtsi | 9 +
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm/boot/dts/sun5i-a10s.dt
From: Roman Byshko
Signed-off-by: Roman Byshko
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun4i-a10.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ebb4cd0..8d10f27 100644
--- a/arch/arm/boot/dt
The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.
Signed-off-by: Hans de Goede
---
drivers/clk/sunxi/clk-sunxi.c | 71
Hi All,
And here is v4 of my sunxi usb clks support series.
Changes since v2:
-rename the compatibilty strings from foo-usb-gates-clk to foo-usb-clk
Changes since v3:
-rename the compatibilty string for sun4i-usb-clk to sun4i-a10-usb-clk
Note the dts bits (patches 3-5) of this series depends on
On Fri, Feb 07, 2014 at 05:38:09AM -0800, Guenter Roeck wrote:
> On 02/07/2014 02:40 AM, Ezequiel Garcia wrote:
> > On Thu, Feb 06, 2014 at 06:02:56PM -0800, Guenter Roeck wrote:
> >> On 02/06/2014 09:20 AM, Ezequiel Garcia wrote:
> >>> Having the watchdog initially fully stopped is important to av
From: Thomas Abraham
Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
support for CPU boost mode. This patch adds support for finding available
boost frequencies from device tree and marking them as usable in boost mode.
Cc: Nishanth Menon
Cc: Lukasz Majewski
Signed-off-by
Changes since v1:
- Boost mode frequencies are specfied as a set of frequencies instead of
specifying them as OPPs. Thanks to Nishanth, Lukasz and Rob for the
feedback.
Commit 6f19efc0 ("cpufreq: Add boost frequency support in core") adds
support for CPU boost mode for CPUfreq drivers. To use
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