This reverts commit 06b29e76a74b2373e6f8b5a7938b3630b9ae98b2.
As pointed out by Grant Likely, we should also take the type and name
into account when searching the best compatible match. That means the
match with compatible, type and name should be better than the match
just with the same
In the current implementation of __of_match_node(), it will compare
each given match entry against all the node's compatible strings
with of_device_is_compatible().
To achieve multiple compatible strings per node with ordering from
specific to generic, this requires given matches to be ordered
On 17/02/14 20:48, Florian Fainelli wrote:
[snip]
- fixing up some design mistake?
- accounting for a specific board design?
Kind of both. This was invented to defy the necessity of having platform
fixup in the DT case (where there should be no board file to place it into).
I have
+static const struct resource lm3633_effect_resources[] = {
+ {
+ .name = LM3633_EFFECT_BL0_RAMPUP,
+ .flags = IORESOURCE_REG,
+ .start = LM3633_EFFECT_REGISTER(BL0_RAMPUP),
+ },
snip
+ {
+ .name = LM3633_EFFECT_PTN_HIGHBRT,
+
On Saturday 15 February 2014 01:51 AM, Mark Brown wrote:
On Thu, Feb 06, 2014 at 11:20:13AM +0530, Keerthy wrote:
This patch adds support for TPS65218 PMIC regulators.
The regulators set consists of 6 DCDCs and 1 LDO. The output
voltages are configurable and are meant to supply power to the
On Tue, Feb 18, 2014 at 10:07:04AM +1000, Ben Peddell wrote:
On 18/02/2014 8:34 AM, Josh Cartwright wrote:
On Tue, Feb 18, 2014 at 07:45:35AM +1000, klightsp...@killerwolves.net
wrote:
From: Andrew Lunn and...@lunn.ch
The following patches make use of vendor names ricoh, ssi and
On Mon, 17 Feb 2014 16:29:40 +, Ben Dooks ben.do...@codethink.co.uk wrote:
The of_mdiobus_register_phy() is not setting phy-irq this causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it or install an interrupt handler for the
PHY.
Simplify the
+Required properties:
+- compatible : Should be either marvell,ferocean-cache or
+ marvell,kirkwood-cache.
+
+Optional properties:
+- wt-override: If present then L2 is forced to Write through mode
+- reg: Address of the L2 cache control register. Mandatory for
+
On Mon, 17 Feb 2014 17:13:07 +0100, Arnd Bergmann a...@arndb.de wrote:
On Monday 17 February 2014 15:54:19 Grant Likely wrote:
On Wed, 12 Feb 2014 11:20:00 -0700, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Wed, Feb 12, 2014 at 12:45:54PM -0500, Jason Cooper wrote:
On 18/02/14 09:30, Grant Likely wrote:
On Mon, 17 Feb 2014 16:29:40 +, Ben Dooks ben.do...@codethink.co.uk wrote:
The of_mdiobus_register_phy() is not setting phy-irq this causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it or install an interrupt
HDMI codec dummy entries for Panda/ES.
Signed-off-by: Paolo Pisati paolo.pis...@canonical.com
---
Depends on 0f7f3d1 ASoC: hdmi-codec: Add devicetree binding with
documentation, eligible for a 3.14-rcX fix.
arch/arm/boot/dts/omap4-panda-common.dtsi |9 -
On 14/02/14 14:25, Marek Belisko wrote:
Signed-off-by: Marek Belisko ma...@goldelico.com
I wonder how this got missed. However, for those data elements to be useful,
you will
need to read them somewhere in the driver I think (if there is any magic
that puts this in the relevant i2c
2014-02-11 13:58 GMT+01:00 Daniel Lezcano daniel.lezc...@linaro.org:
On 02/10/2014 11:10 AM, Ivan Khoronzhuk wrote:
Add broadcast clock-event device for the Keystone arch.
The timer can be configured as a general-purpose 64-bit timer,
dual general-purpose 32-bit timers. When configured as
From: Rahul Sharma rahul.sha...@samsung.com
V4:
1) Removed duplicate MMC Soc property from Board file.
V3:
1) Addressed review comments from Tomasz figa.
V2:
1) Split up DT patch into SoC and Board patch.
This series is dependent on Sachin's patch
ARM: EXYNOS: Consolidate CPU init code
The patch adds the dts files for exynos5260.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 574
The patch adds the dts files for xyref5260 board which
is based on Exynos5260 Evt0 sample.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/exynos5260-xyref5260-evt0.dts | 103 +++
2 files
On Tuesday 18 February 2014 16:27:54 Rahul Sharma wrote:
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 7654f19..1cc52c9 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -176,6 +176,15 @@ static struct map_desc
On Fri, Feb 14, 2014 at 04:43:04PM +, Stephen Warren wrote:
On 02/14/2014 03:35 AM, Mark Rutland wrote:
On Fri, Feb 14, 2014 at 06:16:52AM +, Stephen Warren wrote:
clk-fixed-rate currently names clocks according to a node's name without
the unit address. When faced with the legal
On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar jaswinder.si...@linaro.org wrote:
On 15 February 2014 17:30, Srikanth Thokala stho...@xilinx.com wrote:
The current implementation of interleaved DMA API support multiple
frames only when the memory is contiguous by incrementing src_start/
dst_start
On Tue, Feb 18, 2014 at 10:17:12AM +0800, Jingchang Lu wrote:
Add Freescale enhanced direct memory(eDMA) controller support.
This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jingchang Lu b35...@freescale.com
Acked-by: Arnd
Hi,
here is an updated and more complete version of the imx-drm DT binding
series. These patches apply on top of Russell's second preview of the
imx-drm cleanup series on v3.14-rc2. I have added device tree bindings
between IPU and the encoders as documented in
This patch connects IPU and display encoder (HDMI, LVDS, MIPI)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display
This patch updates the device tree binding documentation for i.MX IPU/display
nodes using the OF graph bindings documented in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../bindings/staging/imx-drm/fsl-imx-drm.txt |
From: Lucas Stach l.st...@pengutronix.de
Since imx_drm_encoder_parse_of is called from the encoder bind callbacks,
it is too late to request probe deferral. Rather the core should make sure
that the crtcs are bound before the encoders, after all needed components
are probed.
This fixes probe
From: Philipp Zabel philipp.za...@gmail.com
The existing v4l2-of parser functions for the video interface bindings
described in Documentation/device-tree/bindings/media/video-interfaces.txt
are useful for DRM drivers, too. They will be moved to drivers/media
so they can be used by drm drivers,
This patch connects IPU and and parallel display device tree
nodes using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Since the imx-drm
This patch adds device tree binding documentation for the HDMI transmitter
on i.MX6.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
.../devicetree/bindings/staging/imx-drm/hdmi.txt | 53 ++
1 file changed, 53 insertions(+)
create mode 100644
This patch adds support to find the involved components connected to the
IPU display interface ports using the OF graph bindings documented in
Documentation/devicetree/bindings/media/video-interfaces.txt
Each display interface needs to have an associated port node in the
device tree. We can
This patch connects IPU and display encoder (VGA, LVDS)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
On Tue, Feb 18, 2014 at 08:16:46AM +, Ben Dooks wrote:
On 17/02/14 20:48, Florian Fainelli wrote:
[snip]
- fixing up some design mistake?
- accounting for a specific board design?
Kind of both. This was invented to defy the necessity of having
platform
fixup in the DT
Hi,
On Thursday 13 February 2014 06:02 PM, Tomi Valkeinen wrote:
Add device tree bindings for OMAP Display Subsystem for the following
SoCs: OMAP2, OMAP3, OMAP4.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
snip
+A shortened example of the board description for OMAP4 Panda
On Tuesday 18 February 2014 17:11:43 Sachin Kamat wrote:
On 18 February 2014 16:33, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 18 February 2014 16:27:54 Rahul Sharma wrote:
+static struct map_desc exynos5260_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned
Hi,
On Thursday 13 February 2014 06:02 PM, Tomi Valkeinen wrote:
Hi,
Here is DT binding documentation for OMAP Display Subsystem. I've sent these
earlier as part of the whole DSS DT series, but I'm now sending them separately
to get comments for them.
These patches are essentially the same as
On Thu, Feb 13, 2014 at 05:19:11AM +, Mohit KUMAR DCG wrote:
Hello Mark,
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Wednesday, February 12, 2014 11:50 PM
To: Mohit KUMAR DCG
Cc: a...@arndb.de; Pratyush ANAND; Viresh Kumar; Kishon Vijay
Some PWM outputs are wired such that the LED they're controlling is
connected to supply rather than ground. Therefore, the duty cycle
needs to be inverted to make the LED behave as it should do.
We also provide a way to specify the default brightness when a
trigger is not specified.
From: Ivan T. Ivanov iiva...@mm-sol.com
Document device tree binding information as required by
the Qualcomm USB controller.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-hsusb.txt | 17 +
1 file changed, 17 insertions(+)
diff
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c | 23 ++-
1 file changed, 22 insertions(+), 1
On 25/11/13 19:47, Jean-Francois Moine wrote:
At probe time, a clock device may not be ready when some other device
wants to use it.
This patch lets the functions clk_get/devm_clk_get return a probe defer
when the clock is defined in the DT but not yet available.
Signed-off-by:
Hi all!
This is yet another update of the second attempt to add basic support
for dynamic allocation of memory reserved regions defined in device
tree.
This time I've tried to address all the issues reported by Grant Likely.
The side-effect of it is a complete rewrite of memory reservation code,
This patch adds device tree support for contiguous and reserved memory
regions defined in device tree.
Large memory blocks can be reliably reserved only during early boot.
This must happen before the whole memory management subsystem is
initialized, because we need to ensure that the given
Hi Grant,
Am Montag, den 17.02.2014, 18:14 + schrieb Grant Likely:
On Tue, 11 Feb 2014 07:56:33 -0600, Rob Herring robherri...@gmail.com wrote:
On Tue, Feb 11, 2014 at 5:45 AM, Philipp Zabel p.za...@pengutronix.de
wrote:
From: Philipp Zabel philipp.za...@gmail.com
This patch
From: Josh Cartwright jo...@codeaurora.org
Add support for handling 'shared-dma-pool' reserved-memory nodes using
Contiguous Memory Allocator driver.
Signed-off-by: Josh Cartwright jo...@codeaurora.org
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
drivers/of/Kconfig
Enable reserved memory initialization from device tree.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/Kconfig |1 +
arch/arm/mm/init.c |3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e25419817791..d0262bea8020
On Tue, Feb 18, 2014 at 10:09 +0800, Shawn Guo wrote:
On Mon, Feb 17, 2014 at 10:24:39PM +0100, Gerhard Sittig wrote:
On Mon, Feb 10, 2014 at 19:50 +0800, Shawn Guo wrote:
Update fsl-fec to explicitly list the supported compatible strings
and add missing 'clocks' and 'clock-names'
This patch adds support for USB_OTG on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh ashutos...@phytec.in
---
arch/arm/boot/dts/imx6q-phytec-pbab01.dts |4
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 17 +
2 files changed, 21 insertions(+)
diff
This patch adds support for GPMI-NAND on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh ashutos...@phytec.in
---
arch/arm/boot/dts/imx6q-phytec-pbab01.dts |4
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi |7 +++
2 files changed, 11 insertions(+)
diff --git
This patch adds support for USB_HOST on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh ashutos...@phytec.in
---
arch/arm/boot/dts/imx6q-phytec-pbab01.dts |4
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 14 ++
2 files changed, 18 insertions(+)
diff --git
This patch adds support for SATA on Phytec phyFLEX-i.MX6 Quad module.
Signed-off-by: Ashutosh singh ashutos...@phytec.in
---
arch/arm/boot/dts/imx6q-phytec-pbab01.dts |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
On Tue, February 18, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
Like the rockchip, Altera's SOCFPGA platform specific implementation of the
dw_mmc driver requires using the HOLD register for SD commands. This patch
renames dw_mci_rockchip_prepare_command to
On Tue, February 18, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
It turns now that the only really platform specific code that is needed for
SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
Since the Rockchip already has this functionality,
After showcasing my dtc change as RFC before, this series shows essentially
where I want to go with the whole change - adding support for our ereaders
without duplicating the generic pinconfig nodes :-) . And also provides with
the dt change a user for the dtc flag addition.
That being said, the
From: Heiko Stuebner heiko.stueb...@bqreaders.com
Using the delete-unreferenced flag, the pingroups can be kept globally but won't
be unecessarily included in dts files not using them.
Signed-off-by: Heiko Stuebner heiko.stueb...@bqreaders.com
---
arch/arm/boot/dts/imx6sl-evk.dts | 181
From: Heiko Stuebner heiko.stueb...@bqreaders.com
On i.MX, which carries a lot of pin-groups of which most are unused on
individual boards, they noticed that this plethora of nodes also results
in the runtime-lookup-performance also degrading [0].
A i.MX-specific solution defining the pingroups
From: Heiko Stuebner heiko.stueb...@bqreaders.com
i.MX6SL based ebook-reader released in 2013.
Signed-off-by: Heiko Stuebner heiko.stueb...@bqreaders.com
---
arch/arm/boot/dts/imx6sl-bq-cervantes.dts | 133 ++
1 file changed, 133 insertions(+)
create mode 100644
On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote:
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
Again, your SoB is missing, and that can be squashed with the previous
patch.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel
Hi,
On Mon, Feb 17, 2014 at 11:02:21AM +0100, David Lanzendörfer wrote:
From: Emilio López emi...@elopez.com.ar
Signed-off-by: Emilio López emi...@elopez.com.ar
You're missing your Signed-off-by here too. Remember, for every patch
you send, your Signed-off-by must be there, regardless
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |
On Mon, Feb 17, 2014 at 01:05:44PM -0500, Jason Cooper wrote:
Interested individuals can look through the irc archives for
#devicetree.
oops, My mistake. They are supposed to be at irclogs.linaro.org, but it
hasn't been set up yet. You'll just have to ask nicely for someone to
go through
On Friday 14 February 2014 11:15 AM, Nishanth Menon wrote:
When device is booted using devicetree, platforms impacted by Erratum
2.1.1.128 is not detected easily in the mmc driver. This erratum
indicates that the module cannot do multi-block transfers. Platforms
such as LDP which use OMAP3 ES
Greg,
On Wednesday 05 February 2014 02:46 PM, Ivan Khoronzhuk wrote:
These patches introduce Async External Memory Interface (EMIF16/AEMIF)
controller driver for Davinci/Keystone archs.
For more informations see documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
On Tue, Feb 18, 2014 at 02:44:30PM +0100, Gerhard Sittig wrote:
@@ -1,9 +1,26 @@
* Freescale Fast Ethernet Controller (FEC)
Required properties:
-- compatible : Should be fsl,soc-fec
+- compatible : Should contain one of the following:
+ fsl,imx25-fec
El 05/02/14 10:05, Maxime Ripard escribió:
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Taken via sunxi-clk-for-mike.
Thanks!
Emilio
--
To unsubscribe from this list: send the line
Hello.
On 18-02-2014 16:16, Ben Dooks wrote:
The of_mdiobus_register_phy() is not setting phy-irq thus causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it. Not only do some drivers report no IRQ
they do not install an interrupt handler for the PHY.
On Thu, 30 Jan 2014 14:54:36 +0100
Linus Walleij linus.wall...@linaro.org wrote:
On Mon, Jan 13, 2014 at 5:56 PM, Alexander Shiyan shc_w...@mail.ru wrote:
SYSCON driver was designed for using memory areas (registers)
that are used in several subsystems. There are systems (CPUs)
which use
On Tuesday 18 February 2014, Mark Rutland wrote:
- These are Spear SoC specific miscellaneous registers. Here these are used
for
to configure sata/pcie aux clock.
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - 1st cell:
Cc: devicetree@vger.kernel.org
Acked-by Angus Clark angus.cl...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Documentation/devicetree/bindings/mtd/st-fsm.txt | 26
1 file changed, 26 insertions(+)
create mode 100644
Hi,
On 02/18/2014 03:22 PM, Maxime Ripard wrote:
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
On 02/14/2014 03:33 PM, Lee Jones wrote:
Use a meaningful name for the reference clocks so that it indicates the
function.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mfd/omap-usb-host.c | 6 +++---
1
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework and needs a phandle to the PU regulator to turn off power when
the domain is disabled.
Signed-off-by: Philipp Zabel
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To
This avoids the ... latency exceeded, new value ... warnings
emitted by the power domain framework code whenever the PU domain
is enabled or disabled.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/gpc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
Drivers still handle clocks themselves, we only enable pm clocks of the
GPU and VPU devices in the PU power domain temporarily during powerup
so that the reset machinery can work.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
arch/arm/mach-imx/gpc.c | 74
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel
The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v3:
- Updated documentation to use fsl,power-domain property name
and pu-power-domain as node name.
- Removed
On 22/12/13 22:27, Sylwester Nawrocki wrote:
This patch adds DT binding documentation for the Samsung S5K6A3(YX)
raw image sensor.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch adds missing documentation [1]
On Mon, Feb 17, 2014 at 11:03:02AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 32
1 file changed, 32 insertions(+)
create mode 100644
On Thu, Jan 09, 2014 at 11:54:13AM +0100, Andreas Larsson wrote:
Rename struct platform_device pointers from ofdev to pdev for clarity.
Suggested by Mark Rutland.
Signed-off-by: Andreas Larsson andr...@gaisler.com
---
drivers/usb/gadget/gr_udc.c | 18 +-
1 file changed,
Hello.
On 02/18/2014 02:54 PM, Mark Rutland wrote:
[snip]
- fixing up some design mistake?
- accounting for a specific board design?
Kind of both. This was invented to defy the necessity of having platform
fixup in the DT case (where there should be no board file to place it into).
Use a meaningful name for the reference clocks so that it indicates the
function.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mfd/omap-usb-host.c | 6 +++---
1 file changed, 3 insertions(+), 3
On Tue, Feb 18, 2014 at 03:21:19PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Document device tree binding information as required by
the Qualcomm USB controller.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-hsusb.txt
On Tue, 18 Feb 2014 12:16:58 +, Ben Dooks ben.do...@codethink.co.uk wrote:
The of_mdiobus_register_phy() is not setting phy-irq thus causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it. Not only do some drivers report no IRQ
they do not install
On Tue, 18 Feb 2014 08:06:24 +0100, Sascha Hauer s.ha...@pengutronix.de wrote:
Hi Grant,
On Mon, Feb 17, 2014 at 06:14:51PM +, Grant Likely wrote:
On Tue, 11 Feb 2014 07:56:33 -0600, Rob Herring robherri...@gmail.com
wrote:
On Tue, Feb 11, 2014 at 5:45 AM, Philipp Zabel
On 18 February 2014 16:58, Srikanth Thokala stho...@xilinx.com wrote:
On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar jaswinder.si...@linaro.org
wrote:
On 15 February 2014 17:30, Srikanth Thokala stho...@xilinx.com wrote:
The current implementation of interleaved DMA API support multiple
frames
Hello.
On 02/18/2014 04:21 PM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c |
On Tue, 18 Feb 2014 14:37:58 +0100, Marek Szyprowski m.szyprow...@samsung.com
wrote:
From: Josh Cartwright jo...@codeaurora.org
Add support for handling 'shared-dma-pool' reserved-memory nodes using
dma exclusive driver (dma_alloc_coherent()).
Signed-off-by: Josh Cartwright
On Tue, 18 Feb 2014 09:40:39 +, Ben Dooks ben.do...@codethink.co.uk wrote:
On 18/02/14 09:30, Grant Likely wrote:
On Mon, 17 Feb 2014 16:29:40 +, Ben Dooks ben.do...@codethink.co.uk
wrote:
The of_mdiobus_register_phy() is not setting phy-irq this causing
some drivers to
On Tue, 18 Feb 2014 15:57:29 +0800, Kevin Hao haoke...@gmail.com wrote:
This reverts commit 06b29e76a74b2373e6f8b5a7938b3630b9ae98b2.
As pointed out by Grant Likely, we should also take the type and name
into account when searching the best compatible match. That means the
match with
Hello.
On 02/18/2014 08:02 PM, Grant Likely wrote:
On Mon, 17 Feb 2014 16:29:40 +, Ben Dooks ben.do...@codethink.co.uk wrote:
The of_mdiobus_register_phy() is not setting phy-irq this causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it or
On Tue, Feb 18, 2014 at 05:00:03PM +, Sergei Shtylyov wrote:
Hello.
On 02/18/2014 02:54 PM, Mark Rutland wrote:
[snip]
- fixing up some design mistake?
- accounting for a specific board design?
Kind of both. This was invented to defy the necessity of having
platform
Hi,
On Tue, 2014-02-18 at 20:53 +0300, Sergei Shtylyov wrote:
Hello.
On 02/18/2014 04:21 PM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan
On Tue, 2014-02-18 at 08:08 -0600, Josh Cartwright wrote:
Hey Ivan-
Nit below.
On Tue, Feb 18, 2014 at 03:21:20PM +0200, Ivan T. Ivanov wrote:
+static struct of_device_id msm_ci_dt_match[] = {
const?
Thanks, will do.
Regards,
Ivan
+ { .compatible = qcom,ci-hdrc, },
+
Hi,
On Tue, 2014-02-18 at 10:13 -0600, Josh Cartwright wrote:
On Tue, Feb 18, 2014 at 03:21:19PM +0200, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Document device tree binding information as required by
the Qualcomm USB controller.
Signed-off-by: Ivan T.
On 02/18/2014 08:14 PM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Allows controller to be specified via device tree.
Pass PHY phandle specified in DT to core driver.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
drivers/usb/chipidea/ci_hdrc_msm.c | 23
On 02/18/2014 04:23 AM, Mark Rutland wrote:
On Fri, Feb 14, 2014 at 04:43:04PM +, Stephen Warren wrote:
On 02/14/2014 03:35 AM, Mark Rutland wrote:
On Fri, Feb 14, 2014 at 06:16:52AM +, Stephen Warren wrote:
clk-fixed-rate currently names clocks according to a node's name without
the
On Tue, Sep 03, 2013 at 05:49:29PM +0100, Ian Molton wrote:
Add a driver for the EMMA mobile I2C block.
The driver supports low and high-speed interrupt driven PIO transfers.
Signed-off-by: Ian Molton ian.mol...@codethink.co.uk
--- a/drivers/i2c/busses/Kconfig
+++
On Tue, Feb 18, 2014 at 10:20 PM, Jassi Brar jaswinder.si...@linaro.org wrote:
On 18 February 2014 16:58, Srikanth Thokala stho...@xilinx.com wrote:
On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar jaswinder.si...@linaro.org
wrote:
On 15 February 2014 17:30, Srikanth Thokala stho...@xilinx.com
On 02/17/2014 02:26 AM, Lee Jones wrote:
From: Stephen Warren swar...@nvidia.com
Some boards or SoCs have an inverter between the PMIC IRQ output pin and
the IRQ controller input signal.
The IRQ specifier in DT is meant to represent the IRQ flags at the input
to the IRQ controller.
The
On Mon, Feb 17, 2014 at 10:07:50PM +0100, Geert Uytterhoeven wrote:
On Mon, Feb 17, 2014 at 7:23 PM, Jason Cooper ja...@lakedaemon.net wrote:
Could we use a faster hash function that scans the entire device tree and
then just feed the output of that into add_device_randomness? We probably
From: Stephen Warren swar...@nvidia.com
Some boards or SoCs have an inverter between the PMIC IRQ output pin and
the IRQ controller input signal.
The IRQ specifier in DT is meant to represent the IRQ flags at the input
to the IRQ controller.
The Palmas HW's IRQ output has
On Tuesday 18 February 2014 16:34:41 Philipp Zabel wrote:
+
+Example of a device that is part of a power domain:
+
+ vpu: vpu@0204 {
+ reg = 0x0204 0x3c000;
+ /* ... */
+ fsl,power-domain = pd_pu;
+ /* ... */
+ };
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