2013/7/5 Bo Shen voice.s...@atmel.com:
Yes, I aware this issue.
Actually the system not hang, the resource all are occupied by the
interrupt. This because, we enable the interrupt, when once interrupt occur,
I try many methods to clear it, however we can not clear it. So, it
generates the
Hi Arnd,
On Fri, Jul 5, 2013 at 6:34 AM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 04 July 2013, Mark Brown wrote:
On Thu, Jul 04, 2013 at 06:56:24PM +0200, Daniel Mack wrote:
Unless I missed some recent discussion, this case is not easy to handle.
Yes, I know that these kind of
The clocks should be numbered sequentially as they are represented as
enum values in the clock driver.
Typo introduced by commit 17d4caccef (clk: exynos5250: register
display block gate clocks to common clock framework)
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
On Tue, Jul 2, 2013 at 9:25 PM, Russell King r...@arm.linux.org.uk wrote:
On Tue, Jul 02, 2013 at 09:57:32PM +0200, Sebastian Hesselbarth wrote:
I am against a super node which contains lcd and dcon/ire nodes. You can
enable those devices on a per board basis. We add them to dove.dtsi but
On Wed, Jul 3, 2013 at 10:02 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Wed, Jul 03, 2013 at 05:57:18PM +0900, Inki Dae wrote:
video {
/* Single video card w/ multiple lcd controllers */
card0 {
compatible = marvell,armada-510-display;
reg = 0
On Fri, Jul 05, 2013 at 09:37:34AM +0100, Grant Likely wrote:
Alternatively, you can have the same effect with a property or set of
properties in the controller node that contains phandles to the
required devices. That would provide the driver with the same
information about which devices must
Exynos5250 G2D IP requires only the gate clock. Update the
binding documentation accordingly.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Inki Dae inki@samsung.com
---
.../devicetree/bindings/gpu/samsung-g2d.txt|4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Adds gate clock for G2D IP for Exynos5250 SoC.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Mike Turquette mturque...@linaro.org
---
This patch depends on the following patch:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581
---
Adds G2D node to exynos5250 DT file.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5250.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index ef57277..6f356ce 100644
---
On Fri, Jul 5, 2013 at 9:50 AM, Russell King r...@arm.linux.org.uk wrote:
On Fri, Jul 05, 2013 at 09:37:34AM +0100, Grant Likely wrote:
Alternatively, you can have the same effect with a property or set of
properties in the controller node that contains phandles to the
required devices. That
If we set the uart compatible in the dts file like this:
--
compatible = fsl,imx6q-uart, fsl,imx21-uart;
--
and we set the uart compatible in the uart driver like this:
On 07/05/13 10:43, Grant Likely wrote:
On Wed, Jul 3, 2013 at 10:02 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Wed, Jul 03, 2013 at 05:57:18PM +0900, Inki Dae wrote:
video {
/* Single video card w/ multiple lcd controllers */
card0 {
compatible =
On Fri, Jul 5, 2013 at 10:34 AM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
So for the discussion, I can see that there have been some voting for
super-node, some for node-to-node linking. Although I initially proposed
super-nodes, I can also happily live with node-to-node
On Thu, Jul 04, 2013 at 12:58:29PM +0200, Sebastian Hesselbarth wrote:
On 07/04/13 12:09, Sascha Hauer wrote:
On Thu, Jul 04, 2013 at 11:44:41AM +0200, Sebastian Hesselbarth wrote:
On 07/04/13 11:30, Sascha Hauer wrote:
On Thu, Jul 04, 2013 at 10:11:31AM +0100, Russell King wrote:
On Thu, Jul
On Sun, Jun 30, 2013 at 10:48:46AM +0100, Lorenzo Pieralisi wrote:
On Sat, Jun 29, 2013 at 08:38:19PM +0100, Russell King - ARM Linux wrote:
On Fri, Jun 28, 2013 at 01:05:42PM -0700, Olof Johansson wrote:
On Fri, Jun 28, 2013 at 1:03 PM, Maxime Ripard
maxime.rip...@free-electrons.com
On Fri, Jul 5, 2013 at 11:07 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
Again the difference between supernodes and graphs is that the supernode
approach does not contain information about what components are needed
to do something useful with the device. You simply have to wait until
On 07/05/13 11:51, Grant Likely wrote:
On Fri, Jul 5, 2013 at 10:34 AM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
So for the discussion, I can see that there have been some voting for
super-node, some for node-to-node linking. Although I initially proposed
super-nodes, I can
Hi Jean-Christophe,
On Tue, May 28, 2013 at 8:09 AM, Jean-Christophe PLAGNIOL-VILLARD
plagn...@jcrosoft.com wrote:
On 12:35 Sun 26 May , Markus Pargmann wrote:
Add devicetree support for imx framebuffer driver. It uses the generic
display bindings and helper functions.
Signed-off-by:
Signed-off-by: Cho KyongHo pullip@samsung.com
---
.../bindings/iommu/samsung,exynos4210-sysmmu.txt | 103 +++
arch/arm/boot/dts/exynos4.dtsi | 122
arch/arm/boot/dts/exynos4210.dtsi | 25 ++
arch/arm/boot/dts/exynos4x12.dtsi
This commit adds device tree support for System MMU.
This also include the following changes and enhancements:
* use managed device helper functions.
Simplyfies System MMU device driver.
* use only a single clock descriptor.
System MMU device descriptor is seperate if it is imposible to make
a
This series enables the use of the additional cores on Rockchip
Cortex-A9 SoCs.
To achieve this, add the scu, the needed sram and power-management-unit.
Tested on a rk3066a (dual core) by me and on a rk3188 (quad core)
by Ulrich Prinz.
(Note: rk3188 support in general needs additional upcoming
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off again if it exists.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
drivers/misc/sram.c |3 ++-
1
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary portions of the
sram from being part of the pool.
Suggested-by: Rob Herring
This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
arch/arm/boot/dts/rk3066a.dtsi |5 +
arch/arm/mach-rockchip/Kconfig |1 +
2 files
The Rockchip SoCs need a special part of their sram for bringup
of additional cores. Therefore also add a reserved section when adding the
mmio-sram node to keep the sram driver from using this space.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz
The pmu is needed to bring up the cores during smp operations.
Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
Documentation/devicetree/bindings/arm/rockchip/pmu.txt | 16
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done
On Fri, Jul 5, 2013 at 9:41 AM, Heiko Stübner he...@sntech.de wrote:
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary portions of
Fixup of commit 7874d595b78e431f0f661d2fe47625649308a52e
ARM: dts: Add device tree support for phycard pca100.
Remove wrong I2C RTC node.
Signed-off-by: Markus Pargmann m...@pengutronix.de
---
Thanks, Alexander, you are right. I2C2 has no RTC.
Regards,
Markus
On 16:41-20130704, Mark Brown wrote:
On Fri, Jun 21, 2013 at 04:25:42PM -0500, Nishanth Menon wrote:
+static const struct omap_pmic_info omap_twl4030_vdd1 = {
+ .slave_addr = 0x12,
+ .voltage_reg_addr = 0x00,
+ .cmd_reg_addr = 0x00,
+ .i2c_timeout_us = 200,
+ .slew_rate_uV
On Sun, Jun 23, 2013 at 12:49:17PM -0500, Timur Tabi wrote:
Markus Pargmann wrote:
This patch removes the NO_DT flag. The pdev pointer may have a proper
of_node with the dmas property, so we can use it to request DMA
channels.
Signed-off-by: Markus Pargmannm...@pengutronix.de
Extcon for palma driver does not need vbus supply and hence
removing this from devicetree document/bindings.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
---
.../devicetree/bindings/extcon/extcon-palmas.txt |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git
The driver name is extcon/extcon-palmas.c and hence renaming the
device tree binding document to extcon-palmas.txt.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
---
.../extcon/{extcon-twl.txt = extcon-palmas.txt} |0
1 files changed, 0 insertions(+), 0 deletions(-)
rename
On Fri, Jul 05, 2013 at 08:55:07AM -0500, Nishanth Menon wrote:
Please write in paragraphs, an enormous wall of unbroken text isn't
helpful for legibility.
On 16:41-20130704, Mark Brown wrote:
So, this still has the thing where all the data about the PMIC is
replicated (but now in this
Am Freitag, 5. Juli 2013, 14:55:40 schrieb Fabio Estevam:
On Fri, Jul 5, 2013 at 9:41 AM, Heiko Stübner he...@sntech.de wrote:
Some SoCs need parts of their sram for special purposes. So while being
part of the periphal, it should not be part of the genpool controlling
the sram.
Am Freitag, den 05.07.2013, 14:41 +0200 schrieb Heiko Stübner:
Some SoCs need parts of their sram for special purposes. So while being part
of the periphal, it should not be part of the genpool controlling the sram.
Threfore add an option mmio-sram-reserved to keep arbitary portions of the
Am Freitag, den 05.07.2013, 14:40 +0200 schrieb Heiko Stübner:
The pool is created thru devm_gen_pool_create, so the call to
gen_pool_destroy is not necessary.
Instead the sram-clock must be turned off again if it exists.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz
On 07/05/2013 09:08 AM, Mark Brown wrote:
On Fri, Jul 05, 2013 at 08:55:07AM -0500, Nishanth Menon wrote:
Please write in paragraphs, an enormous wall of unbroken text isn't
helpful for legibility.
Apologies on the same. Will try to do better.
On 16:41-20130704, Mark Brown wrote:
So,
On Fri, Jul 5, 2013 at 9:43 AM, Heiko Stübner he...@sntech.de wrote:
--- /dev/null
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner he...@sntech.de
+ *
+ * This program is free software; you can redistribute it
2013/7/2 Bo Shen voice.s...@atmel.com:
Hi Richard,
Will move this patch before 5, 6, 7?
yes, you're right.
On 7/1/2013 16:39, Richard Genoud wrote:
From: Nicolas Ferre nicolas.fe...@atmel.com
Description of the Asoc machine driver for an at91sam9x5 based board
with a wm8731 audio
2013/7/2 Bo Shen voice.s...@atmel.com:
Hi Richard,
On 7/1/2013 16:39, Richard Genoud wrote:
With device tree, pdev-id is always -1, so we introduce a local
counter.
Signed-off-by: Richard Genoud richard.gen...@gmail.com
---
drivers/misc/atmel-ssc.c |7 +++
1 file changed, 7
2013/7/2 Bo Shen voice.s...@atmel.com:
Hi Richard,
On 7/1/2013 16:39, Richard Genoud wrote:
Signed-off-by: Richard Genoud richard.gen...@gmail.com
---
arch/arm/mach-at91/at91sam9x5.c |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-at91/at91sam9x5.c
On 07/05/2013 11:52 AM, Mark Brown wrote:
On Fri, Jul 05, 2013 at 09:50:34AM -0500, Nishanth Menon wrote:
On 07/05/2013 09:08 AM, Mark Brown wrote:
option 1) we just bypass get_voltage/set_voltage to point through to
this function. result will be something similar to what we got here[1]
I
On Fri, Jul 05, 2013 at 12:33:10PM -0500, Nishanth Menon wrote:
Taking an example of twl-regulator and omap_pmic, are you suggesting
omap_pmic to be a user twl-regulator using
include/linux/regulator/consumer.h? or are you suggesting that
omap_pmic should not be a regulator at all?
No, I'm
2013/7/5 Mark Brown broo...@kernel.org:
On Fri, Jul 05, 2013 at 05:15:05PM +0200, Richard Genoud wrote:
2013/7/2 Bo Shen voice.s...@atmel.com:
From: Nicolas Ferre nicolas.fe...@atmel.com
Description of the Asoc machine driver for an at91sam9x5 based board
with a wm8731 audio DAC. Wm8731
On 07/04/2013 10:56 AM, Daniel Mack wrote:
...
The built-in support for attaching a DTB to the zImage does not suffice
here, because we have one image for all models, and also, we couldn't do
a 'per-board-revision' selection that way either.
...
As a solution, I'm thinking of a small framework
On 07/05/2013 03:49 AM, Christian Ruppert wrote:
On Wed, Jun 26, 2013 at 11:40:42AM -0600, Stephen Warren wrote:
On 06/26/2013 05:50 AM, Christian Ruppert wrote:
On Wed, Jun 19, 2013 at 04:35:14PM -0600, Stephen Warren wrote:
On 06/18/2013 03:29 AM, Christian Ruppert wrote:
[...]
+Example
On 7/3/2013 7:15 AM, Ming Lei wrote:
On Sat, Apr 27, 2013 at 5:32 AM, Rob Herring robherri...@gmail.com wrote:
On 04/26/2013 03:31 PM, Laura Abbott wrote:
Currently, of_platform_device_create_pdata always sets the
coherent DMA mask to 32 bits. On ARM systems without CONFIG_ZONE_DMA,
See the previous version of this patchset for further context:
http://www.mail-archive.com/devicetree-discuss@lists.ozlabs.org/msg35753.html
This new proposal is an attempt to address some issues raised about the PCIe
'fake' windows mapping present in the previous version.
Instead of defining a
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
We add an API to create MBus address decoding windows from the target
ID and attribute. This function will be used later and deprecate the
current name based scheme.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Now that mbus device tree binding has been introduced, remove the address
decoding window management from this driver.
A suitable 'ranges' entry should be added to the devbus-compatible node in
the device tree, as described by the mbus binding documentation.
Acked-by: Greg Kroah-Hartman
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.
This will allow to deprecate the name based API, once every
user is removed.
Signed-off-by: Thomas Petazzoni
This patch adds the most fundamental device-tree initialization.
We only introduce what's required to be able to probe the mvebu-mbus
driver from the DT. Follow-up patches will extend the device tree binding,
allowing to describe static address decoding windows.
Signed-off-by: Thomas Petazzoni
We introduce a common initialization function mvebu_mbus_common_init()
that will be used by both legacy and device-tree initialization code.
This patch is an intermediate step, which will allow to introduce the
DT binding for this driver in a less intrusive way.
Signed-off-by: Thomas Petazzoni
This patch adds static window allocation to the device tree binding.
Each first-child of the mbus-compatible node, with a suitable 'ranges'
property, declaring an address translation, will trigger an address
decoding window allocation.
Signed-off-by: Ezequiel Garcia
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Now that every user of the deprecated name-based API has been
converted to using the ID-based API, let's remove the former one.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/bus/mvebu-mbus.c | 38
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
The new device tree layout encodes the window's target ID and attribute
in the PCIe controller node's ranges property. This allows to parse
such entries to obtain such information and use the recently introduced
MBus API to create the
Now that the mbus device tree binding has been introduced, we can
switch over to it.
Also, and since the initialization of the mbus driver is quite
fundamental for the system to work properly, this patch adds a BUG()
in case mbus fails to initialize.
Signed-off-by: Ezequiel Garcia
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
These structures were only different in the mapping tables.
Now that those tables have been removed, it doesn't make any sense
to keep different structures.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
This tables were used together with the name-based MBus window
creation API. Since that's has been removed, we can also remove
the tables.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/bus/mvebu-mbus.c
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
After replacing the MBus name-based by the new ID-based API
let's fix the general description of the driver at the beginning
of the file.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/bus/mvebu-mbus.c |
The address decoding window to access the BootROM should not be
allocated programatically, but instead declared in the device tree.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/mach-mvebu/platsmp.c | 25 -
1 file changed, 24
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts | 2 +-
arch/arm/boot/dts/armada-370-mirabox.dts | 2 +-
arch/arm/boot/dts/armada-370-rd.dts | 2 +-
arch/arm/boot/dts/armada-370.dtsi| 2 +-
Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit
In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
---
arch/arm/boot/dts/armada-370-db.dts
On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
ranges =
0x8200 0 0x4 MBUS_ID(0xf0, 0x01)
0x4 0 0x2000 /* Port 0.0 registers */
0x8200 0 0x42000 MBUS_ID(0xf0, 0x01)
On Wed, Jul 03, 2013 at 10:15:50PM +0800, Ming Lei wrote:
Without the patch, LPAE enabled board may not boot at all, but looks
it still isn't in -next tree.
But I am wondering if it is a correct approach, because enabling LPAE
doesn't mean the I/O devices can support DMA to/from 64bit
Dear Jason Gunthorpe,
Thanks for your quick feedback!
On Fri, 5 Jul 2013 16:08:20 -0600, Jason Gunthorpe wrote:
On Fri, Jul 05, 2013 at 06:39:11PM -0300, Ezequiel Garcia wrote:
ranges =
0x8200 0 0x4 MBUS_ID(0xf0, 0x01)
0x4 0
On Friday 05 July 2013, Ezequiel Garcia wrote:
See the previous version of this patchset for further context:
http://www.mail-archive.com/devicetree-discuss@lists.ozlabs.org/msg35753.html
This new proposal is an attempt to address some issues raised about the PCIe
'fake' windows mapping
There exist variants of the timer IP with some modified properties.
Therefore add infrastructure to handle hardware-quirks in the driver.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/x86/kernel/apb_timer.c |4 ++--
drivers/clocksource/dw_apb_timer.c|7 +--
The Rockchip rk3188 SoCs use a variant of the timer with some slight
modifications. This series implements them as quirks for the dw_apb_timer.
Tested on a rk3188 for the quirk handling and on a rk3066a to check that
nothing broke.
Heiko Stuebner (5):
clocksource: dw_apb_timer: infrastructure
There exists variants of the apb-timer that use slightly different
register positions. To accomodate this, add elements to the timer struct
to hold the actual register offsets.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
drivers/clocksource/dw_apb_timer.c | 83
This adds a quirk for IP variants containing two load_count and value
registers that are used to provide 64bit accuracy on 32bit systems.
The added accuracy is currently not used, the driver is only adapted to
handle the different register layout and make it work on affected devices.
Some timer variants have different mechanisms to clear a pending timer
interrupt. Therefore don't hardcode the reading of the eoi register to
clear them, but instead use the already existing eoi callback for this.
Signed-off-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
On Saturday 06 July 2013, Jason Gunthorpe wrote:
This is a good try, but this coding doesn't work...
Recall the long discussion that came up during the original
development of this binding. The OF spec says this:
In particular, the phys.hi fields of the child address spaces in the
From: Ulrich Prinz ulrich.pr...@googlemail.com
Some variants of SOCs using dw_apb_timer have inverted logic for the
bit that sets one-shot / periodic mode or free running timer. This
commit adds the new APBTMR_QUIRK_INVERSE_PERIODIC.
Signed-off-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
The rk3188 uses a variant of the timer containing two registers for load_count
and current_values.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
.../bindings/arm/rockchip/rk3188-timer.txt | 20
drivers/clocksource/dw_apb_timer_of.c |6 ++
2
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:54:35 schrieb Heiko Stübner:
Some timer variants use an inverted setting to mask the timer interrupt.
Therefore add a quirk to handle these variants.
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:54:07 schrieb Heiko Stübner:
Some variants of the dw_apb_timer don't have an eoi register but instead
expect a one to be written to the int_status register at eoi
this patch should have had a
From: Ulrich Prinz ulrich.pr...@googlemail.com
sorry for the mistake
Am Samstag, 6. Juli 2013, 00:53:36 schrieb Heiko Stübner:
Some timer variants have different mechanisms to clear a pending timer
interrupt. Therefore don't hardcode the reading of the eoi
Hi Jingoo,
On Tuesday 02 of July 2013 17:42:49 Jingoo Han wrote:
Use the generic PHY API instead of the platform callback to control
the DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
---
.../devicetree/bindings/video/exynos_dp.txt| 23
+---
Hi Jingoo,
On Tuesday 02 of July 2013 17:41:52 Jingoo Han wrote:
Exynos Display Port can be used only for Exynos SoCs. In addition,
non-DT for EXYNOS SoCs is be supported from v3.11; thus, there is
no need to support non-DT for Exynos Display Port.
The 'include/video/exynos_dp.h' file has
On Tuesday 02 of July 2013 17:40:31 Jingoo Han wrote:
Add a PHY provider driver for the Samsung Exynos SoC DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
---
On Tuesday 02 of July 2013 17:39:11 Jingoo Han wrote:
Add PHY provider node for the DP PHY.
Signed-off-by: Jingoo Han jg1@samsung.com
Acked-by: Felipe Balbi ba...@ti.com
---
arch/arm/boot/dts/exynos5250.dtsi | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
Hi Sylwester, Jacek,
On Monday 01 of July 2013 17:22:29 Sylwester Nawrocki wrote:
From: Jacek Anaszewski j.anaszew...@samsung.com
This patch adds AK8975 magnetometer node and corresponding
i2c-gpio bus node for TRATS2 board.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Hi Sylwester,
On Monday 01 of July 2013 17:22:30 Sylwester Nawrocki wrote:
This patch enables the front camera using the internal
camera ISP (FIMC-IS).
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
Hi Sylwester, Andrzej,
On Monday 01 of July 2013 17:22:34 Sylwester Nawrocki wrote:
From: Andrzej Hajda a.ha...@samsung.com
Add MAX8998 LDO12 and fixed voltage regulator nodes. While at it,
all fixed voltage regulator nodes are grouped in a 'regulators' node.
Signed-off-by: Andrzej Hajda
Hi Sylwester,
On Monday 01 of July 2013 17:22:22 Sylwester Nawrocki wrote:
This patch series includes some fixes and extensions to the Exynos dts
files to add the camera and magnetometer sensor support for the TRATS
and TRATS2 board. It depends on a patch from Tomasz adding initial
TRATS2
Jason, Arnd,
On Fri, 5 Jul 2013 18:39:11 -0300, Ezequiel Garcia wrote:
See the previous version of this patchset for further context:
http://www.mail-archive.com/devicetree-discuss@lists.ozlabs.org/msg35753.html
This new proposal is an attempt to address some issues raised about the PCIe
On Saturday 06 July 2013, Thomas Petazzoni wrote:
Arnd, Jason, if you could confirm that you both agree with this DT
binding soon, Ezequiel and I would quickly adapt the code accordingly,
and hopefully converge towards a final patch set.
Looks all good from what I can tell.
Arnd
On Sat, 6 Jul 2013, Heiko Stübner wrote:
This adds a quirk for IP variants containing two load_count and value
registers that are used to provide 64bit accuracy on 32bit systems.
The added accuracy is currently not used, the driver is only adapted to
handle the different register layout and
On Sat, 6 Jul 2013, Heiko Stübner wrote:
- dw_ced-eoi = apbt_eoi;
+ if (quirks APBTMR_QUIRK_NO_EOI)
+ dw_ced-eoi = apbt_eoi_int_status;
+ else
+ dw_ced-eoi = apbt_eoi;
No again. This has nothing to do with quirks. We use quirks for
workarounds and not for
On Sat, 6 Jul 2013, Heiko Stübner wrote:
Some timer variants use an inverted setting to mask the timer interrupt.
Therefore add a quirk to handle these variants.
And by that add even more pointless conditionals into critical code
pathes.
___
Hi Sachin,
On Friday 05 of July 2013 14:12:28 Sachin Kamat wrote:
Exynos5250 G2D IP requires only the gate clock. Update the
binding documentation accordingly.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Cc: Inki Dae inki@samsung.com
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