The short answer is, you can implement your block in any fashion you
like. If you want to simply change the number of taps, simply editing
our FIR filter (which the Xilinx coregen tools) is the easiest way to
go. The number of taps (up to a degree) mostly depends on the available
resources on your
Hello,
I am working with a USRP X310 and am trying to increase the number of taps
above the default limit of 41. The default RFNoC FIR filter is Xilinx
coregen based and I am wondering if my new FIR filter will also have to be
Xilinx coregen based. According to the attached data sheet the FIR
