On 04/12/2010 05:22 PM, Vikram Ragukumar wrote:
Matt,
In our effort to distill the gemac core and related logic, we have
pulled out the following module under u2_core
SERDES, Dsp core, UART, external RAM interface and the buffer pool
The mac is all contained in simple_gemac, and above that in
Matt,
In our effort to distill the gemac core and related logic, we have
pulled out the following module under u2_core
SERDES, Dsp core, UART, external RAM interface and the buffer pool
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
which is instantiated in
Matt,
3) Do you have an FPGA internal achitecture block diagram of any
type? Is there another group you're aware of doing such "major
modification" FPGA work that we might talk to?
There were some on the wiki at one time. If they're not still there
I'll post a talk I did which covers the ar
Matt-
>> My understanding is that it takes 3 BUFGs and one DCM for tri-mode (maybe
>> one more of each for RGMII support but I
>> don't see that) and, between this and other USRP2 needs, you ran into the
>> limit of 8. Is that accurate? Or would
>> 10/100/1000 support would take more than 3...
My understanding is that it takes 3 BUFGs and one DCM for tri-mode (maybe one
more of each for RGMII support but I
don't see that) and, between this and other USRP2 needs, you ran into the limit
of 8. Is that accurate? Or would
10/100/1000 support would take more than 3...
I can't say how
Matt-
>> About Vikram's 10/100 mode question, we were wondering if it's a design
>> flaw; i.e. something wrong from the start in
>> the original opencores.org source, or if it's fixable but hasn't been a high
>> priority item given USRP2's high data
>> rate requirements. But then I found this p
On 04/07/2010 05:58 PM, Vikram Ragukumar wrote:
Matt,
Thank you for your email.
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac
simple_gemac_wrapper in the fi
On 04/07/2010 09:10 PM, Jeff Brower wrote:
Matt-
About Vikram's 10/100 mode question, we were wondering if it's a design flaw;
i.e. something wrong from the start in
the original opencores.org source, or if it's fixable but hasn't been a high
priority item given USRP2's high data
rate requirem
Matt-
About Vikram's 10/100 mode question, we were wondering if it's a design flaw;
i.e. something wrong from the start in
the original opencores.org source, or if it's fixable but hasn't been a high
priority item given USRP2's high data
rate requirements. But then I found this post:
http://
Matt,
Thank you for your email.
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac
simple_gemac_wrapper in the fifo_2clock_cascade files.
which is instantiated i
On 03/30/2010 11:48 AM, Jeff Brower wrote:
Matt-
We're working on a project at Signalogic to interface one of our DSP
array PCIe cards to the USRP2. This would provide a way for one or
more TI DSPs to "insert" into the data flow and run C/C++ code for
low-latency and/or other high performance a
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