El lun, 23-10-2023 a las 07:58 -0300, Maíra Canal escribió:
> Currently, we are only warning the user if the BIN or RENDER jobs
> don't
> finish before we unregister V3D. We must wait for all jobs to finish
> before unregistering. Therefore, warn the user if TFU or CSD jobs
> are not done by the
From: Jacek Lawrynowicz
IP reset has to followed by ivpu_pll_disable() to properly enter
reset state.
Fixes: 828d63042aec ("accel/ivpu: Don't enter d0i3 during FLR")
Cc: sta...@vger.kernel.org
Signed-off-by: Jacek Lawrynowicz
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Hi,
On 2023-10-17 11:09, Matthew Brost wrote:
> DRM_SCHED_POLICY_SINGLE_ENTITY creates a 1 to 1 relationship between
> scheduler and entity. No priorities or run queue used in this mode.
> Intended for devices with firmware schedulers.
>
> v2:
> - Drop sched / rq union (Luben)
> v3:
> -
On 2023-10-17 11:09, Matthew Brost wrote:
> Rather than a global modparam for scheduling policy, move the scheduling
> policy to scheduler so user can control each scheduler policy.
>
> v2:
> - s/DRM_SCHED_POLICY_MAX/DRM_SCHED_POLICY_COUNT (Luben)
> - Only include policy in scheduler (Luben)
On 2023-10-23 18:35, Danilo Krummrich wrote:
> On Wed, Oct 11, 2023 at 09:52:36PM -0400, Luben Tuikov wrote:
>> Hi,
>>
>> Thanks for fixing the title and submitting a v2 of this patch. Comments
>> inlined below.
>>
>> On 2023-10-09 18:35, Danilo Krummrich wrote:
>>> Currently, job flow control is
On 2023-10-23 18:57, Danilo Krummrich wrote:
> On Tue, Oct 10, 2023 at 09:41:51AM +0200, Boris Brezillon wrote:
>> On Tue, 10 Oct 2023 00:35:53 +0200
>> Danilo Krummrich wrote:
>>
>>> Currently, job flow control is implemented simply by limiting the number
>>> of jobs in flight. Therefore, a
topic/vmemdup-user-array-2023-10-24-1:
vmemdup-user-array API and changes with it.
This is just a process PR to merge the topic branch into drm-next, this
contains some core kernel and drm changes.
Signed-off-by: Dave Airlie
The following changes since commit
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul
Cc: dri-devel@lists.freedesktop.org
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul
Signed-off-by: Imre Deak
---
Hi all,
On Thu, 19 Oct 2023 12:06:18 +1100 Stephen Rothwell
wrote:
>
> On Tue, 10 Oct 2023 12:43:57 +1100 Stephen Rothwell
> wrote:
> >
> > After merging the amdgpu tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> >
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/msm/msm_drv.c
between commit:
cd61a76c210a ("drm/msm: dynamically allocate the drm-msm_gem shrinker")
from the mm-stable tree and commit:
506efcba3129 ("drm/msm: carve out KMS code from msm_drv.c")
Clarify the procedure developer must follow to request privileges to
run tests on Freedesktop gitlab CI.
This measure was added to avoid untrusted people to misuse the
infrastructure.
Signed-off-by: Helen Koike
Reviewed-by: David Heidelberg
---
v2:
- fix typo in commit message
v3:
-no changes
Since the kernel doesn't use a bot like Mesa that requires tests to pass
in order to merge the patches, leave it to developers and/or maintainers
to manually retry.
Suggested-by: Rob Clark
Signed-off-by: Helen Koike
Reviewed-by: David Heidelberg
---
v2:
- no changes
v3:
-no changes
---
Export the resultant kernel config, making it easier to verify if the
resultant config was correctly generated.
Suggested-by: Rob Clark
Signed-off-by: Helen Koike
Acked-by: Dmitry Baryshkov
Reviewed-by: David Heidelberg
---
v2:
- no changes
v3:
-no changes
---
drivers/gpu/drm/ci/build.sh
With the new sharding, the default job timeout is not enough for i915
and their jobs are failing before completing.
See below the current execution time:
job i915:tgl 8/8 has new status: success (37m3s)
job i915:tgl 7/8 has new status: success (19m43s)
job i915:tgl 6/8 has new status:
The Collabora Lava farm added a tag called `subset-1-gfx` to half of
devices the graphics community use.
Lets use this tag so we don't occupy all the resources.
This is particular important because Mesa3D shares the resources with
DRM-CI and use them to do pre-merge tests, so it can block
Since the script that collected the list of the expectation files was
bogus and placing test to the flakes list incorrectly, restart the
expectation files with the correct script.
This reduces a lot the number of tests in the flakes list.
Signed-off-by: Helen Koike
Reviewed-by: David Heidelberg
IGT has recently merged a patch that makes code_getversion test to fails
if the driver isn't loaded or if it isn't the expected one defined in
variable IGT_FORCE_DRIVER.
Without this test, jobs were passing when the driver didn't load or
probe for some reason, giving the illusion that everything
Add helper script that given a gitlab pipeline url, analyse which are
the failures and flakes and update the xfails folder accordingly.
Example:
Trigger a pipeline in gitlab infrastructure, than re-try a few jobs more
than once (so we can have data if failures are consistent across jobs
with the
amdgpu driver wasn't loading because amdgpu firmware wasn't being
installed in the rootfs due to the wrong DEBIAN_ARCH variable.
rename ARCH to DEBIAN_ARCH also, so we don't have the confusing
DEBIAN_ARCH, KERNEL_ARCH and ARCH.
Signed-off-by: Helen Koike
Reviewed-by: David Heidelberg
---
v2:
This series contains the several fixes, making drm/ci much
more reliable and useful.
Highlights:
* Current DRM/CI in drm-misc is broken, this series fixes it with mesa
uprev (commit 1/9).
* The fails.txt and flakes.txt lists were generated by a bogus script,
this series restart that initial
When building containers, some rust packages were installed without
locking the dependencies version, which got updated and started giving
errors like:
error: failed to compile `bindgen-cli v0.62.0`, intermediate artifacts can be
found at `/tmp/cargo-installkNKRwf`
Caused by:
package `rustix
On Tue, 24 Oct 2023 at 01:36, Rob Clark wrote:
>
> On Mon, Oct 23, 2023 at 3:30 PM Dmitry Baryshkov
> wrote:
> >
> > On Tue, 24 Oct 2023 at 01:12, Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > Seems like we need to pick INPUT_SEL=1 when CTM is enabled. But not
> > > otherwise.
> >
On Tue, Oct 10, 2023 at 09:41:51AM +0200, Boris Brezillon wrote:
> On Tue, 10 Oct 2023 00:35:53 +0200
> Danilo Krummrich wrote:
>
> > Currently, job flow control is implemented simply by limiting the number
> > of jobs in flight. Therefore, a scheduler is initialized with a
> > submission limit
On Mon, Oct 23, 2023 at 3:30 PM Dmitry Baryshkov
wrote:
>
> On Tue, 24 Oct 2023 at 01:12, Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Seems like we need to pick INPUT_SEL=1 when CTM is enabled. But not
> > otherwise.
> >
> > Suggested-by: Dmitry Baryshkov
> > Signed-off-by: Rob Clark
>
Hi Chris,
On 2023-10-23 19:52, Christopher Obbard wrote:
> Hi Jonas,
>
> On Mon, 2023-10-23 at 17:37 +, Jonas Karlman wrote:
>> This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats
>> produced
>> by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
>>
On Wed, Oct 11, 2023 at 09:52:36PM -0400, Luben Tuikov wrote:
> Hi,
>
> Thanks for fixing the title and submitting a v2 of this patch. Comments
> inlined below.
>
> On 2023-10-09 18:35, Danilo Krummrich wrote:
> > Currently, job flow control is implemented simply by limiting the number
> > of
On 19/10/23 18:21, Harry Wentland wrote:
> Debugging LUT math is much easier when we can unit test
> it. Add kunit functionality to VKMS and add tests for
> - get_lut_index
> - lerp_u16
>
> Signed-off-by: Harry Wentland
> Cc: Ville Syrjala
> Cc: Pekka Paalanen
> Cc: Simon Ser
> Cc: Harry
On Tue, 24 Oct 2023 at 01:12, Rob Clark wrote:
>
> From: Rob Clark
>
> Seems like we need to pick INPUT_SEL=1 when CTM is enabled. But not
> otherwise.
>
> Suggested-by: Dmitry Baryshkov
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 2 +-
>
From: Rob Clark
Seems like we need to pick INPUT_SEL=1 when CTM is enabled. But not
otherwise.
Suggested-by: Dmitry Baryshkov
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
On Mon, Oct 23, 2023 at 04:22:16PM +0200, Boris Brezillon wrote:
> On Mon, 23 Oct 2023 13:54:13 +
> Matthew Brost wrote:
>
> > On Mon, Oct 23, 2023 at 02:39:37PM +0200, Boris Brezillon wrote:
> > > On Mon, 23 Oct 2023 14:16:06 +0200
> > > Boris Brezillon wrote:
> > >
> > > > Hi,
> > > >
On Mon, Oct 23, 2023 at 04:40:12PM +0200, Alexandre Mergnat wrote:
> Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> along with MT8183 SoC.
>
> Signed-off-by: Alexandre Mergnat
Acked-by: Uwe Kleine-König
What is the merge plan here? Should the whole series go in
On 10/8/23 19:27, Bragatheswaran Manickavel wrote:
On running checkpatch.pl to nouveau_drm.h identified
few warnings. Fixing them in this patch
WARNING: Missing or malformed SPDX-License-Identifier tag in line 1
+/*
WARNING: space prohibited between function name and open parenthesis '('
On Mon, 23 Oct 2023 at 23:37, Simon Ser wrote:
>
> This is already uAPI, xserver parses it. It's useful to document
> since user-space might want to lookup the parent connector.
>
> Additionally, people (me included) have misunderstood the PATH
> property for being stable across reboots, but
Albert Esteve writes:
> From: Michael Banack
>
> To clarify the intent and reasoning behind the hotspot properties
> introduce userspace documentation that goes over cursor handling
> in para-virtualized environments.
>
> The documentation is generic enough to not special case for any
>
On 10/13/23 03:18, Ma Ke wrote:
In nv17_tv_get_hd_modes(), the return value of drm_mode_duplicate()
is assigned to mode, which will lead to a NULL pointer dereference on
failure of drm_mode_duplicate(). The same applies to drm_cvt_mode().
Add a check to avoid null pointer dereference.
Use of DRM_FORMAT_RGB888 and DRM_FORMAT_BGR888 on e.g. RK3288, RK3328
and RK3399 result in wrong colors being displayed.
The issue can be observed using modetest:
modetest -s @:1920x1080-60@RG24
modetest -s @:1920x1080-60@BG24
Vendor 4.4 kernel apply an inverted rb swap for these formats on
This is already uAPI, xserver parses it. It's useful to document
since user-space might want to lookup the parent connector.
Additionally, people (me included) have misunderstood the PATH
property for being stable across reboots, but since a KMS object
ID is baked in there that's not the case. So
Applied. Thanks!
Alex
On Mon, Oct 23, 2023 at 9:06 AM wrote:
>
> In certain types of chips, such as VEGA20, reading the amdgpu_regs_smc file
> could result in an abnormal null pointer access when the smc_rreg pointer is
> NULL. Below are the steps to reproduce this issue and the
On Mon, Oct 23, 2023 at 12:56 PM Konrad Dybcio wrote:
>
>
>
> On 10/23/23 21:42, Rob Clark wrote:
> > On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio
> > wrote:
> >>
> >> New GPUs still use the lower 2 bytes of the chip id (in whatever form
> >> it comes) to signify silicon revision. Drop the
Currently the DRM GPUVM offers common infrastructure to track GPU VA
allocations and mappings, generically connect GPU VA mappings to their
backing buffers and perform more complex mapping operations on the GPU VA
space.
However, there are more design patterns commonly used by drivers, which
can
GPUVM provides common infrastructure to track external and evicted GEM
objects as well as locking and validation helpers.
Especially external and evicted object tracking is a huge improvement
compared to the current brute force approach of iterating all mappings
in order to lock and validate the
Add an abstraction layer between the drm_gpuva mappings of a particular
drm_gem_object and this GEM object itself. The abstraction represents a
combination of a drm_gem_object and drm_gpuvm. The drm_gem_object holds
a list of drm_gpuvm_bo structures (the structure representing this
abstraction),
DRM GEM objects private to a single GPUVM can use a shared dma-resv.
Make use of the shared dma-resv of GPUVM rather than a driver specific
one.
The shared dma-resv originates from a "root" GEM object serving as
container for the dma-resv to make it compatible with drm_exec.
In order to make
Use drm_WARN() and drm_WARN_ON() variants to indicate drivers the
context the failing VM resides in.
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/drm_gpuvm.c| 32 ++
drivers/gpu/drm/nouveau/nouveau_uvmm.c | 3 ++-
include/drm/drm_gpuvm.h
Introduce flags for struct drm_gpuvm, this required by subsequent
commits.
Reviewed-by: Thomas Hellström
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/drm_gpuvm.c| 3 +++
drivers/gpu/drm/nouveau/nouveau_uvmm.c | 2 +-
include/drm/drm_gpuvm.h| 16
Provide a common dma-resv for GEM objects not being used outside of this
GPU-VM. This is used in a subsequent patch to generalize dma-resv,
external and evicted object handling and GEM validation.
Reviewed-by: Thomas Hellström
Signed-off-by: Danilo Krummrich
---
drivers/gpu/drm/drm_gpuvm.c
Currently GPUVM offers common infrastructure to track GPU VA allocations
and mappings, generically connect GPU VA mappings to their backing
buffers and perform more complex mapping operations on the GPU VA space.
However, there are more design patterns commonly used by drivers, which
can
On 10/23/23 21:42, Rob Clark wrote:
On Mon, Oct 23, 2023 at 7:29 AM Konrad Dybcio wrote:
New GPUs still use the lower 2 bytes of the chip id (in whatever form
it comes) to signify silicon revision. Drop the warning that makes it
sound as if that was unintended.
Fixes: 90b593ce1c9e
hange it to ADRENO_6XX_GEN4?
BR,
-R
> return gpu->chip_id & 0xff;
> }
>
>
> ---
> base-commit: e8361b005d7c92997d12f2b85a9e4a525738bd9d
> change-id: 20231023-topic-adreno_warn-42a09bb4bf64
>
> Best regards,
> --
> Konrad Dybcio
>
Add quirk orientation for Ayn Loki Max model.
This has been tested by JELOS team that uses their
own patched kernel for a while now and confirmed by
users in the ChimeraOS discord servers.
Signed-off-by: Bouke Sybren Haarsma
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file
Add quirk orientation for the Ayn Loki Zero.
This also has been tested/used by the JELOS team.
Signed-off-by: Bouke Sybren Haarsma
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
Add orientation quirks for AYN loki devices:
- Ayn Loki Zero
- Ayn Loki Max
The quirks have been tested by the JELOS team and ChimeraOS
who have been patching their own kernel. This has been
confirmed working by users in the ChimeraOS discord
servers.
Since there are additional Ayn Loki devices
On 15 September 2023 15:14:35 EEST, Heikki Krogerus
wrote:
>Hi Dmitry,
>
>On Mon, Sep 04, 2023 at 12:41:50AM +0300, Dmitry Baryshkov wrote:
>> In order to notify the userspace about the DRM connector's USB-C port,
>> export the corresponding port's name as the bridge's path field.
>>
>>
Hi Jonas,
On Mon, 2023-10-23 at 17:37 +, Jonas Karlman wrote:
> Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
> the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
> Also add support for 10-bit 4:4:4 format while at it.
>
> V5: Use
Hi Jonas,
On Mon, 2023-10-23 at 17:37 +, Jonas Karlman wrote:
> DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
> variant of NV15, a 10-bit 2-plane YUV format that has no padding between
> components. Instead, luminance and chrominance samples are grouped into 4s
>
Hi Jonas,
On Mon, 2023-10-23 at 17:37 +, Jonas Karlman wrote:
> This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats
> produced
> by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
> Also include 10-bit 4:4:4 support since VOP can support that also.
>
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
variant of NV15, a 10-bit 2-plane YUV format that has no padding between
components. Instead, luminance and chrominance samples are grouped into 4s
so that each group is packed into an integer number of bytes:
= UVUV =
This series add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced
by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
Also include 10-bit 4:4:4 support since VOP can support that also.
First patch adds new fourcc 10-bit YUV formats with 4:2:2/4:4:4
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by
the Rockchip Video Decoder on RK322X, RK3288, RK3328 and RK3399.
Also add support for 10-bit 4:4:4 format while at it.
V5: Use drm_format_info_min_pitch() for correct bpp
Add missing NV21, NV61 and NV42 formats
V4: Rework
Yo,
On Mon, Oct 23, 2023 at 04:40:11PM +0200, Alexandre Mergnat wrote:
> According to the Mediatek datasheet, the display PWM block has a power
> domain.
Datasheet for which soc? The mt8173? Is it valid for all devices in this
binding?
Cheers,
Conor.
>
> Signed-off-by: Alexandre Mergnat
>
On Mon, Oct 23, 2023 at 04:40:12PM +0200, Alexandre Mergnat wrote:
> Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
> along with MT8183 SoC.
Additionally here, for the subject,
"dt-bindings: pwm: mediatek,pwm-disp: add compatible for mt8365 SoC"
Cheers
Conor.
>
>
On Mon, Oct 23, 2023 at 06:31:45PM +0100, Conor Dooley wrote:
> On Mon, Oct 23, 2023 at 04:40:02PM +0200, Alexandre Mergnat wrote:
> > Display Color Correction for MT8365 is compatible with another SoC.
> > Then, add MT8365 binding along with MT8183 SoC.
>
> This commit message's first line is
On Mon, Oct 23, 2023 at 04:40:02PM +0200, Alexandre Mergnat wrote:
> Display Color Correction for MT8365 is compatible with another SoC.
> Then, add MT8365 binding along with MT8183 SoC.
This commit message's first line is too vague & the second doesn't make
sense. I suspect something as succinct
> -Original Message-
> From: Dmitry Osipenko
> Sent: Monday, October 23, 2023 5:24 AM
> To: Kim, Dongwon ; dri-devel@lists.freedesktop.org
> Cc: kra...@redhat.com; Kasireddy, Vivek
> Subject: Re: [RFC PATCH v2 1/1] drm/virtio: new fence for every plane update
>
> On 10/3/23 04:00,
Hi,
On Mon, Oct 23, 2023 at 9:31 AM Yuran Pereira wrote:
>
> Since "Clean up checks for already prepared/enabled in panels" has
> already been done and merged [1], I think there is no longer a need
> for this item to be in the gpu TODO.
>
> [1] https://patchwork.freedesktop.org/patch/551421/
>
>
https://bugzilla.kernel.org/show_bug.cgi?id=201957
Mario Limonciello (AMD) (mario.limoncie...@amd.com) changed:
What|Removed |Added
CC|
On Mon, Oct 23, 2023 at 04:40:01PM +0200, Alexandre Mergnat wrote:
> Display Adaptive Ambient Light for MT8365 is compatible with another SoC.
> Then, add MT8365 binding along with MT8183 SoC.
s/binding/compatible/, here and in the subject.
Cheers,
Conor.
>
> Signed-off-by: Alexandre Mergnat
This patch introduces an initial KUnit test suite for GEM objects
backed by shmem buffers.
Signed-off-by: Marco Pagani
---
drivers/gpu/drm/Kconfig| 1 +
drivers/gpu/drm/tests/Makefile | 3 +-
drivers/gpu/drm/tests/drm_gem_shmem_test.c | 303
Since "Clean up checks for already prepared/enabled in panels" has
already been done and merged [1], I think there is no longer a need
for this item to be in the gpu TODO.
[1] https://patchwork.freedesktop.org/patch/551421/
Signed-off-by: Yuran Pereira
---
Documentation/gpu/todo.rst | 25
On Mon, Oct 23, 2023 at 09:28:03AM +, Flavio Suligoi wrote:
> > On Fri, Oct 20, 2023 at 03:54:33PM +0200, Flavio Suligoi wrote:
> > > The two properties:
> > >
> > > - max-brightness
> > > - default brightness
> > >
> > > are not really required, so they can be removed from the "required"
> >
Honestly, the less time people spend on this property the better. Lift
the Intel one into core and be done with it. We'll hopefully be able
to remove it in the not-to-distant future with the new color pipeline
API and adding a new property which only sets the connector metadata
instead of
On Fri, Oct 20, 2023 at 7:42 PM Aravind Iddamsetty
wrote:
>
> Our hardware supports RAS(Reliability, Availability, Serviceability) by
> reporting the errors to the host, which the KMD processes and exposes a
> set of error counters which can be used by observability tools to take
> corrective
Since the core function drm_panel_prepare already checks if the
panel is prepared, we can remove this duplicate check from tm5p5_nt35596_prepare
which acts as a no-op. As suggested in the GPU TODO [1]
[1]
Hi Hans,
On Thu, Oct 19, 2023 at 10:26:40AM +0200, Hans Verkuil wrote:
> Hi Maxime,
>
> On 19/10/2023 10:02, Maxime Ripard wrote:
> > Hi,
> >
> > On Wed, Oct 11, 2023 at 03:23:18PM +0200, Daniel Vetter wrote:
> >> On Mon, 6 Mar 2023 at 11:49, Maxime Ripard wrote:
> >>>
> >>> From: Dave
Hi,
On 23/10/2023 16:51, Yuran Pereira wrote:
Since the core function drm_panel_prepare already checks if the
panel is prepared, we can remove this duplicate check from tm5p5_nt35596_prepare
which acts as a no-op. As suggested in the GPU TODO [1]
[1]
MIPI DSI:
- Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg",
to power the pannel plugged to the DSI connector.
- Setup the Display Parallel Interface.
- Add the startek kd070fhfid015 pannel support.
HDMI:
- Add HDMI connector support.
- Add the "ite,it66121" HDMI bridge
Display Color Correction for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding
along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered
before mtk_dsi_poweron. lanes_ready flag toggle to true during
mtk_dsi_lane_ready function, and the DSI module is set up during
mtk_dsi_poweron.
Later, during panel driver init, mtk_dsi_lane_ready is triggered but does
nothing
Display GAMMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
- Add aliases for each display components to help display drivers.
- Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
for the LED driver of mobile LCM.
- Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
output)
- Add the display mutex support.
-
From: Fabien Parent
DPI is part of the display / multimedia block in MediaTek SoCs, and
always have a power-domain (at least in the upstream device-trees).
Add the power-domains property to the binding documentation.
Signed-off-by: Fabien Parent
Signed-off-by: Alexandre Mergnat
---
Display Color for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Fabien Parent
Add DRM support for MT8365 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Alexandre Mergnat
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
Display Overlay for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8192 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Enable this feature for the i350-evk HDMI connector support.
Signed-off-by: Alexandre Mergnat
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..0a60e7616abe 100644
---
From: Fabien Parent
MT8365 requires an additional clock for DPI. Add support for that
additional clock.
Signed-off-by: Fabien Parent
Signed-off-by: Alexandre Mergnat
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 50 +-
1 file changed, 49 insertions(+), 1
Display Dither for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
According to the Mediatek datasheet, the display PWM block has a power
domain.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8
1 file changed, 8 insertions(+)
diff --git
From: Fabien Parent
DPI for MT8365 is compatible with MT8192 but requires an additional
clock. Modify the documentation to requires this clock only on MT8365 SoCs.
Signed-off-by: Fabien Parent
Signed-off-by: Alexandre Mergnat
---
.../bindings/display/mediatek/mediatek,dpi.yaml | 19
Display Serial Interface for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
Display Data Path Read DMA for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Display Adaptive Ambient Light for MT8365 is compatible with another SoC.
Then, add MT8365 binding along with MT8183 SoC.
Signed-off-by: Alexandre Mergnat
---
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
: d27bed55ce32b0732ef65561851fec3dc8d01852
change-id: 20231023-display-support-c6418b30e419
Best regards,
--
Alexandre Mergnat
* to older things.
-*/
- WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1);
return gpu->chip_id & 0xff;
}
---
base-commit: e8361b005d7c92997d12f2b85a9e4a525738bd9d
change-id: 20231023-topic-adreno_warn-42a09bb4bf64
Best regards,
--
Konrad Dybcio
On Mon, 23 Oct 2023 13:54:13 +
Matthew Brost wrote:
> On Mon, Oct 23, 2023 at 02:39:37PM +0200, Boris Brezillon wrote:
> > On Mon, 23 Oct 2023 14:16:06 +0200
> > Boris Brezillon wrote:
> >
> > > Hi,
> > >
> > > On Tue, 17 Oct 2023 08:09:56 -0700
> > > Matthew Brost wrote:
> > >
> >
On Mon, Oct 23, 2023 at 02:39:37PM +0200, Boris Brezillon wrote:
> On Mon, 23 Oct 2023 14:16:06 +0200
> Boris Brezillon wrote:
>
> > Hi,
> >
> > On Tue, 17 Oct 2023 08:09:56 -0700
> > Matthew Brost wrote:
> >
> > > +static void drm_sched_run_job_work(struct work_struct *w)
> > > +{
> > > +
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