Hi,
On 12/09/2025 08:42, Svyatoslav Ryhel wrote:
Document Sharp LQ079L1SX01 panel found in Xiaomi Mi Pad.
The patch doesn't apply on drm-misc-next, please rebase.
Neil
Signed-off-by: Svyatoslav Ryhel
---
.../display/panel/sharp,lq079l1sx01.yaml | 99 +++
1 file cha
On Fri, Jul 04, 2025 at 05:03:56PM +0800, Liu Ying wrote:
> Add a helper to get ExtDst source selection. This is needed by
> disabling CRTC at boot in an upcoming commit which tries to get
> the source selection.
>
> Signed-off-by: Liu Ying
Reviewed-by: Frank Li
> ---
> drivers/gpu/drm/imx/dc
Hi,
On 19/09/2025 18:42, Marek Vasut wrote:
> On 9/19/25 5:21 PM, Tomi Valkeinen wrote:
>
> Hello Tomi,
>
On 05/09/2025 00:01, Marek Vasut wrote:
> This controller can have both bridges and panels connected to it. In
> order to describe panels properly in DT, pull in dsi-controller.
This reverts commit f6bfc9afc7510cb5e6fbe0a17c507917b0120280.
since we are going to revert commit 5307dce878d4 ("drm/gem: Acquire
references on GEM handles for framebuffers"), which it was fixing, this
commit won't be needed anymore.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/drm_framebuffe
On 9/19/25 5:39 PM, Joel Fernandes wrote:
> On Tue, Sep 16, 2025 at 05:59:18AM -0400, Joel Fernandes wrote:
> [...]
In C also this is valid. If you passed a higher value than what the
bitfield can hold, the compiler will still just use the bits that it
needs and ignore the rest.
>>>
On Wed, 03 Sep 2025 12:49:51 +0530, Akhil P Oommen wrote:
> This series adds support for A623 GPU found in QCS8300 (internal codename -
> Monaco)
> chipsets. This GPU IP is very similar to A621 GPU, except for the UBWC
> configuration
> and the GMU firmware.
>
> Since the last revision, there
When a zone device page is split (via huge pmd folio split). The driver
callback for folio_split is invoked to let the device driver know that the
folio size has been split into a smaller order.
Provide a default implementation for drivers that do not provide this
callback that copies the pgmap a
On 9/19/25 06:49, Louis Chauvet wrote:
Le 18/09/2025 à 02:45, Alex Hung a écrit :
On 9/17/25 08:47, Nícolas F. R. A. Prado wrote:
On Tue, 2025-09-16 at 19:54 -0600, Alex Hung wrote:
On 9/5/25 11:12, Louis Chauvet wrote:
Le 15/08/2025 à 05:50, Alex Hung a écrit :
From: Harry Wentla
On Wed, Aug 27, 2025 at 3:28 AM Alistair Popple wrote:
>
> +register!(NV_PRISCV_RISCV_CPUCTL @ PFalconBase[0x1388] {
> +7:7 active_stat as bool;
> +0:0 halted as bool;
> +});
Two more things I've noticed:
1) I think the convention is to list the bits in increase position.
Tha
On Tue, Sep 16, 2025 at 05:59:18AM -0400, Joel Fernandes wrote:
[...]
> > > In C also this is valid. If you passed a higher value than what the
> > > bitfield can hold, the compiler will still just use the bits that it
> > > needs and ignore the rest.
> >
> > In C we've got FIELD_{PREP,GET,MODIFY}
Hi all,
I just talked with Thomas that these two patches are preventing amdgpu
driver to be unloaded:
`modprobe: FATAL: Module amdgpu is in use.`
and there is no process using the driver.
We agreed that the best approach now is to completely revert the work
done for improving DMA bug handling t
On Fri Sep 19, 2025 at 10:56 PM CEST, Gary Guo wrote:
> Turbofish is cumbersome to write with just magic numbers, and the
> fact `{}` is needed to pass in constant expressions made this much
> worse. If the drivers try hard to avoid magic numbers, you would
> effective require all code to be `::<{
On Tue, Sep 16, 2025 at 05:59:18AM -0400, Joel Fernandes wrote:
[...]
> > > > The same question for the setters. What would happen for this:
> > > >
> > > > let bf = bf::default()
> > > > .set_state(0xf)
> > > > .set_ready(true);
> > > >
> > > > I think that after th
On 19.09.25 10:46, Tvrtko Ursulin wrote:
>
> On 19/09/2025 09:01, Christian König wrote:
>> On 19.09.25 09:43, Tvrtko Ursulin wrote:
>>> On 19/09/2025 07:46, Christian König wrote:
On 18.09.25 22:09, Thadeu Lima de Souza Cascardo wrote:
> On certain workloads, like on ChromeOS when openin
Move resets to qmp_phy_cfg for per-PHY customization. Keep legacy DT
path on the old hardcoded list; non-legacy path uses cfg->reset_list.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git
On Fri, Jul 04, 2025 at 05:03:58PM +0800, Liu Ying wrote:
> It's unnecessary to set initial ExtDst source selection because KMS
> driver would do that when doing atomic commits. Drop the selection.
> This is needed as a preparation for reading ExtDst source selection
> when trying to disable CRTC
Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
Add a new cap that drivers can set to signal they support post-blend
color pipelines.
Signed-off-by: Nícolas F. R. A. Prado
Reviewed-by: Louis Chauvet
---
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/drm/drm_drv.h | 6
On 9/19/25 7:45 AM, Neil Armstrong wrote:
This patch hasn't been reviewed, and anyway the subject is wrong, it
should start with MAINTAINERS:
please fix ans send a v3.
Thanks,
Neil
Is there a rule that a driver must be reviewed before getting
MAINTAINERS? I'm a little bit confused by your mess
Hi Dave and Sima, here's the last pull request towards 6.18 for xe.
Several refactors and code moving around with a few big changes.
This is reproducing a bug in dim in which triggers a warning about
"missing mandatory Ack from maintainer" for commit 9e9787414882
("drm/xe/userptr: replace xe_hmm
On Fri, Sep 12, 2025 at 11:38 AM Nicolas Frattaroli
wrote:
> +static irqreturn_t mtk_gpueb_mbox_thread(int irq, void *data)
> +{
> + struct mtk_gpueb_mbox_chan *ch = data;
> + int status;
> +
> + status = atomic_cmpxchg(&ch->rx_status,
> + MBOX_FULL
On Fri, Jul 04, 2025 at 05:03:59PM +0800, Liu Ying wrote:
> It's unnecessary to set initial primary and secondary input selections
> because KMS driver would do that when doing atomic commits. Drop the
> selections. This is needed as a preparation for reading LayerBlend
> secondary input selectio
Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
Introduce colorop helper counterparts for post-blend color pipelines
that take a CRTC instead of a plane.
Signed-off-by: Nícolas F. R. A. Prado
Reviewed-by: Louis Chauvet
---
drivers/gpu/drm/drm_colorop.c | 73 +++
On 2025-09-17 15:49, Melissa Wen wrote:
>
>
> On 12/09/2025 15:50, Harry Wentland wrote:
>>
>> On 2025-09-11 13:21, Melissa Wen wrote:
>>> Don't update DC stream color components during atomic check. The driver
>>> will continue validating the new CRTC color state but will not change DC
>>> st
On Fri, Jul 04, 2025 at 05:03:51PM +0800, Liu Ying wrote:
> Fix off-by-one issue in LINEWIDTH, LINECOUNT, FRAMEWIDTH and FRAMEHEIGHT
> macro definitions. The first two macros are used to set a fetchunit's
> source buffer dimension and the other two are used to set a fetchunit's
> frame dimension.
On Fri, Sep 19, 2025 at 11:26:19AM +0200, Benno Lossin wrote:
> On Fri Sep 19, 2025 at 9:59 AM CEST, Joel Fernandes wrote:
> > Hello, Danilo,
> >
> >> On Sep 19, 2025, at 1:26 AM, Danilo Krummrich wrote:
> >>
> >> On Thu Sep 18, 2025 at 8:13 PM CEST, Joel Fernandes wrote:
> On Thu, Sep 18, 2
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.
v1: Rename the title of patch [Ankit]
v2: Remove setup_casf from here[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_casf.c | 2 +
driv
Commit de8548813824 ("drm/panthor: Add the scheduler logical block")
handled destruction of a group's queues' drm scheduler entities early
into the group destruction procedure.
However, that races with the group submit ioctl, because by the time
entities are destroyed (through the group destroy io
Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
Rename the existing color pipeline helpers so they contain "pre_blend"
in the name to make them clearly distinguishable from the post-blend
helpers when they're introduced.
Signed-off-by: Nícolas F. R. A. Prado
Reviewed-by: Louis Chau
From: Randolph Sapp
Update the memory region listed in the k3-am62p.dtsi for the BXS-4-64
GPU to match the Main Memory Map described in the TRM [1].
[1] https://www.ti.com/lit/ug/spruj83b/spruj83b.pdf
Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs")
Signed-off-by: Randolp
Hi Dave, Simona,
Updates for 6.18.
The following changes since commit 2fd653b9bb5aacec5d4c421ab290905898fe85a2:
drm/amd/display: Drop dm_prepare_suspend() and dm_complete() (2025-09-05
17:38:42 -0400)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
This is the GPU/NPU combined device found on the ST STM32MP25 SoC.
Feature bits taken from the downstream kernel driver 6.4.21.
Signed-off-by: Marek Vasut
---
Cc: Christian Gmeiner
Cc: David Airlie
Cc: Lucas Stach
Cc: Simona Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: etna...@lists.freedes
On Fri, Jul 04, 2025 at 05:03:55PM +0800, Liu Ying wrote:
> In TCON operation mode, sync signals from FrameGen are ignored, but
> a much more customized output timing can be generated by the TCON
> module. By using TCON operaton mode, generate KACHUNK signal along
> with HSYNC/VSYNC/data enable si
On Fri, Sep 19, 2025 at 10:24:24PM +0800, Xiangxu Yin wrote:
> Move USB-only register setup from com_init to qmp_usbc_usb_power_on,
> so it runs only for USB mode.
Please rewrite the commit message to start from the problem description.
With that fixed:
Reviewed-by: Dmitry Baryshkov
>
> Sig
On Fri, Sep 19, 2025 at 10:24:28PM +0800, Xiangxu Yin wrote:
> Add dedicated headers for DP v2 PHY, including QSERDES COM and TX/RX
> register definitions.
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h | 21
> drivers/phy/qualcomm/phy-qcom-qmp-qs
On Mon Sep 15, 2025 at 9:34 AM CDT, Michael Walle wrote:
> The TISCI firmware will return 0 if the clock or consumer is not
> enabled although there is a stored value in the firmware. IOW a call to
> set rate will work but at get rate will always return 0 if the clock is
> disabled.
> The clk frame
On Fri, Sep 19, 2025 at 03:41:56AM +0300, Dmitry Baryshkov wrote:
> On Thu, Sep 18, 2025 at 09:28:52PM +0800, Jun Nie wrote:
> > 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> > And 4 DSC are preferred for power optimal in this case due to width
> > limitation of SSPP and M
On Fri, Sep 19, 2025 at 10:24:29PM +0800, Xiangxu Yin wrote:
> Add QCS615-specific configuration for USB/DP PHY, including DP init
> routines, voltage swing tables, and platform data. Add compatible
> "qcs615-qmp-usb3-dp-phy".
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-
Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
As a preparatory step for supporting post-blend color pipelines in VKMS,
rename pre_blend_color_transform() to color_transform() and make it take
the first colorop instead of a plane state, so it can be shared by both
pre- and post-blend
On Fri, Sep 19, 2025 at 10:24:26PM +0800, Xiangxu Yin wrote:
> Define qmp_usbc_dp_phy_ops struct to support DP mode on USB/DP
> switchable PHYs.
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 194
> ++-
> 1 file changed, 193 inserti
On Fri, Sep 19, 2025 at 10:24:31PM +0800, Xiangxu Yin wrote:
> QCS615 platform requires non-default logical-to-physical lane mapping due
> to its unique hardware routing. Unlike the standard mapping sequence
> <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit
> configuration via the dat
On Fri, Sep 19, 2025 at 10:24:25PM +0800, Xiangxu Yin wrote:
> Extend TCSR parsing to read optional dp_phy_mode_reg and add
> qmp_usbc_set_phy_mode() to switch between USB and DP modes when
> supported.
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 25
Document Sharp LQ079L1SX01 panel found in Xiaomi Mi Pad.
Signed-off-by: Svyatoslav Ryhel
Reviewed-by: Rob Herring (Arm)
---
.../display/panel/sharp,lq079l1sx01.yaml | 99 +++
1 file changed, 99 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/pan
On Fri, Jul 04, 2025 at 05:03:53PM +0800, Liu Ying wrote:
> Display Prefetch Resolve Gasket(PRG) is a part of a FetchUnit's
> prefetch engine. It sits between a Display Prefetch Resolve
> Channel(DPRC) and a FetchUnit. Add a platform driver to support
> the PRG.
>
> Signed-off-by: Liu Ying
> ---
On 9/19/25 7:03 PM, Tomi Valkeinen wrote:
Hello Tomi,
Ok. My point was just that the dsi-controller.yaml doesn't allow
"bridge" node (you can just rename the panel to bridge to test). I
thought someone (I just can't remember who was it =) will send a patch
for it, but I think that hasn't happen
This panel requires dual-channel mode. The device accepts video-mode data
on 8 lanes and will therefore need a dual-channel DSI controller. The two
interfaces that make up this device need to be instantiated in the
controllers that gang up to provide the dual-channel DSI host.
Signed-off-by: Svyat
On Fri, Jul 04, 2025 at 05:04:01PM +0800, Liu Ying wrote:
> One prefetch engine consists of one DPR channel and one or two PRGs.
> Each PRG handles one planar in a pixel format. Every FetchUnit used
> by KMS may attach to a PRG and hence use a prefetch engine. So, to
> simplify driver code, alway
On Thu, Sep 18, 2025 at 09:29:02PM +0800, Jun Nie wrote:
> To support high-resolution cases that exceed the width limitation of
> a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate,
> additional pipes are necessary to enable parallel data processing
> within the SSPP width constr
Hi,
On 19/09/2025 18:42, Marek Vasut wrote:
> On 9/19/25 5:21 PM, Tomi Valkeinen wrote:
>
> Hello Tomi,
>
On 05/09/2025 00:01, Marek Vasut wrote:
> This controller can have both bridges and panels connected to it. In
> order to describe panels properly in DT, pull in dsi-controller.
Following the discussion from:
https://lore.kernel.org/dri-devel/7c6a3aa0-c1eb-4726-988a-460c4895f...@amd.com/T/#m32a0260769a0ffb2f114d00066ef3bfda91f9fd6
Idea being that we can afford with no performance benefit to try less hard when
allocating contiguous backing store larger than the size whi
On Fri, Sep 19, 2025 at 10:24:23PM +0800, Xiangxu Yin wrote:
> Add USB/DP switchable PHY clock registration and DT parsing for DP offsets.
> Extend qmp_usbc_register_clocks and clock provider logic to support both
> USB and DP instances.
Why?
>
> Signed-off-by: Xiangxu Yin
> ---
> drivers/phy/
On Fri, Sep 19, 2025 at 10:24:22PM +0800, Xiangxu Yin wrote:
> Move resets to qmp_phy_cfg for per-PHY customization. Keep legacy DT
> path on the old hardcoded list; non-legacy path uses cfg->reset_list.
Why? Start your commit messages with the description of the issue that
you are trying to solve
Le 18/09/2025 à 02:43, Nícolas F. R. A. Prado a écrit :
Print the value of the color pipeline in the CRTC state as part of the
CRTC state print.
Signed-off-by: Nícolas F. R. A. Prado
---
drivers/gpu/drm/drm_atomic.c | 8 +---
drivers/gpu/drm/drm_colorop.c | 26 ++
Both sharpness and panel fitter use pipe scaler,
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler is available and make sure that only
either of panel fitter or sharpness is enabled at
a time.
v2: Add the panel fitting check befor
This reverts commit 5307dce878d4126e1b375587318955bd019c3741.
We've already reverted all other commits related to dma_bug handling and
there is still something wrong with this approach that does not allow
unloading a driver. By reverting this commit, we'd just go back ot the
old behavior.
Signed-
On 9/19/25 5:21 PM, Tomi Valkeinen wrote:
Hello Tomi,
On 05/09/2025 00:01, Marek Vasut wrote:
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel nod
Extend qmp_usbc_offsets and qmp_phy_cfg with DP-specific fields,
including register offsets, init tables, and callback hooks. Also
update qmp_usbc struct to track DP-related resources and state.
This enables support for USB/DP switchable Type-C PHYs that operate
in either mode.
Reviewed-by: Dmitry
Sharp LQ079L1SX01 panel is a LCD panel working in dual video mode found in
Xiaomi Mi Pad (A0101).
---
Changes in v2:
- adjusted schema with ">" and dsi0 > dsi
- fixed copyright from Nvidia to Xiaomi since sconfiguration equence is
based on the downstream Xiaomi code.
- adjusted commit name of se
On Fri, Jul 04, 2025 at 05:04:00PM +0800, Liu Ying wrote:
> Add a helper dc_fu_get_dprc() to get DPR channel for FetchUnit.
> And, call it from dc_{fl,fw)_bind() to get DPR channels for
> FetchLayer and FetchWarp.
>
> Signed-off-by: Liu Ying
Reviewed-by: Frank Li
> ---
> drivers/gpu/drm/imx/dc
The pull request you sent on Fri, 19 Sep 2025 13:32:16 +1000:
> https://gitlab.freedesktop.org/drm/kernel.git tags/drm-fixes-2025-09-19
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/f2738f5660f5c48eb9254689b569640091d3674f
Thank you!
--
Deet-doot-dot, I am a bot.
h
On Fri, Jul 04, 2025 at 05:03:57PM +0800, Liu Ying wrote:
> Add a helper to get LayerBlend secondary input selection. This is
> needed by disabling CRTC at boot in an upcoming commit which tries
> to get the selection.
>
> Signed-off-by: Liu Ying
Reviewed-by: Frank Li
> ---
> drivers/gpu/drm/
Hi,
On 08/09/2025 15:54, Marek Vasut wrote:
> On 9/8/25 9:43 AM, Tomi Valkeinen wrote:
>> Hi,
>
> Hello Tomi,
>
>> On 05/09/2025 00:01, Marek Vasut wrote:
>>> This controller can have both bridges and panels connected to it. In
>>> order to describe panels properly in DT, pull in dsi-controller.
пт, 19 вер. 2025 р. о 17:45 Svyatoslav Ryhel пише:
>
> пт, 19 вер. 2025 р. о 17:36 Neil Armstrong пише:
> >
> > Hi,
> >
> > On 12/09/2025 08:42, Svyatoslav Ryhel wrote:
> > > Document Sharp LQ079L1SX01 panel found in Xiaomi Mi Pad.
> >
> > The patch doesn't apply on drm-misc-next, please rebase.
On Fri, Jul 04, 2025 at 05:03:54PM +0800, Liu Ying wrote:
> Display Prefetch Resolve Channel(DPRC) is a part of a prefetch engine.
> It fetches display data, transforms it to linear format and stores it
> to DPRC's RTRAM. PRG, as the other part of a prefetch engine, acts as
> a gasket between the
On Fri, Jul 04, 2025 at 05:03:52PM +0800, Liu Ying wrote:
> CRTC(s) could still be running after the DRM device is unplugged by
> calling drm_dev_unplug(), because the CRTC disablement logic is
> protected and bypassed by the drm_dev_enter()/drm_dev_exit() pair.
> Hence, Pixel Engine's AXI clock us
Add USB/DP switchable PHY clock registration and DT parsing for DP offsets.
Extend qmp_usbc_register_clocks and clock provider logic to support both
USB and DP instances.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 210 ++-
1 file changed
Hi,
I have noticed that the (bo) size arguments to those is unused by half
of the drivers, and that there is also ttm_resource->size. The latter
also looks mostly equal to the bo size, unless on some driver path the
resource can end up larger than the bo? Would it matter?
Anyway, overall q
On Fri, Jul 04, 2025 at 05:03:50PM +0800, Liu Ying wrote:
> Add i.MX8qxp prefetch engine DT binding files to
> 'DRM DRIVERS FOR FREESCALE IMX8 DISPLAY CONTROLLER' section.
>
> Signed-off-by: Liu Ying
Reviewed-by: Frank Li
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff -
On Fri, Sep 19, 2025 at 02:15:29PM +0100, Tvrtko Ursulin wrote:
> No need to initialize a subset of fields to zero.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/ttm/ttm_bo_util.c | 10 ++
> drivers/gpu/drm/ttm/ttm_device.c | 5 +
> drivers/gpu/drm/ttm/ttm_resource.c
On Fri, Sep 19, 2025 at 02:15:27PM +0100, Tvrtko Ursulin wrote:
> Struct ttm_operation_ctx initializer in ttm_bo_init_validate assumes the
> order of the structure fields when it is configuring the interruptible
> flag.
>
> Fix it by using named initialization.
>
> Signed-off-by: Tvrtko Ursulin
пт, 19 вер. 2025 р. о 17:36 Neil Armstrong пише:
>
> Hi,
>
> On 12/09/2025 08:42, Svyatoslav Ryhel wrote:
> > Document Sharp LQ079L1SX01 panel found in Xiaomi Mi Pad.
>
> The patch doesn't apply on drm-misc-next, please rebase.
>
Sure, but I have synced with drm-misc-next right now and it applied
On 16/09/2025 04:32, Paul Sajna wrote:
This patch series adds a drm panel driver for the LG SW49410 panel found
in the LG G7 ThinQ (codename judyln).
The basic driver skeleton was generated by
https://github.com/msm8916-mainline/linux-mdss-dsi-panel-driver-generator
from the vendor device-tree.
Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.
v2: Update subject[Ankit]
v3: Add the state compare[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drive
To enable or disable the sharpness check the
casf_enable flag. While enabling the sharpness
write the programmable coefficients, sharpness
register bits and also enable the scaler.
Load the filter lut value which needs to be done
one time while enabling the sharpness.
v2: Introduce casf_enable her
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all values and then dividing each value with a sum.
Add HAS_CASF macro to check whether platform supports
the content adaptive sharpness capability or not.
v2: Update commit message[Ankit]
v3: Remove \n from middle[Jani]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 7 +++
Many a times images are blurred or upscaled content is also not as
crisp as original rendered image. Traditional sharpening techniques often
apply a uniform level of enhancement across entire image, which sometimes
result in over-sharpening of some areas and potential loss of natural detail
Hi,
On Fri, Sep 19, 2025 at 4:11 AM Zhijian Yan
wrote:
>
> Add panel driver support for the KD116N3730A12 eDP panel.
> This includes initialization sequence and compatible string, the
> enable timimg required 50ms.
>
> KD116N3730A12:
> edid-decode (hex):
>
> 00 ff ff ff ff ff ff 00 2c 83 97 03 00
Since max_dp_lanes and max_dp_link_rate are link-specific parameters, move
their parsing from dp_panel to dp_link for better separation of concerns.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Xiangxu Yin
---
drivers/gpu/drm/msm/dp/dp_link.c | 57
drivers/gpu/drm/
QCS615 platform requires non-default logical-to-physical lane mapping due
to its unique hardware routing. Unlike the standard mapping sequence
<0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit
configuration via the data-lanes property in the device tree. This ensures
correct signal rout
Add QCS615-specific configuration for USB/DP PHY, including DP init
routines, voltage swing tables, and platform data. Add compatible
"qcs615-qmp-usb3-dp-phy".
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 395 +++
1 file changed, 395 inser
Add dedicated headers for DP v2 PHY, including QSERDES COM and TX/RX
register definitions.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h | 21
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h | 106 +
.../phy/qualcomm/phy-qcom-qmp-q
Define qmp_usbc_dp_phy_ops struct to support DP mode on USB/DP
switchable PHYs.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 194 ++-
1 file changed, 193 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
Move USB-only register setup from com_init to qmp_usbc_usb_power_on,
so it runs only for USB mode.
Signed-off-by: Xiangxu Yin
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qm
To support following DisplayPort (DP) mode over the Type-C PHY, rename
USB-specific functions and ops to clearly separate them from common or
DP-related logic.
This is a preparatory cleanup to enable USB + DP dual mode.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Xiangxu Yin
---
drivers/phy/q
Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
on QCS615 Platform. This PHY supports both USB3 and DP functionality
over USB-C, with PHY mode switching capability. It does not support
combo mode.
Signed-off-by: Xiangxu Yin
---
.../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.y
| 1058 ++--
drivers/phy/qualcomm/phy-qcom-qmp.h|3 +
11 files changed, 1412 insertions(+), 168 deletions(-)
---
base-commit: 8f7f8b1b3f4c613dd886f53f768f82816b41eaa3
change-id: 20250919-add-displayport-support-for-qcs615-platform-f885597b3573
Best regards,
--
Xiangxu Yin
Let the TTM pool allocator know that we can afford for it to expend less
effort for satisfying contiguous allocations larger than 2MiB. The latter
is the maximum relevant PTE entry size and the driver and hardware are
happy to get larger blocks only opportunistically.
Signed-off-by: Tvrtko Ursulin
On 19 Sep 2025, at 1:01, Balbir Singh wrote:
> On 9/18/25 12:49, Zi Yan wrote:
>> On 16 Sep 2025, at 8:21, Balbir Singh wrote:
>>
>>> Add routines to support allocation of large order zone device folios
>>> and helper functions for zone device folios, to check if a folio is
>>> device private and
Struct ttm_operation_ctx initializer in ttm_bo_init_validate assumes the
order of the structure fields when it is configuring the interruptible
flag.
Fix it by using named initialization.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/ttm/ttm_bo.c | 2 +-
1 file changed, 1 insertion(+), 1 de
GPUs typically benefit from contiguous memory via reduced TLB pressure and
improved caching performance, where the maximum size of contiguous block
which adds a performance benefit is related to hardware design.
TTM pool allocator by default tries (hard) to allocate up to the system
MAX_PAGE_ORDER
At the moment the TTM code has a few places which exibit sub-optimal
patterns regarding local variable usage:
* Having a local with some object cached but not always using it.
* Having a local for a single use object member access.
* Failed opportunities to use a local to cache a pointer.
Lets
No need to initialize a subset of fields to zero.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 10 ++
drivers/gpu/drm/ttm/ttm_device.c | 5 +
drivers/gpu/drm/ttm/ttm_resource.c | 5 +
drivers/gpu/drm/ttm/ttm_tt.c | 2 +-
4 files changed, 5 ins
Function has a single caller and the resource cannot be NULL therefore
remove the early return check.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/ttm/ttm_resource.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c
b/drivers/gpu/drm/ttm/ttm_resource.
Some small cleanups, nothing intentionally functional. It is mostly about
applying some consistency to when to use a local variable to cache something,
when not, and making the code use the ones already there.
Tvrtko Ursulin (4):
drm/ttm: Make ttm_bo_init_validate safe against ttm_operation_ctx
From: "Matthew Wilcox (Oracle)"
[ Upstream commit f9bff0e31881d03badf191d3b0005839391f5f2b ]
Patch series "New page table range API", v6.
This patchset changes the API used by the MM to set up page table entries.
The four APIs are:
set_ptes(mm, addr, ptep, pte, nr)
update_mmu_cache_ran
From: David Laight
[ Upstream commit 867046cc7027703f60a46339ffde91a1970f2901 ]
Allow (for example) min(unsigned_var, 20).
The opposite min(signed_var, 20u) is still errored.
Since a comparison between signed and unsigned never makes the unsigned
value negative it is only necessary to adjust t
From: David Laight
[ Upstream commit a5743f32baec4728711bbc01d6ac2b33d4c67040 ]
Use BUILD_BUG_ON_MSG(statically_true(ulo > uhi), ...) for the sanity check
of the bounds in clamp(). Gives better error coverage and one less
expansion of the arguments.
Link:
https://lkml.kernel.org/r/34d53778977
From: Linus Torvalds
[ Upstream commit 1a251f52cfdc417c84411a056bc142cbd77baef4 ]
This just standardizes the use of MIN() and MAX() macros, with the very
traditional semantics. The goal is to use these for C constant
expressions and for top-level / static initializers, and so be able to
simplif
Remove the MIN() and MAX() macros from zstd_internal.h to avoid
duplicate definitions now that the generic MIN() and MAX() macros
are available globally.
This change continues commit 1a251f52cfdc ("minmax: make generic MIN()
and MAX() macros available everywhere") and is required for 5.10.y,
where
From: Bart Van Assche
[ Upstream commit 92d23c6e94157739b997cacce151586a0d07bb8a ]
There are two definitions of the is_signed_type() macro: one in
and a second definition in .
As suggested by Linus Torvalds, move the definition of the
is_signed_type() macro into the header file. Change
the de
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