Hi Heiko
On 2017年12月02日 05:58, Heiko Stuebner wrote:
Am Freitag, 1. Dezember 2017, 13:42:46 CET schrieb Doug Anderson:
Hi,
On Wed, Nov 29, 2017 at 6:27 PM, Chris Zhong <z...@rock-chips.com> wrote:
Hi Doug
Thank you for mentioning this patch.
I think the focus of the discussion is:
of
Type-C phy, these 2 phy have different bits, just similar to other bits
(such as "pipe-status").
Put them to DTS file might be a accepted practice.
On 2017年11月29日 07:32, Doug Anderson wrote:
Hi,
On Thu, Feb 9, 2017 at 11:44 PM, Chris Zhong <z...@rock-chips.com> wrote
Some DP/HDMI sink need to receive the audio infoframe to play sound,
especially some multi-channel AV receiver, they need the
channel_allocation from infoframe to config the speakers. Send the
audio infoframe via SDP will make them work properly.
Signed-off-by: Chris Zhong <z...@rock-chips.
Hi Sean
Thanks for your replying.
On Tuesday, July 18, 2017 04:23 AM, Sean Paul wrote:
On Sat, Jul 15, 2017 at 07:00:18PM +0800, Chris Zhong wrote:
Some DP/HDMI sink need to receive the audio infoframe to play sound,
especially some multi-channel AV receiver, they need the
channel_allocation
Some DP/HDMI sink need to receive the audio infoframe to play sound,
especially some multi-channel AV receiver, they need the
channel_allocation from infoframe to config the speakers. Send the
audio infoframe via SDP will make them work properly.
Signed-off-by: Chris Zhong <z...@rock-chips.
Some DP/HDMI sink need to receive the audio infoframe to play sound,
especially some multi-channel AV receiver, they need the
channel_allocation from infoframe to config the speakers. Send the
audio infoframe via SDP will make them work properly.
Signed-off-by: Chris Zhong <z...@rock-chips.
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
...
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
Tested-by: Brian Norris <briannor...@chromium.org>
---
Changes in v4:
- remove backlight check aft
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v4:
- remove "additional"
Changes in v3: No
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chr
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v4: None
C
in v3:
- add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399
- add a DW_MIPI_NEEDS_GRF_CLK for RK3399
Changes in v2:
- check the grf_clk only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings: add the grf clock for dw-mipi-dsi
drm/rockchip/dsi: enable the grf clk before writing
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v4:
- print the err after clk_prepare_enable(
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Brian Norris <briannor...@chromium.org>
---
Changes in v3: None
Changes in v2: None
.../bindings/disp
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
Tested-by: Brian Norris <briannor...@chromium.org>
---
Changes in v3:
- printk err after regulator_
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3:
- add a DW_MIPI_NEEDS_GRF_CLK for RK3399
Changes in v2:
- check the grf_clk only for RK3399
drive
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file c
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3:
- add a DW_MIPI_NEEDS_PHY_C
only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings: add the grf clock for dw-mipi-dsi
drm/rockchip/dsi: enable the grf clk before writing grf registers
drm/rockchip/dsi: correct the grf_switch_reg name
.../display/rockchip
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Hi John
On 03/16/2017 06:55 PM, John Keeping wrote:
On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote:
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2:
- check the grf_clk only for RK3399
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 ++
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file changed, 1 insertion
Hi all
This series set the phy_cfg_clk to be a required clock for RK3399, and
add a grf clock control in dw-mipi-dsi driver. And then correct a
register name.
Changes in v2:
- check the grf_clk only for RK3399
Chris Zhong (4):
drm/rockchip/dsi: check phy_cfg_clk only for RK3399
dt-bindings
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drive
For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is
disabled, MIPI phy can not work. Let's return a error if there is no
phy_cfg_clk in dts property, when the pdata match RK3399.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2: None
drivers/gpu/drm/rockc
Hi Heiko
On 03/15/2017 05:03 PM, Heiko Stübner wrote:
Am Mittwoch, 15. März 2017, 16:42:30 CET schrieb Chris Zhong:
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
.../devi
For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20,
not RK3399_GRF_SOC_CON19.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/d
For RK3399, the grf clk should be enabled before writing grf registers,
otherwise the register value can not be changed.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24
1 file changed, 24 insertions(+)
diff
For RK3399, the grf clock should be controlled by dw-mipi-dsi driver,
add the description for this clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2:
- add some error check
- always use Low power mode to send commend
- add comments for all the sleep
- use DRM_DEV_ERROR instead of dev_er
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v2: None
.../bindings/display/panel/innolux,p079zca.txt | 23 ++
1 file changed, 23
Hi Heiko and Brain
On 03/09/2017 09:02 AM, Heiko Stübner wrote:
Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris:
On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote:
There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence
only one PHY can connect to DP
Oh, a slip of the finger :(, the headline should be "RK3399 cdn-dp patches"
On 03/08/2017 10:27 AM, Chris Zhong wrote:
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
dr
Correct some DP register address for PHY Configuration according to
latest datasheet.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp
uot; instead of "u32" is better.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 +++--
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 2 +-
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff
Hi all
This series is to correct some mistakes in clk_get_rate and the register
address. And in order to better develop, adding more prints.
Chris Zhong (3):
drm/rockchip: cdn-dp: return error code when clk_get_rate failed
drm/rockchip: cdn-dp: Correct PHY register address
drm/rockchip
In order to analyze some video config failed, add some useful
printouts.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c
b/drivers/gpu/drm/rockchip/
The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and
connected to DSI using four lanes.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
.../bindings/display/panel/innolux,p079zca.txt | 22 ++
1 file changed, 22 insertions(+)
create
Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI
panel.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-innolux-p079
Hi John
I have test this v4 series on my RK3399 board, it works well, thanks.
Tested-by: Chris Zhong<z...@rock-chips.com>
On 02/24/2017 08:54 PM, John Keeping wrote:
This version is mostly small changes in response to review comments from
Sean and Chris, the details are in the indi
n Paul wrote:
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidth fix" patch back, since we reall
Hi Sean
On 02/21/2017 11:39 PM, Sean Paul wrote:
On Mon, Feb 20, 2017 at 04:02:16PM +0800, Chris Zhong wrote:
Hi all
[Resend this v7 version series, since there are 5 mails have gone missing, last
week]
This version does not change the existing v6 patches, just to add the
"bandwidt
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mip
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
..
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/g
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 inserti
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some panel, it will cause the screen display is not normal, so
increases the badnwidth to 1 / 0.8.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
C
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mip
le/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi
Hi Rob
On 02/16/2017 10:20 AM, Rob Herring wrote:
On Fri, Feb 10, 2017 at 03:44:11PM +0800, Chris Zhong wrote:
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
"dt-bindings: phy:" is the preferred subject prefix.
OK, I will change the header next version.
d
Hi John
On 02/01/2017 03:22 AM, Sean Paul wrote:
On Sun, Jan 29, 2017 at 01:24:42PM +, John Keeping wrote:
Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: John Keeping <j...@metanate.com>
Reviewed-by: Chris Zhong <z...@rock-chips.com>
---
v3:
- A
Hi John
On 02/15/2017 08:39 PM, John Keeping wrote:
On Wed, 15 Feb 2017 11:38:45 +0800, Chris Zhong wrote:
On 01/29/2017 09:24 PM, John Keeping wrote:
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
..
nges in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (7):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
drm/rockchip/dsi: dw-mipi: correct the coding style
drm/rockchip/dsi: remove
Hi John
On 01/17/2017 06:54 PM, John Keeping wrote:
On Tue, 17 Jan 2017 17:31:53 +0800, Chris Zhong wrote:
On 01/16/2017 08:44 PM, John Keeping wrote:
On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
for some
-by: John Keeping <j...@metanate.com>
Reviewed-by: Chris Zhong <z...@rock-chips.com>
---
v3:
- Add Chris' Reviewed-by
Unchanged in v2
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-m
-by: Chris Zhong <z...@rock-chips.com>
---
drivers/phy/phy-rockchip-typec.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/phy-rockchip-typec.c b/drivers/phy/phy-rockchip-typec.c
index 7cfb0f8..1604aaa 100644
--- a/drivers/phy/phy-rockchip-typec.c
+++ b/drivers/phy/phy-ro
driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/g
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-ro
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/ro
driver can distinguish between PHY 0
and PHY 1, and then write the correct register bit.
Chris Zhong (4):
Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY
arm64: dts: rockchip: add rockchip,uphy-dp-sel for Type-C phy
phy: rockchip-typec: support DP phy switch
drm
://patchwork.kernel.org/patch/9544109
Changes in v6:
- no need check phy_cfg_clk before enable/disable
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (6):
dt-bindings: add rk3399
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
..
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/g
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 inserti
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mip
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mip
..@chromium.org>
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 15 +--
drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 +
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/
With atomic modesetting the hardware will be powered off when the
mode_set function is called. We should configure the hardware in the
enable function.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.
-power on, and wait for a while until it is ready to
DPCD communication.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 91 +++---
drivers/gpu/drm/rockchip/cdn-dp-core.h | 1 +
2 files chang
From: Jeffy Chen <jeffy.c...@rock-chips.com>
We're trying to lock mutex when cdn-dp shutdown, so we need to make
sure the mutex is inited in cdn-dp's probe.
Signed-off-by: Jeffy Chen <jeffy.c...@rock-chips.com>
Reviewed-by: Guenter Roeck <gro...@chromium.org>
Reviewed-by: Chri
system crash. replace drm_helper_hpd_irq_event with
drm_kms_helper_hotplug_event, only update cdn-dp status.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Tested-by: Guenter Roeck <gro...@chromium.org>
Reviewed-by: Guenter Roeck <gro...@chromium.org>
---
Changes in v17: None
/firmware/rockchip/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
[seanpaul fixed up some races between the worker and m
/9442141/
https://patchwork.kernel.org/patch/9442151/
Changes in v17:
- Correct the clock check condition
- Correct the coding style
- change LANE_REF_CYC to 0x8000
Chris Zhong (4):
drm/rockchip: cdn-dp: add cdn DP support for rk3399
drm/rockchip: cdn-dp: do not use drm_helper_hpd_irq_event
drm
y: Sean Paul <seanp...@chromium.org>
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v17: None
drivers/gpu/drm/rockchip/cdn-dp-core.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/gpu/drm/rock
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/d
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mip
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/disp
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/D
/patch/9340251
[25/26] https://patchwork.kernel.org/patch/9340127
[26/26] https://patchwork.kernel.org/patch/9340139
Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong
On 02/02/2017 02:12 AM, Sean Paul wrote:
On Tue, Jan 24, 2017 at 10:27:27AM +0800, Chris Zhong wrote:
Hi Sean
On 01/24/2017 01:48 AM, Sean Paul wrote:
On Fri, Jan 20, 2017 at 06:10:49PM +0800, Chris Zhong wrote:
The MIPI DSI do not need check the validity of resolution, the max
resolution
On 01/23/2017 08:49 PM, John Keeping wrote:
Hi Chris,
On Mon, 23 Jan 2017 09:38:54 +0800, Chris Zhong wrote:
On 01/22/2017 12:31 AM, John Keeping wrote:
The multiplication ratio for the PLL is required to be even due to the
use of a "by 2 pre-scaler". Currently we are likely
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.
Reference the power domain incase dw-mipi power down when
in use.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Reviewed-by: Sean Paul <seanp...@chromium.org>
---
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16
1 file
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicet
The dw-mipi-dsi of rk3399 is almost the same as rk3288, the rk3399 has
additional phy config clock.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v4: None
Changes in v3: None
.../devicetree/bindings/disp
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.
Signed-off-by: Chris Zhong <z...@rock-chips.com>
Sign
correct the coding style, according the checkpatch scripts
Signed-off-by: Chris Zhong <z...@rock-chips.com>
---
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 33 -
1 file changed, 16 insertions(+), 17 deletions(-)
diff
/patch/9340251
[25/26] https://patchwork.kernel.org/patch/9340127
[26/26] https://patchwork.kernel.org/patch/9340139
Changes in v4:
- remove the unrelated change
Changes in v3:
- base on John Keeping's patch series
Chris Zhong (6):
dt-bindings: add rk3399 support for dw-mipi-rockchip
drm
Hi Sean
On 01/24/2017 01:48 AM, Sean Paul wrote:
On Fri, Jan 20, 2017 at 06:10:49PM +0800, Chris Zhong wrote:
The MIPI DSI do not need check the validity of resolution, the max
resolution should depend VOP. Hence, remove rk3288_mipi_dsi_mode_valid
here.
Does vop actually enforce this, though
Reviewed-by: Chris Zhong <z...@rock-chips.com>
On 01/22/2017 12:31 AM, John Keeping wrote:
In order to fully reset the state of the MIPI controller we must assert
this reset.
This is slightly more complicated than it could be in order to maintain
compatibility with device trees t
Reviewed-by: Chris Zhong <z...@rock-chips.com>
On 01/22/2017 12:31 AM, John Keeping wrote:
Signed-off-by: John Keeping <j...@metanate.com>
---
Unchanged in v2
---
drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
Hi John
On 01/22/2017 12:31 AM, John Keeping wrote:
The multiplication ratio for the PLL is required to be even due to the
use of a "by 2 pre-scaler". Currently we are likely to end up with an
odd multiplier even though there is an equivalent set of parameters with
an even multiplier.
For
Reviewed-by: Chris Zhong <z...@rock-chips.com>
On 01/22/2017 12:31 AM, John Keeping wrote:
As the documentation for readx_poll_timeout says, we want to use the
specialized macro for readl rather than using the generic version
directly.
Signed-off-by: John Keeping <j...@met
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