On 22.10.2024 12:09 AM, Akhil P Oommen wrote:
> On Mon, Oct 21, 2024 at 11:38:41AM +0200, Konrad Dybcio wrote:
>> On 11.10.2024 10:29 PM, Akhil P Oommen wrote:
>>> ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
>>> the power consumption. In
available for A612. Verified Glmark2 with
> weston.
>
> Some dependencies for the devicetree change are not yet available
> in the mailing lists. I will send it out as a separate patch later.
> ---
Reviewed-by: Konrad Dybcio
Konrad
[...]
> - retu
at it will always suceess, quit if it fail.
>
> Signed-off-by: Sui Jingfeng
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 30.10.2024 8:02 AM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Enable GPU for sa8775p-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Reviewed-by: Dmitry Baryshkov
> ---
On 30.10.2024 8:02 AM, Akhil P Oommen wrote:
> From: Puranam V G Tejaswi
>
> Add gpu and gmu nodes for sa8775p chipset. As of now all
> SKUs have the same GPU fmax, so there is no requirement of
> speed bin support.
>
> Signed-off-by: Puranam V G Tejaswi
> Signed-off-by: Akhil P Oommen
> Revie
On 28.10.2024 11:52 AM, Dmitry Baryshkov wrote:
> On Mon, Oct 28, 2024 at 11:36:15AM +0100, Konrad Dybcio wrote:
>> On 28.10.2024 11:27 AM, Dmitry Baryshkov wrote:
>>> On Mon, 28 Oct 2024 at 12:08, Akhil P Oommen
>>> wrote:
>>>>
>>>> On 10/28
On 28.10.2024 10:52 AM, Akhil P Oommen wrote:
> On 10/28/2024 12:13 AM, Arnd Bergmann wrote:
>> On Sun, Oct 27, 2024, at 18:05, Akhil P Oommen wrote:
>>> Clang-19 and above sometimes end up with multiple copies of the large
>>> a6xx_hfi_msg_bw_table structure on the stack. The problem is that
>>> a
On 28.10.2024 11:27 AM, Dmitry Baryshkov wrote:
> On Mon, 28 Oct 2024 at 12:08, Akhil P Oommen wrote:
>>
>> On 10/28/2024 1:56 PM, Dmitry Baryshkov wrote:
>>> On Sun, Oct 27, 2024 at 11:35:47PM +0530, Akhil P Oommen wrote:
Clang-19 and above sometimes end up with multiple copies of the large
On 15.10.2024 2:07 PM, Jyothi Kumar Seerapu wrote:
> The current GPI driver hardcodes the channel TRE (Transfer Ring Element)
> size to 64. For scenarios requiring high performance with multiple
> messages in a transfer, use Block Event Interrupt (BEI).
> This method triggers interrupt after specif
On 11.10.2024 10:29 PM, Akhil P Oommen wrote:
> ACD a.k.a Adaptive Clock Distribution is a feature which helps to reduce
> the power consumption. In some chipsets, it is also a requirement to
> support higher GPU frequencies. This patch adds support for GPU ACD by
> sending necessary data to GMU an
On 21.10.2024 11:25 AM, Akhil P Oommen wrote:
> On Sat, Oct 19, 2024 at 04:14:13PM +0300, Dmitry Baryshkov wrote:
>> On Sat, Oct 19, 2024 at 03:01:46PM +0530, Akhil P Oommen wrote:
>>> On Fri, Oct 18, 2024 at 03:11:38PM +, Arnd Bergmann wrote:
From: Arnd Bergmann
Clang-19 and ab
On 18.10.2024 12:08 PM, Dmitry Baryshkov wrote:
> On Fri, Oct 18, 2024 at 12:37:01PM +0530, Soutrik Mukhopadhyay wrote:
>> This series adds support for the DisplayPort controller
>> and eDP PHY v5 found on the Qualcomm SA8775P platform.
>>
>> ---
>> v2: Fixed review comments from Dmitry and Bjorn
>
On 5.10.2024 4:38 PM, Jonathan Marek wrote:
> drm_mode_vrefresh() can introduce a large rounding error, avoid it.
>
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_hos
sson
> ---
Not all A6xx targets support PPPT (e.g. A619 on SM6375 - but A619 on SM6350
does..). We already print some error messages when that's the case, I think
this may add one more.
Nonetheless, I think that sticks to the accepted status quo where lacking
PPPT is a bug, so..
Te
setup by firmware).
>
> This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
> bus error"-errors from the GPU.
>
> Introduce a function to allow the msm driver to invoke this call.
>
> Signed-off-by: Bjorn Andersson
> ---
Tested-by: Konrad Dybcio # FP5
Reviewed-by: Konrad Dybcio
Konrad
On 19.09.2024 5:00 PM, Jeffrey Hugo wrote:
> On 9/18/2024 5:41 PM, Konrad Dybcio wrote:
>> On 18.09.2024 5:52 PM, Jeffrey Hugo wrote:
>>> The Sahara protocol has a crashdump functionality. In the hello
>>> exchange, the device can advertise it has a memory dump av
On 18.09.2024 5:52 PM, Jeffrey Hugo wrote:
> The Sahara protocol has a crashdump functionality. In the hello
> exchange, the device can advertise it has a memory dump available for
> the host to collect. Instead of the device making requests of the host,
> the host requests data from the device whi
On 17.09.2024 5:30 PM, Rob Clark wrote:
> On Tue, Sep 17, 2024 at 6:47 AM Konrad Dybcio wrote:
>>
>> On 13.09.2024 9:51 PM, Rob Clark wrote:
>>> From: Rob Clark
>>>
>>> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
>>> devi
On 13.09.2024 9:51 PM, Rob Clark wrote:
> From: Rob Clark
>
> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> devices (x1-85, possibly others), it seems to pass that barrier while
> there are still things in the event completion FIFO waiting to be
> written back to memory.
C
On 17.09.2024 10:12 AM, Soutrik Mukhopadhyay wrote:
>
> On 9/14/2024 2:54 AM, Bjorn Andersson wrote:
>> On Thu, Sep 12, 2024 at 03:34:05PM +0530, Soutrik Mukhopadhyay wrote:
>>> On 9/12/2024 1:32 AM, Bjorn Andersson wrote:
On Wed, Sep 11, 2024 at 03:38:13PM +0530, Soutrik Mukhopadhyay wrote:
On 16.09.2024 10:33 PM, Dmitry Baryshkov wrote:
> On Mon, Sep 16, 2024 at 05:23:55PM GMT, Krzysztof Kozlowski wrote:
>> On Fri, Sep 13, 2024 at 04:07:51PM +0530, Soutrik Mukhopadhyay wrote:
>>> Add compatible string for the supported eDP PHY on sa8775p platform.
>>>
>>> Signed-off-by: Soutrik Mukho
On 13.09.2024 12:37 PM, Soutrik Mukhopadhyay wrote:
> In order to support different HW versions, introduce aux_cfg array
> to move v4 specific aux configuration settings.
>
> Signed-off-by: Soutrik Mukhopadhyay
> ---
> v2: Fixed review comments from Bjorn and Dmitry
> - Made aux_cfg array a
On 9.09.2024 1:25 PM, Dmitry Baryshkov wrote:
> On Mon, 9 Sept 2024 at 13:34, Konrad Dybcio wrote:
>>
>> On 8.09.2024 7:59 PM, Dmitry Baryshkov wrote:
>>> Under some circumstance
>>
>> Under what circumstances?
>>
>> This branch is only taken if the
On 8.09.2024 7:59 PM, Dmitry Baryshkov wrote:
> Under some circumstance
Under what circumstances?
This branch is only taken if there's a .create_private_address_space
callback and it only seems to be there on a[67]xx.
a6xx_create_address_space returns:
- an ERR_PTR if msm_iommu_pagetable_create
From: Konrad Dybcio
A621 is a clear A662 derivative (same lineage as A650), no explosions
or sick features, other than a NoC bug which can stall the GPU..
Add support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 78
From: Konrad Dybcio
This was apparently never done before.. Program the expected values.
This also gets rid of sneakily setting that register through the HWCG
reg list on A690.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 1 -
drivers/gpu/drm/msm/adreno
From: Konrad Dybcio
Store the correct values that we happen to have for some A7xx SKUs in
the GPU info struct and fill out the missing information for A6xx GPUs
based on downstream kernel information.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 18
From: Konrad Dybcio
This register's magic value differs wildly between different GPUs, use
the hardcoded data instead of trying to make some logic out of it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++
1 file changed, 2 insertions(+), 4 dele
Baby A650, needs mesa mr !30253 (or better)
Signed-off-by: Konrad Dybcio
---
Changes in v2:
- Split up the gmu_cgc_mode patches more sensibly and write better
commit messages
- Link to v1:
https://lore.kernel.org/r/20240719-topic-a621-v1-0-850ae5307...@linaro.org
---
Konrad Dybcio (6
From: Konrad Dybcio
A650 family includes A660 family (they've got a big family), A650
itself, and some more A6XX_GEN3 SKUs, all of which should fall into
the same branch of the if-condition. Simplify that.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +--
1
From: Konrad Dybcio
The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 +---
drivers/gpu/drm
On 27.08.2024 10:12 PM, Rob Clark wrote:
> resending with updated Konrad email addr
>
> On Mon, Aug 26, 2024 at 2:09 PM Rob Clark wrote:
>>
>> On Mon, Aug 26, 2024 at 2:07 PM Rob Clark wrote:
>>>
>>> On Fri, Jul 19, 2024 at 3:03 AM Konrad Dybcio
>>
On 2.08.2024 9:47 PM, Dmitry Baryshkov wrote:
> DPU debugging macros need to be converted to a proper drm_debug_*
> macros, however this is a going an intrusive patch, not suitable for a
> fix. Wire DPU_DEBUG and DPU_DEBUG_DRIVER to always use DRM_DEBUG_DRIVER
> to make sure that DPU debugging mess
On 20.08.2024 12:45 PM, Connor Abbott wrote:
> On Tue, Aug 20, 2024 at 11:15 AM Konrad Dybcio wrote:
>>
>> On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
>>> The bv_fence field of rbmemptrs was being used incorrectly as the BV
>>> rptr shadow pointer in some pl
On 20.08.2024 12:16 PM, Konrad Dybcio wrote:
> On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
>> Some userspace changes are necessary so add a flag for userspace to
>> advertise support for preemption.
>>
>> Signed-off-by: Antonino Maniscalco
>> ---
>
&g
On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
> Some userspace changes are necessary so add a flag for userspace to
> advertise support for preemption.
>
> Signed-off-by: Antonino Maniscalco
> ---
Squash this into the "add preemption" patch, or add the flag earlier
(probably the latter, as t
On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
> This patch adds a bit of infrastructure to give the different Adreno
> targets the flexibility to setup the submitqueues per their needs.
>
> Signed-off-by: Sharat Masetty
> ---
This email doesn't exist anymore and doesn't match yours
Konrad
On 15.08.2024 8:26 PM, Antonino Maniscalco wrote:
> The bv_fence field of rbmemptrs was being used incorrectly as the BV
> rptr shadow pointer in some places.
>
> Add a bv_rptr field and change the code to use that instead.
>
> Signed-off-by: Antonino Maniscalco
> ---
> drivers/gpu/drm/msm/adre
On 29.07.2024 2:51 PM, Wolfram Sang wrote:
> The old email address bounced. I found the newer one in MAINTAINERS,
> so update entries accordingly.
>
> Cc: Konrad Dybcio
> Signed-off-by: Wolfram Sang
> ---
Already sent a series of fixups, but thanks for keeping track
https
On 29.07.2024 2:13 PM, Konrad Dybcio wrote:
> On 16.07.2024 1:56 PM, Konrad Dybcio wrote:
>> On 15.07.2024 10:04 PM, Akhil P Oommen wrote:
>>> On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote:
>>>> On recent (SM8550+) Snapdragon platforms, the GPU spe
On 16.07.2024 1:56 PM, Konrad Dybcio wrote:
> On 15.07.2024 10:04 PM, Akhil P Oommen wrote:
>> On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote:
>>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>>> abstracted through SMEM, instead of
On 26.07.2024 1:18 PM, Konrad Dybcio wrote:
> Patch 3 should probably go straight to Rob's dt-bindings tree
>
> Signed-off-by: Konrad Dybcio
> ---
> Konrad Dybcio (3):
> mailmap: Add an entry for Konrad Dybcio
> MAINTAINERS: Update Konrad Dybcio's em
Use my @kernel.org address everywhere.
Signed-off-by: Konrad Dybcio
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9200d953868e..6c7d3951192f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2745,7 +2745,7 @@ F
Use my @kernel.org address everywhere.
Signed-off-by: Konrad Dybcio
---
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml | 2 +-
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml | 2 +-
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
Map my old addresses.
Signed-off-by: Konrad Dybcio
---
.mailmap | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.mailmap b/.mailmap
index e51d76df75c2..d189c6424697 100644
--- a/.mailmap
+++ b/.mailmap
@@ -353,6 +353,8 @@ Kenneth Westfield
Kiran Gunda
Kirill Tkhai
Kishon Vijay
Patch 3 should probably go straight to Rob's dt-bindings tree
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (3):
mailmap: Add an entry for Konrad Dybcio
MAINTAINERS: Update Konrad Dybcio's email address
dt-bindings: Batch-update Konrad Dybcio's e
On 23.07.2024 3:38 PM, Marc Gonzalez wrote:
> On 23/07/2024 15:08, Konrad Dybcio wrote:
>
>> On 23.07.2024 2:57 PM, Marc Gonzalez wrote:
>>
>>> On 23/07/2024 13:45, Konrad Dybcio wrote:
>>>
>>>> On 23.07.2024 11:59 AM, Dmitry Baryshkov wrote:
>&g
On 23.07.2024 2:57 PM, Marc Gonzalez wrote:
> On 23/07/2024 13:45, Konrad Dybcio wrote:
>
>> On 23.07.2024 11:59 AM, Dmitry Baryshkov wrote:
>>
>>> On Tue, 23 Jul 2024 at 12:48, Marc Gonzalez wrote:
>>>
>>>> On 16/07/2024 18:37, Dmitry Baryshkov w
On 23.07.2024 11:59 AM, Dmitry Baryshkov wrote:
> On Tue, 23 Jul 2024 at 12:48, Marc Gonzalez wrote:
>>
>> On 16/07/2024 18:37, Dmitry Baryshkov wrote:
>>
>>> No, that's fine. It is the SMMU issue that Konrad has been asking you
>>> to take a look at.
>>
>> Context:
>>
>> [4.911422] arm-smmu c
On 22.07.2024 8:43 PM, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> A642L (speedbin 0x81) uses index 4, so this commit
> sets the fourth bit for A642L supported opps.
>
> Signed-off-by: Eugene Lepshy
> Signed-off-by: Danila Tikhonov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 22.07.2024 8:43 PM, Danila Tikhonov wrote:
> From: Eugene Lepshy
>
> According to downstream, A642L's speedbin is 129 and uses 4 as index
>
> Signed-off-by: Eugene Lepshy
> Signed-off-by: Danila Tikhonov
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 21.07.2024 11:43 PM, Barnabás Czémán wrote:
> On Sat, Jun 22, 2024 at 1:36 PM Konrad Dybcio
> wrote:
>>
>> On 20.06.2024 11:52 PM, Barnabás Czémán wrote:
>>> From: Otto Pflüger
>>>
>>> Add support for Adreno 306A GPU what is found in MSM8917 S
This was apparently never done before.. Program the expected values.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +++-
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers
A621 is a clear A662 derivative (same lineage as A650), no explosions
or sick features, other than a NoC bug which can stall the GPU..
Add support for it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 78 ++-
drivers/gpu/drm/msm/adreno
This was apparently almost never set on a6xx.. move the existing values
and fill out the remaining ones within the catalog.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 19 ++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++
drivers/gpu/drm
The if-else monster is so unmaintainable that one case is repeated
twice. Get rid of it.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
A650 family includes A660 family (they've got a big family), A650
itself, and some more A6XX_GEN3 SKUs, all of which should fall into
the same branch of the if-condition. Simplify that.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +--
1 file changed, 1 inse
Baby A650, needs mesa mr !30253 (or better)
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (5):
drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check
drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
drm/msm/a6xx: Store gmu_cgc_mode in struct a6xx_info
On 17.07.2024 6:36 PM, Rob Clark wrote:
> From: Rob Clark
>
> In the case of iova fault triggered devcore dumps, include additional
> debug information based on what we think is the current page tables,
> including the TTBR0 value (which should match what we have in
> adreno_smmu_fault_info unles
};
> + };
> };
> };
>
> @@ -3045,6 +3053,96 @@ mdss_dsi1_phy: phy@c996400 {
>
> status = "disabled";
> };
> +
> +
On 15.07.2024 10:04 PM, Akhil P Oommen wrote:
> On Tue, Jul 09, 2024 at 12:45:29PM +0200, Konrad Dybcio wrote:
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add s
gt; In addition those faults can't be recovered from because we use suspend
> and resume to do so (keeping values of those fields again).
>
> Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
> Signed-off-by: Vladimir Lypak
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 30.06.2024 8:36 PM, Caleb Connolly wrote:
> Initial support for USB, UFS, touchscreen, panel, wifi, and bluetooth.
>
> Co-developed-by: Frieder Hannenheim
> Signed-off-by: Frieder Hannenheim
> Signed-off-by: Caleb Connolly
> ---
[...]
> +/delete-node/ &spss_mem;
> +/delete-node/ &cdsp_secu
<1>; /* 1.8V */
Would be nice to get the #defines for this PMIC instead..
> + input-disable;
> + output-enable;
LGTM otherwise
Reviewed-by: Konrad Dybcio
Konrad
erefore do so.
Signed-off-by: Konrad Dybcio
---
There's no fixes tag on purpose, as there doesn't seem to be a good
single commit to blame.
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
drivers/gpu/drm/msm/msm_gpu.c | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1
There is no need to reinvent the wheel for simple read-match-set logic.
Make speedbin discovery and assignment generation independent.
This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
which has no representation in hardware whatshowever.
Signed-off-by: Konrad Dybcio
In preparation for commonizing the speedbin handling code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
b/drivers/gpu/drm/msm/adreno
form something that lets us match OPPs against.
Due to the product code being ignored in the context of Adreno on
production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +-
drivers/gpu/drm/msm/ad
ewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 68ba9aed5506..e3322f6aec13 100644
--- a/d
ld be in order if we want
to land this in the upcoming cycle.
FWIW I preferred the fuses myself..
Signed-off-by: Konrad Dybcio
---
Changes in v5:
- Rebase
- Fix some unhandled cases (Elliot)
- Fix unused variable warning
- Touch up some comments
- Link to v4:
https://lore.kernel.org/r/20240625
On 30.06.2024 12:25 PM, Akhil P Oommen wrote:
> On Tue, Jun 25, 2024 at 08:28:06PM +0200, Konrad Dybcio wrote:
>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>> abstracted through SMEM, instead of being directly available in a fuse.
>>
>> Add s
On 30.06.2024 12:29 PM, Akhil P Oommen wrote:
> On Tue, Jun 25, 2024 at 08:28:09PM +0200, Konrad Dybcio wrote:
>> There is no need to reinvent the wheel for simple read-match-set logic.
>>
>> Make speedbin discovery and assignment generation independent.
>>
>>
On 3.07.2024 7:57 AM, Amirreza Zarrabi wrote:
> Qualcomm TEE hosts Trusted Applications (TAs) and services that run in
> the secure world. Access to these resources is provided using MinkIPC.
> MinkIPC is a capability-based synchronous message passing facility. It
> allows code executing in one dom
On 8.07.2024 2:49 PM, Dmitry Baryshkov wrote:
> On Mon, 8 Jul 2024 at 14:07, Marc Gonzalez wrote:
>>
>> On 05/07/2024 16:34, Dmitry Baryshkov wrote:
[...]
>>> I'm not going to check the math, but it looks pretty close to what we
>>> have for msm8996.
>>
>> What is the consequence of this?
>
> T
On 8.07.2024 5:54 PM, Dzmitry Sankouski wrote:
> вт, 18 июн. 2024 г. в 17:12, Konrad Dybcio :
>>
>>
> ...
>>
>>> gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>;
>>
>> Do you know what these are for?
>>
>
On 28.06.2024 4:39 PM, Barnabás Czémán wrote:
> From: Konrad Dybcio
>
> Add support for MSM8996, which - fun fact - was the SoC that this driver
> (or rather SDE, its downstream origin) was meant for and first tested on.
>
> It has some hardware that differs from the modern
On 28.06.2024 7:31 PM, Elliot Berman wrote:
> On Fri, Jun 28, 2024 at 10:24:52AM -0700, Elliot Berman wrote:
>> On Tue, Jun 25, 2024 at 08:28:06PM +0200, Konrad Dybcio wrote:
>>> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
>>> abstracted thr
On 29.06.2024 3:49 AM, Akhil P Oommen wrote:
> Add the necessary dt nodes for gpu support in X1E80100.
>
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
Konrad
a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
> u32 fence_range_lower, fence_range_upper;
> - u32 chipid, chipid_min = 0;
> + u32 chipid = 0;
The initialization doesn't seem necessary
otherwise:
Reviewed-by: Konrad Dybcio
Konrad
On 29.06.2024 3:49 AM, Akhil P Oommen wrote:
> Add support in drm/msm driver for the Adreno X185 gpu found in
> Snapdragon X1 Elite chipset.
>
> Signed-off-by: Akhil P Oommen
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 27.06.2024 12:32 AM, Rob Clark wrote:
> On Wed, Jun 26, 2024 at 2:38 PM Konrad Dybcio
> wrote:
>>
>> On 26.06.2024 8:43 PM, Rob Clark wrote:
>>> On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen
>>> wrote:
>>>>
>>>> O
On 26.06.2024 11:04 PM, Akhil P Oommen wrote:
> On Mon, Jun 24, 2024 at 03:57:35PM +0200, Konrad Dybcio wrote:
>>
>>
>> On 6/23/24 13:06, Akhil P Oommen wrote:
>>> Add the necessary dt nodes for gpu support in X1E80100.
>>
On 26.06.2024 8:43 PM, Rob Clark wrote:
> On Wed, Jun 26, 2024 at 1:24 AM Akhil P Oommen
> wrote:
>>
>> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote:
>>>
>>>
>>> On 6/23/24 13:06, Akhil P Oommen wrote:
>>>> Add s
On 24.06.2024 3:30 AM, Caleb Connolly wrote:
> Initial support for USB, UFS, touchscreen, panel, wifi, and bluetooth.
>
> Co-developed-by: Frieder Hannenheim
> Signed-off-by: Frieder Hannenheim
> Signed-off-by: Caleb Connolly
> ---
[...]
> +&adsp {
> + status = "okay";
> + firmware-na
7.5.10.1
> msm_dpu ae01000.display-controller: Unknown GPU revision: 67.5.20.1
>
> on SM8450, SM8550 & SM8560.
>
> Fixes: 8ed322f632a9 ("drm/msm/adreno: Split up giant device table")
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Konrad Dybcio
Konrad
On 26.06.2024 10:24 AM, Akhil P Oommen wrote:
> On Mon, Jun 24, 2024 at 03:53:48PM +0200, Konrad Dybcio wrote:
>>
>>
>> On 6/23/24 13:06, Akhil P Oommen wrote:
>>> Add support in drm/msm driver for the Adreno X185 gpu found in
>>> Snapdragon X1 Elite chipset
read back).
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
erted no
longer necessary.
Get rid of it.
This reverts commit b77532803d11f2b03efab2ebfd8c0061cd7f8b30.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a
30 by trying to write to non-existent GBIF
Link to v1:
https://lore.kernel.org/linux-arm-msm/20240508-topic-adreno-v1-1-1babd05c1...@linaro.org/
Signed-off-by: Konrad Dybcio
---
Konrad Dybcio (2):
drm/msm/adreno: De-spaghettify the use of memory barriers
Revert "drm/msm/a6xx: Pol
There is no need to reinvent the wheel for simple read-match-set logic.
Make speedbin discovery and assignment generation independent.
This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx,
which has no representation in hardware whatshowever.
Signed-off-by: Konrad Dybcio
Add the speedbin masks to ensure only the desired OPPs are available on
chips of a given bin.
Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 -
1
In preparation for commonizing the speedbin handling code.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c
b/drivers/gpu/drm/msm/adreno
ewed-by: Dmitry Baryshkov
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 53e33ff78411..8f280d69ba71 100644
--- a/d
form something that lets us match OPPs against.
Due to the product code being ignored in the context of Adreno on
production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN.
Signed-off-by: Konrad Dybcio
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++---
drivers/gpu/drm/msm/ad
ld be in order if we want
to land this in the upcoming cycle.
FWIW I preferred the fuses myself..
Signed-off-by: Konrad Dybcio
---
Changes in v4:
- Drop applied qcom patches
- Make the fuse/speedbin fields u16 again (as Pcode is unused)
- Add comments explaining why there's only speedbin0
On 25.06.2024 7:21 PM, Rob Clark wrote:
> On Wed, Jun 5, 2024 at 1:10 PM Konrad Dybcio wrote:
>>
>> Add speebin data for A740, as found on SM8550 and derivative SoCs.
>>
>> Reviewed-by: Dmitry Baryshkov
>> Signed-off-by: Konrad Dybcio
>> ---
>> d
On 25.06.2024 7:20 PM, Rob Clark wrote:
> On Wed, Jun 5, 2024 at 1:10 PM Konrad Dybcio wrote:
>>
[...]
>> struct adreno_speedbin {
>> - uint16_t fuse;
>> + /* <= 16-bit for NVMEM fuses, 32b for SOCID values */
>> + uint32_t fuse;
>>
On 6/23/24 21:34, Krzysztof Kozlowski wrote:
Commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") re-used
amd,imageon compatible for the SM8150 just to enable headless mode due
to missing display controller nodes. This work-around was later
narrowed to the SM8150 MTP board in commit
On 6/23/24 13:06, Akhil P Oommen wrote:
Add the necessary dt nodes for gpu support in X1E80100.
Signed-off-by: Akhil P Oommen
---
[...]
+
+ opp-11 {
+ opp-hz = /bits/ 64 <11>;
+
1 - 100 of 1242 matches
Mail list logo
