On 21.04.2024 04:10, Dharma Balasubiramani wrote:
> Enable LVDS serializer support for display pipeline.
>
> Signed-off-by: Dharma Balasubiramani
> Acked-by: Hari Prasath Gujulan Elango
> Acked-by: Nicolas Ferre
Applied to at91-defconfig, thanks!
driver ops
> drm: atmel-hlcdc: add DPI mode support for XLCDC
> drm: atmel-hlcdc: add vertical and horizontal scaling support for
> XLCDC
> drm: atmel-hlcdc: add support for DSI output formats
> drm: atmel-hlcdc: add LCD controller layer definition for sam9x75
>
Only minor comments from me (check individual patches). W/ or w/o those
addressed you can add:
Reviewed-by: Claudiu Beznea
On 21.02.2024 07:35, Manikandan Muralidharan wrote:
> Add XLCDC specific driver ops and is_xlcdc flag to separate the
> functionality and to access the controller registers.
> HEO scaling, window resampling, Alpha blending, YUV-to-RGB
> conversion in XLCDC is derived and handled using
On 21.02.2024 07:35, Manikandan Muralidharan wrote:
> Add support for the following DPI mode if the encoder type
> is DSI as per the XLCDC IP datasheet:
> - 16BPPCFG1
> - 16BPPCFG2
> - 16BPPCFG3
> - 18BPPCFG1
> - 18BPPCFG2
> - 24BPP
>
> Signed-off-by: Manikandan Muralidharan
>
On 21.02.2024 07:35, Manikandan Muralidharan wrote:
> Add LCD IP specific ops in driver data to differentiate
> HLCDC and XLCDC code within the atmel-hlcdc driver files.
> XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP.
On 29.01.2024 11:23, Manikandan Muralidharan wrote:
> Add support for the following DPI mode if the encoder type
> is DSI as per the XLCDC IP datasheet:
> - 16BPPCFG1
> - 16BPPCFG2
> - 16BPPCFG3
> - 18BPPCFG1
> - 18BPPCFG2
> - 24BPP
>
> Signed-off-by: Manikandan Muralidharan
>
On 29.01.2024 11:23, Manikandan Muralidharan wrote:
> XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP. Read/write
> operation on the controller registers is now separated using the
> XLCDC status flag and with HLCDC and
Hi, Manikandan,
On 29.01.2024 11:23, Manikandan Muralidharan wrote:
> Add is_xlcdc flag and LCD IP specific ops in driver data to differentiate
> XLCDC and HLCDC code within the atmel-hlcdc driver files.
I would first prepare the current code base for the addition of XLCDC by
first adding the
On 29.01.2024 11:23, Manikandan Muralidharan wrote:
> Add the LCD controller layer definition and descriptor structure for
> sam9x75 for the following layers:
> - Base Layer
> - Overlay1 Layer
> - Overlay2 Layer
> - High End Overlay
>
> Signed-off-by: Manikandan Muralidharan
> ---
>
On 03.10.2023 07:18, manikanda...@microchip.com wrote:
> On 28/09/23 11:31 am, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> Hi, Manikandan,
>>
>> On 27.09.2023 12:47, M
+const struct atmel_hlcdc_layer_desc *desc);
> +void xlcdc_irq_dbg(struct atmel_hlcdc_plane *plane,
> +const struct atmel_hlcdc_layer_desc *desc);
> +
These are still here... Isn't the solution I proposed to you in the
previous version good enough?
Thank you,
Claudiu Beznea
On 15.09.2023 13:48, Manikandan Muralidharan wrote:
> - XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP. Read/write
> operation on the controller registers is now separated using the
> XLCDC status flag and with HLCDC and
On 15.09.2023 13:48, Manikandan Muralidharan wrote:
> From: Durai Manickam KR
>
> The register address of the XLCDC IP used in SAM9X7 SoC family
> are different from the previous HLCDC.Defining those address
Add a space after .
> space with valid macros.
>
> Signed-off-by: Durai Manickam
On 15.09.2023 13:48, Manikandan Muralidharan wrote:
> Add the LCD controller layer definition and descriptor structure for
> sam9x75 for the following layers,
s/,/:
> - Base Layer
> - Overlay1 Layer
> - Overlay2 Layer
> - High End Overlay
>
> Signed-off-by: Manikandan Muralidharan
> ---
>
On 15.09.2023 13:48, Manikandan Muralidharan wrote:
> Add support for Display Pixel Interface (DPI) Compatible Mode
> support in atmel-hlcdc driver for XLCDC IP along with legacy
> pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register.
Space after .
>
> Signed-off-by: Manikandan
On 12.09.2023 13:44, manikanda...@microchip.com wrote:
> On 09/09/23 9:50 pm, claudiu beznea wrote:
>> [You don't often get email from claudiu.bez...@tuxon.dev. Learn why this is
>> important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> EXTERNAL EMAIL:
Hi, Manikandan,
On 8/25/23 15:54, Manikandan Muralidharan wrote:
> - XLCDC in SAM9X7 has different sets of registers and additional
> configuration bits when compared to previous HLCDC IP. Read/write
> operation on the controller registers is now separated using the
> XLCDC status flag.
> -
On 8/25/23 15:54, Manikandan Muralidharan wrote:
> update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which
s/update/Update
> supports vertical and horizontal scaling with Bilinear and Bicubic
> co-efficients taps for Chroma and Luma componenets of the Pixel.
>
> Signed-off-by:
On 8/25/23 15:54, Manikandan Muralidharan wrote:
> Add support for Display Pixel Interface (DPI) Compatible Mode
> support in atmel-hlcdc driver for XLCDC IP along with legacy
> pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register.
>
> Signed-off-by: Manikandan Muralidharan
>
On 8/25/23 15:54, Manikandan Muralidharan wrote:
> From: Durai Manickam KR
>
> The register address of the XLCDC IP used in SAM9X7 SoC family
> are different from the previous HLCDC.Defining those address
> space with valid macros.
>
> Signed-off-by: Durai Manickam KR
>
On 8/25/23 15:54, Manikandan Muralidharan wrote:
> Add support for the following DPI mode if the encoder type
> is DSI as per the XLCDC IP datasheet:
> - 16BPPCFG1
> - 16BPPCFG2
> - 16BPPCFG3
> - 18BPPCFG1
> - 18BPPCFG2
> - 24BPP
>
> Signed-off-by: Manikandan Muralidharan
>
devm_kzalloc() can fail and return NULL pointer. Check its return status.
Identified with Coccinelle (kmerr.cocci script).
Fixes: 484e72d3146b ("drm/stm: ltdc: add support of ycbcr pixel formats")
Signed-off-by: Claudiu Beznea
---
Hi,
This has been addressed using kmerr.cocci scrip
Add struct device member to struct atmel_hlcdc_regmap to be
able to use dev_*() specific logging functions.
Signed-off-by: Claudiu Beznea
Acked-for-MFD-by: Lee Jones
---
drivers/mfd/atmel-hlcdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd
around and
actually prefers the higher frequency. Fix that.
Fixes: f6f7ad323461 ("drm/atmel-hlcdc: allow selecting a higher pixel-clock
than requested")
Reported-by: Claudiu Beznea
Tested-by: Claudiu Beznea
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |
Doubled system clock should be used as pixel cock source only if this
is supported. This is emphasized by the value of
atmel_hlcdc_crtc::dc::desc::fixed_clksrc.
Fixes: a6eca2abdd42 ("drm: atmel-hlcdc: add config option for clock selection")
Signed-off-by: Claudiu Beznea
---
drive
For HLCDC timing engine configurations bit ATMEL_HLCDC_SIP of
ATMEL_HLCDC_SR needs to be polled before applying new config. In case of
timeout there is no indicator about this, so, return in case of timeout
and also print a message about this.
Signed-off-by: Claudiu Beznea
Acked-for-MFD-by: Lee
Hi,
I have few fixes for atmel-hlcdc driver in this series as well
as two reverts.
Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
due to the fix in in patch 2/5.
Thank you,
Claudiu Beznea
Changes in v3:
- changes dev_err() message in patch 4/6
- collect Ack
enabled pixel clock source before doing any changes on timing
enginge (only SAM9X60 datasheet specifies that the peripheral clock and
pixel clock must be enabled before using LCD controller).
Fixes: 1a396789f65a ("drm: add Atmel HLCDC Display Controller support")
Signed-off-by: Clau
Mallikarjun
Signed-off-by: Claudiu Beznea
---
Hi Sam,
I still kept this as a patch as I didn't got any answer from you at my
last email up to this moment.
If you think it is better to squash this one with patch 2/6 in this seris
let me know.
Thank you,
Claudiu Beznea
drivers/gpu/drm/atmel-hl
Mallikarjun
Signed-off-by: Claudiu Beznea
---
Hi Sam,
I still kept this as a patch as I didn't got any answer from you at my
last email up to this moment.
If you think it is better to squash this one with patch 2/6 in this seris
let me know.
Thank you,
Claudiu Beznea
drivers/gpu/drm/atmel-hl
Add struct device member to struct atmel_hlcdc_regmap to be
able to use dev_*() specific logging functions.
Signed-off-by: Claudiu Beznea
---
drivers/mfd/atmel-hlcdc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
index 64013c57a920
enabled pixel clock source before doing any changes on timing
enginge (only SAM9X60 datasheet specifies that the peripheral clock and
pixel clock must be enabled before using LCD controller).
Fixes: 1a396789f65a ("drm: add Atmel HLCDC Display Controller support")
Signed-off-by: Clau
Doubled system clock should be used as pixel cock source only if this
is supported. This is emphasized by the value of
atmel_hlcdc_crtc::dc::desc::fixed_clksrc.
Fixes: a6eca2abdd42 ("drm: atmel-hlcdc: add config option for clock selection")
Signed-off-by: Claudiu Beznea
---
drive
Hi,
I have few fixes for atmel-hlcdc driver in this series as well
as two reverts.
Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
due to the fix in in patch 2/5.
Thank you,
Claudiu Beznea
Changes in v2:
- introduce patch 3/6
- use dev_err() inpatch 4/6
- introduce
For HLCDC timing engine configurations bit ATMEL_HLCDC_SIP of
ATMEL_HLCDC_SR needs to be polled before applying new config. In case of
timeout there is no indicator about this, so, return in case of timeout
and also print a message about this.
Signed-off-by: Claudiu Beznea
---
drivers/mfd/atmel
around and
actually prefers the higher frequency. Fix that.
Fixes: f6f7ad323461 ("drm/atmel-hlcdc: allow selecting a higher pixel-clock
than requested")
Reported-by: Claudiu Beznea
Tested-by: Claudiu Beznea
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |
This reverts commit f6f7ad3234613f6f7f27c25036aaf078de07e9b0.
("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested")
because allowing selecting a higher pixel clock may overclock
LCD devices, not all of them being capable of this.
Cc: Peter Rosin
Signed-off-by: Clau
Doubled system clock should be used as pixel cock source only if this
is supported. This is emphasized by the value of
atmel_hlcdc_crtc::dc::desc::fixed_clksrc.
Fixes: a6eca2abdd42 ("drm: atmel-hlcdc: add config option for clock selection")
Signed-off-by: Claudiu Beznea
---
drive
() and also print a message about this.
Signed-off-by: Claudiu Beznea
---
drivers/mfd/atmel-hlcdc.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
index 64013c57a920..19f1dbeb8bcd 100644
--- a/drivers/mfd
Hi,
I have few fixes for atmel-hlcdc driver in this series as well
as two reverts.
Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
due to the fix in in patch 2/5.
Thank you,
Claudiu Beznea
Claudiu Beznea (5):
drm: atmel-hlcdc: use double rate for pixel
Mallikarjun
Signed-off-by: Claudiu Beznea
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 8dc917a1270b.
enabled pixel clock source before doing any changes on timing
enginge (only SAM9X60 datasheet specifies that the peripheral clock and
pixel clock must be enabled before using LCD controller).
Fixes: 1a396789f65a ("drm: add Atmel HLCDC Display Controller support")
Signed-off-by: Clau
On 28.02.2018 21:44, Thierry Reding wrote:
> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>> were adapted to this change.
>>
>> Signed-off-by: Claudiu Beznea &l
Regarding the models to switch on atomic PWM, on the controller side you
can check for drivers that registers apply function at probe time.
Regarding the PWM users, you can look for pwm_apply_state()
(drivers/hwmon/pwm-fan.c or drivers/input/misc/pwm-beeper.c are some examples).
Thierry, ple
On 27.02.2018 17:38, Daniel Thompson wrote:
> On Tue, Feb 27, 2018 at 01:40:58PM +0200, Claudiu Beznea wrote:
>> On 27.02.2018 12:54, Daniel Thompson wrote:
>>> On Mon, Feb 26, 2018 at 04:24:15PM +0200, Claudiu Beznea wrote:
>>>> On 26.02.2018 11:57, Jani Nikula wr
On 27.02.2018 12:54, Daniel Thompson wrote:
> On Mon, Feb 26, 2018 at 04:24:15PM +0200, Claudiu Beznea wrote:
>> On 26.02.2018 11:57, Jani Nikula wrote:
>>> On Thu, 22 Feb 2018, Daniel Thompson <daniel.thomp...@linaro.org> wrote:
>>>> On Thu, Feb 22, 2018
On 26.02.2018 11:57, Jani Nikula wrote:
> On Thu, 22 Feb 2018, Daniel Thompson <daniel.thomp...@linaro.org> wrote:
>> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>>
I'll rebase it on latest for-next in next version.
Thank you,
Claudiu Beznea
On 24.02.2018 22:49, kbuild test robot wrote:
> Hi Claudiu,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on pwm/for-next]
> [also build test WARNING
m/pwmchip0/pwm2# cat mode
[normal] complementary push-pull
The PWM push-pull mode could be usefull in applications like half bridge
converters.
This series also add support for PWM modes on Atmel/Microchip SoCs.
Thank you,
Claudiu Beznea
[1] https://www.spinics.net/lists/arm-kernel/msg580275.html
Add documentation for PWM push-pull mode.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/pwm/pwm.txt | 2 ++
Documentation/pwm.txt | 16
include
Add push-pull mode support. In push-pull mode the channels' outputs have
same polarities and the edges are complementary delayed for one period.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
include/linux/pwm.h | 9 -
1 file changed, 8 insertions(+), 1 de
On 22.02.2018 15:01, Sean Young wrote:
> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>> were adapted to this change.
>>
>> Signed-off-by: Claudiu Beznea &l
Add pwm capabilities for Atmel/Microchip PWM controllers.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
drivers/pwm/pwm-atmel.c | 80 -
1 file changed, 52 insertions(+), 28 deletions(-)
diff --git a/drivers/pwm/pwm-atm
odes could be located in
include/dt-bindings/pwm/pwm.h. Only modes supported by PWM channel could be
set. If nothing is specified for a PWM channel, via DT, the first available
mode will be used (normally, this will be PWM normal mode).
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
Populate PWM mode in of_xlate function to avoid pwm_apply_state() failure.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
drivers/pwm/pwm-pxa.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 4143a46684d2..7a0357
Populate PWM mode in of_xlate function to avoid pwm_apply_state() failure.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
drivers/pwm/pwm-clps711x.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/p
Add support for PWM push-pull mode. This is only supported by SAMA5D2 SoCs.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
drivers/pwm/pwm-atmel.c | 40
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/p
On 22.02.2018 19:28, Andy Shevchenko wrote:
> On Thu, Feb 22, 2018 at 2:01 PM, Claudiu Beznea
> <claudiu.bez...@microchip.com> wrote:
>> Add PWM normal and complementary modes.
>
>> +- PWM_DTMODE_COMPLEMENTARY: PWM complementary working mode (for PWM
>> +channe
Add PWM normal and complementary modes.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
Documentation/devicetree/bindings/pwm/pwm.txt | 9 +++--
Documentation/pwm.txt | 26 +++---
include/dt-bindings/pwm/pwm.h
On 22.02.2018 14:33, Daniel Thompson wrote:
> On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote:
>> Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
>> were adapted to this change.
>>
>> Signed-off-by: Claudiu Beznea &l
Populate PWM mode in of_xlate function to avoid pwm_apply_state() failure.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
drivers/pwm/pwm-cros-ec.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c
index 9c1369
Add PWM mode to pwm_config() function. The drivers which uses pwm_config()
were adapted to this change.
Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
arch/arm/mach-s3c24xx/mach-rx1950.c | 11 +--
drivers/bus/ts-nbus.c| 2 +-
drivers/clk/clk
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