On Fri, May 12, 2023 at 4:02 PM Marek Szyprowski
wrote:
>
> On 12.05.2023 22:00, Adam Ford wrote:
> > On Fri, May 12, 2023 at 2:37 PM Lucas Stach wrote:
> >> Am Samstag, dem 06.05.2023 um 14:24 -0500 schrieb Adam Ford:
> >>> The DPHY timings are currently hard coded. Since the input
> >>> clock
On Fri, 2023-04-28 at 11:58 -0700, Ceraolo Spurio, Daniele wrote:
> Before we add the second step of the MTL HuC auth (via GSC), we need to
> have the ability to differentiate between them. To do so, the huc
> authentication check is duplicated for GuC and GSC auth, with meu
> binaries being
On Fri, 12 May 2023 16:56:03 -0700, Vinay Belgaumkar wrote:
>
Hi Vinay,
> rps_boost debugfs shows host turbo related info. This is not valid
> when SLPC is enabled.
A couple of thoughts about this. It appears people are know only about
rps_boost_info and don't know about guc_slpc_info? So:
a.
On Tue, 2023-05-02 at 08:27 -0700, Ceraolo Spurio, Daniele wrote:
> The new binaries that support the 2-step authentication have contain the
> legacy-style binary, which we can use for loading the HuC via DMA. To
> find out where this is located in the image, we need to parse the meu
> manifest of
On MTL, if the GSC Proxy init flows haven't completed, submissions to the
GSC engine will fail. Those init flows are dependent on the mei's
gsc_proxy component that is loaded in parallel with i915 and a
worker that could potentially start after i915 driver init is done.
That said, all subsytems
rps_boost debugfs shows host turbo related info. This is not valid
when SLPC is enabled. guc_slpc_info already shows the number of boosts.
Add num_waiters there as well and disable rps_boost when SLPC is
enabled.
Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7632
Signed-off-by: Vinay
> On 2023-05-10 15:14:16, Andi Shyti wrote:
>> Hi,
>>
>> On Tue, May 09, 2023 at 09:59:42AM -0700, fei.y...@intel.com wrote:
>>> From: Fei Yang
>>>
>>> To comply with the design that buffer objects shall have immutable
>>> cache setting through out their life cycle, {set, get}_caching ioctl's
>>>
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.
This series is focusing on uAPI changes,
1. end support for set caching ioctl
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
("drm/msm/dpu: get INTF blocks directly rather than through RM") the hw
resources struct was removed, leaving
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
As the debugfs is fully cleared on drm device removal, drop the
encoder-specific cleanup function, remove debugfs_root from dpu_encoder
struct and also remove phys_encoder late_register() ops which has been
unused since the driver being added.
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
Do we need to have a fixes tag for this? This means we dont consider
rotation while calculating src
On Fri, May 12, 2023 at 03:11:35PM +0200, Neil Armstrong wrote:
> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
> (ver 1.21a),
> with a custom glue managing the IP resets, clock and data input similar to
> the DW-HDMI Glue
> on the same Amlogic SoCs.
>
>
The current dpu_hw_dsc calculation for det_thresh_flatness does not
match the downstream calculation or the DSC spec.
Use the DRM DSC helper for det_thresh_flatness to match downstream
implementation and the DSC spec.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by:
Correct the math for slice_last_group_size so that it matches the
calculations downstream.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5
Use MSM and DRM DSC helper methods to configure DSC for DSI.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
hdisplay for compressed images should be calculated as bytes_per_slice *
slice_count. Thus, use MSM DSC helper to calculate hdisplay for
dsi_timing_setup instead of directly using mode->hdisplay.
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
From: Dmitry Baryshkov
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
There are some overlap in calculations for MSM-specific DSC variables
between DP and DSI. In addition, the calculations for initial_scale_value
and det_thresh_flatness that are defined within the DSC 1.2 specifications,
but aren't yet included in drm_dsc_helper.c.
This series moves these
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/msm_dsc_helper.h | 65
1 file changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h
From: Dmitry Baryshkov
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
Add helpers to calculate det_thresh_flatness and initial_scale_value as
these calculations are defined within the DSC spec.
Reviewed-by: Marijn Suijten
Signed-off-by: Jessica Zhang
---
include/drm/display/drm_dsc_helper.h | 10 ++
1 file changed, 10 insertions(+)
diff --git
On Thu, May 11, 2023 at 7:33 PM Dmitry Osipenko <
dmitry.osipe...@collabora.com> wrote:
> On 5/12/23 03:17, Gurchetan Singh wrote:
> ...
> > Can we get one of the Mesa MRs reviewed first? There's currently no
> > virtio-intel MR AFAICT, and the amdgpu one is marked as "Draft:".
> >
> > Even for
On 12/05/2023 23:48, Kuogee Hsieh wrote:
On 5/12/2023 11:19 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off"
On 12.05.2023 22:00, Adam Ford wrote:
> On Fri, May 12, 2023 at 2:37 PM Lucas Stach wrote:
>> Am Samstag, dem 06.05.2023 um 14:24 -0500 schrieb Adam Ford:
>>> The DPHY timings are currently hard coded. Since the input
>>> clock can be variable, the phy timings need to be variable
>>> too. Add an
On 5/12/2023 11:19 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but
not
used at
On Fri, 12 May 2023 02:33:33 -0700, Andi Shyti wrote:
>
Hi Andi,
>
> On Thu, May 11, 2023 at 10:43:30AM -0700, Dixit, Ashutosh wrote:
> > On Wed, 10 May 2023 11:36:06 -0700, Ashutosh Dixit wrote:
> > >
> > > Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
> > > causes the
Loading i915 on UBSAN enabled kernels (CONFIG_UBSAN/CONFIG_UBSAN_BOOL)
causes the following warning:
UBSAN: invalid-load in drivers/gpu/drm/i915/gt/uc/intel_uc.c:558:2
load of value 255 is not a valid value for type '_Bool'
Call Trace:
dump_stack_lvl+0x57/0x7d
ubsan_epilogue+0x5/0x40
On Fri, May 12, 2023 at 2:37 PM Lucas Stach wrote:
>
> Hi Adam,
>
> Am Samstag, dem 06.05.2023 um 14:24 -0500 schrieb Adam Ford:
> > The DPHY timings are currently hard coded. Since the input
> > clock can be variable, the phy timings need to be variable
> > too. Add an additional variable to
On 2023-05-10 15:14:16, Andi Shyti wrote:
> Hi,
>
> On Tue, May 09, 2023 at 09:59:42AM -0700, fei.y...@intel.com wrote:
> > From: Fei Yang
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> >
Hi Adam,
Am Samstag, dem 06.05.2023 um 14:24 -0500 schrieb Adam Ford:
> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too. Add an additional variable to the driver data to enable
> this feature to prevent breaking boards
On 5/12/2023 11:50 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:47, Abhinav Kumar wrote:
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from
On 12/05/2023 21:47, Abhinav Kumar wrote:
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both
On Fri, 12 May 2023 at 21:03, Stephen Boyd wrote:
>
> Quoting Dmitry Baryshkov (2023-05-11 17:54:19)
> > On Fri, 12 May 2023 at 03:16, Kuogee Hsieh wrote:
> > > 1) DP with GPIO: No downstream drm_bridge are connected, is_edp = false
> > > and internal HPD-logic is in used (internal_hpd = true).
https://bugzilla.kernel.org/show_bug.cgi?id=217432
Artem S. Tashkinov (a...@gmx.com) changed:
What|Removed |Added
Status|NEW |RESOLVED
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes
On 12/05/2023 21:00, Kuogee Hsieh wrote:
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the
On 28/04/2023 02:28, Abhinav Kumar wrote:
On sc7280 where eDP is the primary display, PSR is causing
IGT breakage even for basic test cases like kms_atomic and
kms_atomic_transition. Most often the issue starts with below
stack so providing that as reference
Call trace:
Quoting Dmitry Baryshkov (2023-05-11 17:54:19)
> On Fri, 12 May 2023 at 03:16, Kuogee Hsieh wrote:
> > 1) DP with GPIO: No downstream drm_bridge are connected, is_edp = false
> > and internal HPD-logic is in used (internal_hpd = true). Power needs to
> > be on at all times etc.
> >
> > 2) DP
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual hard slice DSC encoders so both share same base address but with
its own different sub block address.
changes in v4:
--
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both per
DSC engine and DSC flush bits at same time to make it consistent with
the location of flush
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
For completeness, this patch adds DSC blocks for platforms which missed
them.
Signed-off-by: Abhinav Kumar
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]:
On 11/05/2023 20:53, Kuogee Hsieh wrote:
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes
On Fri, May 12, 2023 at 02:14:19PM +0300, Andy Shevchenko wrote:
On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
masks for fixed-width types and also the corresponding BIT_U32(),
BIT_U16() and BIT_U8().
Why?
Hi Thomas,
kernel test robot noticed the following build errors:
[auto build test ERROR on 451e49cfbaa90720149e63f4fa9c7824013c783d]
url:
https://github.com/intel-lab-lkp/linux/commits/Thomas-Zimmermann/drm-armada-Use-regular-fbdev-I-O-helpers/20230512-164432
base
Hi!
> > Am 04.04.23 um 06:01 schrieb Sui Jingfeng:
> >> EFI FB, VESA FB or VGA FB etc are belong to firmware based framebuffer
> >> driver.
> >
>
...
> I fixed that before applying, also removed the "are" in the sentence
> above, since it sounded off and repharsed subject line as "Fix typos
https://bugzilla.kernel.org/show_bug.cgi?id=217432
--- Comment #4 from Jonny Mako (jhnmlkv...@gmail.com) ---
Kernel version 6.3.1-arch2-1 #1 SMP PREEMPT_DYNAMIC Wed, 10 May 2023 08:54:47
+ x86_64 GNU/Linux
--
You may reply to this email to add a comment.
You are receiving this mail
On Thu, 06 Apr 2023 19:06:30 +0300, Dmitry Osipenko wrote:
> This patchset makes dma-buf exporters responisble for taking care of
> the reservation lock. I also included patch that moves drm-shmem to use
> reservation lock, to let CI test the whole set. I'm going to take all
> the patches via
Hi
Am 12.05.23 um 15:20 schrieb Linus Walleij:
Sorry for late regression detection but this patch regresses
the Integrator AB IMPD-1 graphics, I bisected down to this
patch.
[...]
This is the driver:
drivers/gpu/drm/pl111/pl111_versatile.c
with the pl110_impd1 variant, so these are the
On 5/12/23 03:04, Jiapeng Chong wrote:
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:586:37-39: WARNING !A || A
&& B is equivalent to !A || B.
./drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c:595:37-39: WARNING !A || A
&& B is equivalent to !A || B.
Reported-by: Abaci Robot
Link:
https://bugzilla.kernel.org/show_bug.cgi?id=217432
--- Comment #3 from Alex Deucher (alexdeuc...@gmail.com) ---
The patch was cc'ed to stable as well, so it should land there soon.
--
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https://bugzilla.kernel.org/show_bug.cgi?id=217432
Bagas Sanjaya (bagasdo...@gmail.com) changed:
What|Removed |Added
CC|
[Public]
> -Original Message-
> From: Thomas Zimmermann
> Sent: Friday, May 12, 2023 4:42 AM
> To: dan...@ffwll.ch; airl...@gmail.com; maarten.lankho...@linux.intel.com;
> mrip...@kernel.org; javi...@redhat.com
> Cc: dri-devel@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org;
On Fri, May 12, 2023 at 02:02:31PM +0200, Javier Martinez Canillas wrote:
> This is a leftover from an early iteration of the driver when it was still
> named ssd1307 instead of ssd130x. Change it for consistency with the rest.
>
> Signed-off-by: Javier Martinez Canillas
Reviewed-by: Sam
Hi Thomas,
> >
> > Nice cleanup.
> >
> > From one of the patches:
> >
> > > +config DRM_ARMADA_FBDEV_EMULATION
> > > + bool
> > > + depends on DRM_ARMADA
> > > + select FB_CFB_COPYAREA
> > > + select FB_CFB_FILLRECT
> > > + select FB_CFB_IMAGEBLIT
> >
> > This seems like a
https://bugzilla.kernel.org/show_bug.cgi?id=217432
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC|
On Fri, May 12, 2023 at 6:07 AM Bagas Sanjaya wrote:
> diff --git a/fs/udf/ecma_167.h b/fs/udf/ecma_167.h
> index de17a97e866742..b2b5bca45758df 100644
> --- a/fs/udf/ecma_167.h
> +++ b/fs/udf/ecma_167.h
> @@ -1,3 +1,4 @@
> +/* SPDX-License-Identifier: BSD-2-Clause OR GPL-1.0+ */
> /*
> *
Sorry for late regression detection but this patch regresses
the Integrator AB IMPD-1 graphics, I bisected down to this
patch.
On Mon, Jan 2, 2023 at 12:30 PM Thomas Zimmermann wrote:
> Fix the color-format selection of the single-probe helper. Go
> through all user-specified values and test
On Thu 11-05-23 20:34:05, Bagas Sanjaya wrote:
> Except Kconfig and Makefile, all source files for UDF filesystem doesn't
> bear SPDX license identifier. Add appropriate license identifier while
> replacing boilerplates.
>
> Cc: Thomas Gleixner
> Signed-off-by: Bagas Sanjaya
> ---
>
This add nodes to support the Khadas TS050 panel on the
Khadas VIM3 & VIM3L boards.
Signed-off-by: Neil Armstrong
---
.../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 76 ++
Add the MIPI DSI Analog & Digital PHY nodes and the DSI control
nodes with proper port endpoint to the VPU.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 +++
1 file changed, 70 insertions(+)
diff --git
This updates the panel timings to achieve a clean 60Hz refresh rate.
Link:
https://lore.kernel.org/r/20221025-ts050-timings-v1-1-5c824bbb2...@linaro.org
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/panel/panel-khadas-ts050.c | 16
1 file changed, 8 insertions(+), 8
The Amlogic G12A/G12B/SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver
1.21a),
with a custom glue managing the IP resets, clock and data input similar to the
DW-HDMI
Glue on other Amlogic SoCs.
This adds support for the Glue managing the transceiver, mimicing the init flow
provided
by
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
(ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the
DW-HDMI Glue
on the same Amlogic SoCs.
Signed-off-by: Neil Armstrong
Signed-off-by: Neil Armstrong
---
This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on
the
Amlogic AXG, G12A, G12B & SM1 SoCs.
Signed-off-by: Neil Armstrong
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_registers.h | 25
drivers/gpu/drm/meson/meson_venc.c | 211
Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported
fixing timings issues.
Fixes: 2a56dc650e54 ("phy: amlogic: Add G12A Analog MIPI D-PHY driver")
Signed-off-by: Neil Armstrong
---
drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c | 2 +-
1 file changed, 1 insertion(+),
If the case the HDMI controller fails to bind, we try to unbind
all components before calling drm_dev_put() which makes drm_bridge_detach()
crash because unbinding the HDMI controller frees the bridge memory.
The solution is the unbind all components at the end like in the remove
path.
In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.
The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
This adds an encoder bridge designed to drive a MIPI-DSI display
by using the ENCL encoder through the internal MIPI DSI transceiver
connected to the output of the ENCL pixel encoder.
Signed-off-by: Neil Armstrong
Reviewed-by: Jagan Teki
Signed-off-by: Neil Armstrong
---
Add third port corresponding to the ENCL DPI encoder used to connect
to DSI or LVDS transceivers.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Reviewed-by: Rob Herring
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml | 5
| 3 +
23 files changed, 1428 insertions(+), 35 deletions(-)
---
base-commit: ac9a78681b921877518763ba0e89202254349d1b
change-id: 20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-b8e5217e1f4a
Best regards,
--
Neil Armstrong
Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
SoCs, they are used to feed the VPU LCD Pixel encoder used for
DSI display purposes.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 40
drivers/clk/meson/g12a.h | 2 +-
2 files
Expose VCLK2_SEL clock id and add new ids for the CTS_ENCL and CTS_ENCL_SEL
clocks on G12A compatible SoCs.
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.h | 1 -
include/dt-bindings/clock/g12a-clkc.h | 3 +++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git
On 12/05/23 07:40, Maíra Canal wrote:
> Create a new fixed-point helper to allow us to return the rounded value
> of our fixed point value.
>
> [v2]:
> * Create the function drm_fixp2int_round() (Melissa Wen).
> [v3]:
> * Use drm_fixp2int() instead of shifting manually (Arthur Grillo).
On Fri, May 12, 2023 at 6:07 AM Bagas Sanjaya wrote:
>
> Replace GPL boilerplate notice on remaining files with appropriate SPDX
> tag. For files mentioning COPYING, use GPL 2.0; otherwise GPL 1.0+.
> diff --git a/drivers/net/ethernet/8390/ne2k-pci.c
> b/drivers/net/ethernet/8390/ne2k-pci.c
>
On 5/12/23 17:06, Bagas Sanjaya wrote:
> diff --git a/drivers/watchdog/octeon-wdt-nmi.S
> b/drivers/watchdog/octeon-wdt-nmi.S
> index 97f6eb7b5a8e04..57bb0845de477d 100644
> --- a/drivers/watchdog/octeon-wdt-nmi.S
> +++ b/drivers/watchdog/octeon-wdt-nmi.S
> @@ -1,8 +1,5 @@
> +/*
On Fri, May 12, 2023 at 05:06:19PM +0700, Bagas Sanjaya wrote:
> Many watchdog drivers's source files has already SPDX license
> identifier, while some remaining doesn't.
>
> Convert notices on remaining files to SPDX identifier. While at it,
> also move SPDX identifier for
On Fri, May 12, 2023 at 6:07 AM Bagas Sanjaya wrote:
> diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c
> index 504be461f992a9..822bf8905bf3ce 100644
> --- a/drivers/watchdog/sb_wdog.c
> +++ b/drivers/watchdog/sb_wdog.c
> @@ -1,3 +1,4 @@
> +// SPDX-License-Identifier:
This is a leftover from an early iteration of the driver when it was still
named ssd1307 instead of ssd130x. Change it for consistency with the rest.
Signed-off-by: Javier Martinez Canillas
---
drivers/gpu/drm/solomon/ssd130x.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Hi Sam
Am 12.05.23 um 12:29 schrieb Sam Ravnborg:
Hi Thomas,
On Fri, May 12, 2023 at 10:41:41AM +0200, Thomas Zimmermann wrote:
DRM provides a number of wrappers around fbdev cfb_() sys_(), fb_io_()
and fb_sys_() helpers. The DRM functions don't provide any additional
functionality for most
On Fri, 12 May 2023, Andy Shevchenko wrote:
> On Fri, May 12, 2023 at 02:25:18PM +0300, Jani Nikula wrote:
>> On Fri, 12 May 2023, Andy Shevchenko
>> wrote:
>> > On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
>> >> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to
Hi
Am 12.05.23 um 13:16 schrieb David Laight:
From: Thomas Zimmermann
Sent: 12 May 2023 11:25
Cast I/O offsets to pointers to use them with I/O functions. The I/O
functions expect pointers of type 'volatile void __iomem *', but the
offsets are plain integers. Build warnings are
Spelling mistake (triple letters) in comment.
Signed-off-by: Deming Wang
---
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 2d65800d8e93..c933e9a1c5ad 100644
---
On Fri, May 12, 2023 at 02:25:18PM +0300, Jani Nikula wrote:
> On Fri, 12 May 2023, Andy Shevchenko
> wrote:
> > On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
> >> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
> >> masks for fixed-width types and also the
Hi Bagas,
On Fri, May 12, 2023 at 12:08 PM Bagas Sanjaya wrote:
> Replace GPL boilerplate notice on remaining files with appropriate SPDX
> tag. For files mentioning COPYING, use GPL 2.0; otherwise GPL 1.0+.
>
> Cc: David A. Hinds
> Cc: Donald Becker
> Cc: Peter De Schrijver
> Cc: Topi
On Fri, 12 May 2023, Andy Shevchenko wrote:
> On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
>> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
>> masks for fixed-width types and also the corresponding BIT_U32(),
>> BIT_U16() and BIT_U8().
>
> Why?
The main
On Fri, May 12, 2023 at 05:06:11PM +0700, Bagas Sanjaya wrote:
> I trigger this patch series as a response to Didi's GPL full name fix
> patches [1], for which all of them had been NAKed. In many cases, the
> appropriate correction is to use SPDX license identifier instead.
>
> Often, when
From: Thomas Zimmermann
> Sent: 12 May 2023 11:25
>
> Cast I/O offsets to pointers to use them with I/O functions. The I/O
> functions expect pointers of type 'volatile void __iomem *', but the
> offsets are plain integers. Build warnings are
>
> ../drivers/video/fbdev/hitfb.c: In function
On Fri, May 12, 2023 at 05:06:16PM +0700, Bagas Sanjaya wrote:
> Replace unversioned GPL boilerplate notice on remaining i825xx files
> with appropriate SPDX identifier. For files that contains "extension to
> Linux kernel", use GPL 2.0, otherwise GPL 1.0+.
>
> Cc: Donald Becker
> Cc: Michael
On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote:
> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create
> masks for fixed-width types and also the corresponding BIT_U32(),
> BIT_U16() and BIT_U8().
Why?
> All of those depend on a new "U" suffix added to the integer
Currently, the pixel conversion isn't rounding the fixed-point values
before assigning it to the RGB coefficients, which is causing the IGT
pixel-format tests to fail. So, use the drm_fixp2int_round() fixed-point
helper to round the values when assigning it to the RGB coefficients.
Tested with
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