Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
SoCs, they are used to feed the VPU LCD Pixel encoder used for
DSI display purposes.

Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
---
 drivers/clk/meson/g12a.c | 40 ++++++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/g12a.h |  2 +-
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 310accf94830..0b4fe88d3108 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3547,6 +3547,22 @@ static struct clk_regmap g12a_cts_encp_sel = {
        },
 };
 
+static struct clk_regmap g12a_cts_encl_sel = {
+       .data = &(struct clk_regmap_mux_data){
+               .offset = HHI_VIID_CLK_DIV,
+               .mask = 0xf,
+               .shift = 12,
+               .table = mux_table_cts_sel,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "cts_encl_sel",
+               .ops = &clk_regmap_mux_ops,
+               .parent_hws = g12a_cts_parent_hws,
+               .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
+               .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
+       },
+};
+
 static struct clk_regmap g12a_cts_vdac_sel = {
        .data = &(struct clk_regmap_mux_data){
                .offset = HHI_VIID_CLK_DIV,
@@ -3626,6 +3642,22 @@ static struct clk_regmap g12a_cts_encp = {
        },
 };
 
+static struct clk_regmap g12a_cts_encl = {
+       .data = &(struct clk_regmap_gate_data){
+               .offset = HHI_VID_CLK_CNTL2,
+               .bit_idx = 3,
+       },
+       .hw.init = &(struct clk_init_data) {
+               .name = "cts_encl",
+               .ops = &clk_regmap_gate_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &g12a_cts_encl_sel.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+       },
+};
+
 static struct clk_regmap g12a_cts_vdac = {
        .data = &(struct clk_regmap_gate_data){
                .offset = HHI_VID_CLK_CNTL2,
@@ -4406,10 +4438,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data 
= {
                [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
                [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
                [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
+               [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
                [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
                [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
                [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
                [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
+               [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
                [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
                [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
                [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
@@ -4635,10 +4669,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data 
= {
                [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
                [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
                [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
+               [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
                [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
                [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
                [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
                [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
+               [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
                [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
                [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
                [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
@@ -4899,10 +4935,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = 
{
                [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
                [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
                [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
+               [CLKID_CTS_ENCL_SEL]            = &g12a_cts_encl_sel.hw,
                [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
                [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
                [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
                [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
+               [CLKID_CTS_ENCL]                = &g12a_cts_encl.hw,
                [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
                [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
                [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
@@ -5133,10 +5171,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
        &g12a_vclk2_div12_en,
        &g12a_cts_enci_sel,
        &g12a_cts_encp_sel,
+       &g12a_cts_encl_sel,
        &g12a_cts_vdac_sel,
        &g12a_hdmi_tx_sel,
        &g12a_cts_enci,
        &g12a_cts_encp,
+       &g12a_cts_encl,
        &g12a_cts_vdac,
        &g12a_hdmi_tx,
        &g12a_hdmi_sel,
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 1a4a626c2c63..80fe5e4532a7 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -265,7 +265,7 @@
 #define CLKID_NNA_CORE_CLK_DIV                 266
 #define CLKID_MIPI_DSI_PXCLK_DIV               268
 
-#define NR_CLKS                                        271
+#define NR_CLKS                                        273
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/g12a-clkc.h>

-- 
2.34.1

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