On Sun, 2005-06-05 at 14:45 -0400, Vladimir Dergachev wrote:
> >> Yes, however it is convenient to do so.
> >>
> >> The point is that AGP base address will not normally overlap the location
> >> of system RAM. This is, of course, only reasonable for 32 bit systems..
> >
> > I understand that part,
On Sun, 2005-06-05 at 20:16 +0200, Nicolai Haehnle wrote:
> I understand that part, but it's not what I meant. What I mean is this: You
> said, RADEON_MC_AGP_LOCATION is used to program where AGP is in the card's
> address space, and that's all fine and makes sense.
>
> However, we are *also* p
> Yes, however it is convenient to do so.
>
> The point is that AGP base address will not normally overlap the location
> of system RAM. This is, of course, only reasonable for 32 bit systems..
It will overlap it on all PowerMac's (where it will be 0)
Ben.
-
> > My understanding is that AGP only does transfers system RAM -> video RAM
> > and all transfers in the opposite direction have to use plain PCI
> > transfers at least as far as the bus is concerned.
>
> You mean system RAM -> graphics card, right? Does this mean that the
> graphics card cann
On Sun, 2005-06-05 at 09:58 -0400, Vladimir Dergachev wrote:
> >> Which way can memory controller be misprogrammed ? The part that concerns
> >> us are positions of Video RAM, AGP and System Ram in Radeon address space.
> >> (these are specified by RADEON_MC_AGP_LOCATION, RADEON_MC_FB_LOCATION).
Yes, however it is convenient to do so.
The point is that AGP base address will not normally overlap the location
of system RAM. This is, of course, only reasonable for 32 bit systems..
I understand that part, but it's not what I meant. What I mean is this: You
said, RADEON_MC_AGP_LOCATION is u
On Sunday 05 June 2005 20:07, Vladimir Dergachev wrote:
> >> My understanding is that dev->agp->base is the address where the AGP
GART
> >> mirrors the pieces of system RAM comprising AGP space.
> >
> > Yes, that's my understanding, too. But what is the Radeon's business
knowing
> > that address?
This
register is programmed to a value that falls within the AGP area (as
defined by RADEON_MC_AGP_LOCATION) if I understand the code correctly.
My understanding is that AGP only does transfers system RAM -> video RAM
and all transfers in the opposite direction have to use plain PCI
transfers a
On Sunday 05 June 2005 15:55, Vladimir Dergachev wrote:
> On Sat, 4 Jun 2005, Nicolai Haehnle wrote:
> >>
> >> The mirroring works as follows: each time scratch register is written
> > the
> >> radeon controller uses PCI to write their value to a specific location
in
> >> system memory.
> >
> >
On Sun, 5 Jun 2005, Jerome Glisse wrote:
Note that old driver was able to test whether mirroring works, so it
would correspond to behaviour of RV350 cards. It could be that R300 cards
are more touchy in this regard.
Might be worth trying to fallback to non-mirrored setup and see if that
he
> > Note that old driver was able to test whether mirroring works, so it
> > would correspond to behaviour of RV350 cards. It could be that R300 cards
> > are more touchy in this regard.
>
> Might be worth trying to fallback to non-mirrored setup and see if that
> helps.
Was wondering were this
Vladimir Dergachev schrieb:
>
> My understanding is that AGP only does transfers system RAM -> video RAM
> and all transfers in the opposite direction have to use plain PCI
> transfers at least as far as the bus is concerned.
AGP can do both. Every AGP compliant device has to support the
System
Which way can memory controller be misprogrammed ? The part that concerns
us are positions of Video RAM, AGP and System Ram in Radeon address space.
(these are specified by RADEON_MC_AGP_LOCATION, RADEON_MC_FB_LOCATION).
The memory controller *always* assumes that system RAM (accessible via
P
On Sat, 4 Jun 2005, Nicolai Haehnle wrote:
The mirroring works as follows: each time scratch register is written
the
radeon controller uses PCI to write their value to a specific location in
system memory.
Are you sure it uses PCI? I'm assuming that the destination address for
scratch w
> This, of course, would not work if the memory controller is misprogrammed
> - which was the cause of failures.
Goood old discussion :)
> Which way can memory controller be misprogrammed ? The part that concerns
> us are positions of Video RAM, AGP and System Ram in Radeon address space.
> Are you sure it uses PCI? I'm assuming that the destination address for
> scratch writeback is controlled by the RADEON_SCRATCH_ADDR register. This
> register is programmed to a value that falls within the AGP area (as
> defined by RADEON_MC_AGP_LOCATION) if I understand the code correctly.
On Saturday 04 June 2005 15:01, Vladimir Dergachev wrote:
> I just wanted to contribute the following piece of information that
might
> help with R300 lockups. I do not know whether it applies or not in this
> case, but just something to be aware about.
>
> Radeon has a memory controller wh
I just wanted to contribute the following piece of information that might
help with R300 lockups. I do not know whether it applies or not in this
case, but just something to be aware about.
Radeon has a memory controller which translates internal address space of
the chip into accesses of
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