The few sources I've read have said that the hardware for AGP, and PCI-E
was designed to emulate the software interface of PCI so that the
underlying hardware would be transparent to software. This can be seen
in the output of lspci, where my marginally supported R200 (Where's
6.2.2 when you need
My understanding of bus operation is that it's sole function is to
provide memory mapped IO, IO ports, and interrupt control, after these
features are configured -- by the BIOS -- software only has to worry
about the device at the other end... After this initial configuration,
so I thought,
