The few sources I've read have said that the hardware for AGP, and PCI-E was designed to emulate the software interface of PCI so that the underlying hardware would be transparent to software. This can be seen in the output of lspci, where my marginally supported R200 (Where's 6.2.2 when you need it?) is reported as two PCI devices... The purpose of the second device entry is obscure. (On a side note, I have a spare 6326 which I'm willing to donate for the price of shipping, I intend to offer one of my two R128s to a dumb-terminal using friend of mine.. If he declines, I'll offer that too, but only after the R200 driver stabilizes to the point where it Does Not Crash(tm)).
My understanding of bus operation is that it's sole function is to provide memory mapped IO, IO ports, and interrupt control, after these features are configured -- by the BIOS -- software only has to worry about the device at the other end... After this initial configuration, so I thought, the bus was invisible and mostly irrelevant... >From the trafic on this list it seems that not only are there performance considerations but vital operational charactoristics of these busses that require software support. Can someone please explain this to me? -- Friends don't let friends use GCC 3.4.4 GCC 3.3.6 produces code that's twice as fast on x86! Non-sequiter item: Charleston, South Carolina ------------------------------------------------------- SF.Net email is Sponsored by the Better Software Conference & EXPO September 19-22, 2005 * San Francisco, CA * Development Lifecycle Practices Agile & Plan-Driven Development * Managing Projects & Teams * Testing & QA Security * Process Improvement & Measurement * http://www.sqe.com/bsce5sf -- _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
