On Thu, 24 Sep 2015, Dan Carpenter wrote:
> Of course, the maintainer gets the last word regardless of what anyone
> else thinks.
>
> Generally, minimal code is better. Trying to future proof code is a
> waste of time because you can't predict what will happen in the future.
> It's way more
On Wed, 23 Sep 2015, Josh Cartwright wrote:
> On Wed, Sep 23, 2015 at 12:10:13PM -0500, atull wrote:
> > On Tue, 22 Sep 2015, Josh Cartwright wrote:
> [..]
> > > > +struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
> > > > +{
>
Hi Josh,
Thanks for the review. This is all at the tail end of a long
(>2 years) discussion on this. I hope that the way this has
shaped out still meets the needs of the people who have been
in this discussion the most and have had the strongest feelings
(due to being current users of FPGAs
From: Alan Tull
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull
Acked-by: Michal Simek
Acked-by: Moritz Fischer
From: Alan Tull
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull
API to support programming FPGA's.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
From: Alan Tull
This patch set adds the FPGA manager core which exports API functions that
write an image to a FPGA
I'm holding off on the DT overlay support a little for now.
The core's API is minimal to start with: only 6 functions. This gives a
From: Alan Tull
Add a document on the new FPGA manager core.
Signed-off-by: Alan Tull
---
v9: initial version where this patch was added
v10: requested cleanups to formatting and otherwise
s/fpga/FPGA/g
rewrite
On Mon, 17 Aug 2015, Pavel Machek wrote:
On Thu 2015-08-13 12:37:29, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Add a document spelling out usage of the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Pavel Machek
On Fri, 14 Aug 2015, Moritz Fischer wrote:
Hi Alan,
I've updated my Zynq driver (it can be found in an older version
against your v8 in the Xilinx tree, too)
https://github.com/mfischer/linux/tree/alan-fpga-mgr-v10
Since we are both already using this and have been for a while now, I
On Thu, 13 Aug 2015, Moritz Fischer wrote:
Hi Moritz,
Thanks for the review. Will include your two nits in v11.
Hi Alan,
thanks for continuing to work on this :) A couple of minor nits ...
On Thu, Aug 13, 2015 at 10:37 AM, at...@opensource.altera.com wrote:
From: Alan Tull
On Fri, 14 Aug 2015, atull wrote:
On Fri, 14 Aug 2015, Moritz Fischer wrote:
Hi Alan,
I've updated my Zynq driver (it can be found in an older version
against your v8 in the Xilinx tree, too)
https://github.com/mfischer/linux/tree/alan-fpga-mgr-v10
Since we are both already
From: Alan Tull at...@opensource.altera.com
API to support programming FPGA.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
From: Alan Tull at...@opensource.altera.com
This patch set adds two chunks plus documentation:
* FPGA manager core: exports API functions that write an image to a FPGA
* DT Overlay support: simple-fpga-bus to handle FPGA from a DT overlay
The FPGA manager core is mature enough to be in the
From: Alan Tull at...@opensource.altera.com
Add a document on the new FPGA manager core.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v9: initial version where this patch was added
v10: requested cleanups to formatting and otherwise
s/fpga/FPGA/g
rewrite implementation
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports API functions that write an image to a FPGA
* DT Overlay support: simple-fpga-bus to handle FPGA from a DT overlay
The fpga manager core is mature enough to be in the
From: Alan Tull at...@opensource.altera.com
Add a document spelling out usage of the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v9: Initial version of this patch in patchset
v10: s/fpga/FPGA/g
improve formatting
some rewriting
move to
From: Alan Tull at...@opensource.altera.com
Add simple fpga bus. This is a bus that configures an fpga and its
bridges before populating the devices below it. This is intended
for use with device tree overlays.
Note that FPGA bridges are seen as reset controllers so no special
framework for
From: Alan Tull at...@opensource.altera.com
New bindings document for simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v9: initial version added to this patchset
v10: s/fpga/FPGA/g
replace DT overlay example with slightly more complicated example
move to
From: Alan Tull at...@opensource.altera.com
Add a TODO document for the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v10: This patch added in v10 of the patch set
---
drivers/staging/simple-fpga-bus/TODO | 13 +
1 file changed, 13 insertions(+)
create
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
On Fri, 24 Jul 2015, Pavel Machek wrote:
Hi Pavel,
Thanks for your your feedback in cleaning up these docs.
Hi!
+What: /sys/class/fpga_manager/fpga/state
+Date: July 2015
+KernelVersion: 4.2
+Contact: Alan Tull at...@opensource.altera.com
On Thu, 23 Jul 2015, Jason Gunthorpe wrote:
On Thu, Jul 23, 2015 at 02:55:52PM -0700, Moritz Fischer wrote:
Hi Alan,
I saw that your socfpga driver doesn't support the partial reconfig
use case (not a big deal).
What I currently do for Zynq is if I'm doing a non-partial reconfig is
On Wed, 22 Jul 2015, Moritz Fischer wrote:
Hi Miritz,
Hi Alan,
a couple of small things I found while reworking the Zynq version to
match the v9 patchset:
On Fri, Jul 17, 2015 at 8:51 AM, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
...
+
On Thu, 23 Jul 2015, Greg KH wrote:
On Fri, Jul 17, 2015 at 10:51:10AM -0500, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports ABI functions that write an image to a FPGA
*
On Fri, 17 Jul 2015, atull wrote:
On Fri, 17 Jul 2015, Jason Gunthorpe wrote:
On Fri, Jul 17, 2015 at 10:51:10AM -0500, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports
On Wed, 22 Jul 2015, Jason Gunthorpe wrote:
On Wed, Jul 22, 2015 at 03:32:32PM -0500, atull wrote:
I looked some more; I don't see a simple way of deferring probing until
after the filesystem is loaded (so that the image file would be
available), late_initcall is still not late enough
From: Alan Tull at...@opensource.altera.com
API to support programming FPGA.
The following functions are exported as GPL:
* fpga_mgr_buf_load
Load fpga from image in buffer
* fpga_mgr_firmware_load
Request firmware and load it to the FPGA.
* fpga_mgr_register
* fpga_mgr_unregister
From: Alan Tull at...@opensource.altera.com
New bindings document for simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
.../Documentation/bindings/simple-fpga-bus.txt | 61
1 file changed, 61 insertions(+)
create mode 100644
From: Alan Tull at...@opensource.altera.com
Add simple fpga bus. This is a bus that configures an fpga and its
bridges before populating the devices below it. This is intended
for use with device tree overlays.
Note that FPGA bridges are seen as reset controllers so no special
framework for
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports ABI functions that write an image to a FPGA
* DT Overlay support: simple-fpga-bus to handle FPGA from a DT overlay
The core's ABI is minimal to start with: only 6
From: Alan Tull at...@opensource.altera.com
Add a document on the new FPGA manager core.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
drivers/staging/fpga/Documentation/fpga-mgr.txt | 117 +++
1 file changed, 117 insertions(+)
create mode 100644
From: Alan Tull at...@opensource.altera.com
Add a document spelling out usage of the simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
.../staging/fpga/Documentation/simple-fpga-bus.txt | 48
1 file changed, 48 insertions(+)
create mode 100644
On Fri, 17 Jul 2015, Jason Gunthorpe wrote:
On Fri, Jul 17, 2015 at 10:51:10AM -0500, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
This patchset adds two chunks plus documentation:
* fpga manager core: exports ABI functions that write an image to a
On Fri, 17 Jul 2015, Steffen Trumtrar wrote:
Hi!
On Fri, Jul 17, 2015 at 10:51:13AM -0500, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
New bindings document for simple fpga bus.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
On Fri, 17 Jul 2015, Moritz Fischer wrote:
Hi Moritz,
Alan,
it looks pretty good so far. I have worked with Michal and developed a
Zynq equivalent against your last
patchset which can be found in the Xilinx tree now.
I just briefly glanced the changes below just two nits that caught my
On Thu, 19 Feb 2015, Michal Simek wrote:
On 02/17/2015 08:17 PM, Pavel Machek wrote:
On Tue 2015-02-17 11:07:53, Rob Landley wrote:
On 02/15/2015 04:40 PM, Pavel Machek wrote:
On Wed 2015-01-21 13:27:00, Jason Gunthorpe wrote:
On Wed, Jan 21, 2015 at 06:33:12PM +0200, Pantelis
On Tue, 13 Jan 2015, Jason Gunthorpe wrote:
On Tue, Jan 13, 2015 at 03:37:14PM -0600, atull wrote:
I do agree with this, and I think this is where this patch set goes so
wrong.
Just exposing all sorts of controls to userspace and having a way for
the kernel to load/unload
On Tue, 13 Jan 2015, Pavel Machek wrote:
On Tue 2015-01-13 09:40:18, Pantelis Antoniou wrote:
Hi Pavel,
On Jan 13, 2015, at 09:28 , Pavel Machek pa...@denx.de wrote:
Hi!
+What: /sys/class/fpga_manager/fpga/firmware
+Date: October 2014
On Tue, 13 Jan 2015, Pantelis Antoniou wrote:
Hi Alan,
On Jan 13, 2015, at 18:28 , One Thousand Gnomes
gno...@lxorguk.ukuu.org.uk wrote:
On Mon, 12 Jan 2015 14:43:14 -0700
Jason Gunthorpe jguntho...@obsidianresearch.com wrote:
On Mon, Jan 12, 2015 at 09:01:34PM +, One
On Tue, 13 Jan 2015, Jason Gunthorpe wrote:
On Tue, Jan 13, 2015 at 04:28:47PM +, One Thousand Gnomes wrote:
There is a lot of code overlap in things like loading the bitstreams,
there is also some overlap because you want to be able to assign FPGA
resources. For example if you have
On Sat, 10 Jan 2015, Konrad Zapalowicz wrote:
On 01/06, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Alan, there is something wrong with your email client configuration
and you need to fix.
thanks,
konrad
Hi Konrad,
Can you be more specific? What
On Sat, 10 Jan 2015, Pavel Machek wrote:
On Sat 2015-01-10 10:10:51, Pantelis Antoniou wrote:
Hi Pavel,
On Jan 9, 2015, at 22:56 , Pavel Machek pa...@denx.de wrote:
On Fri 2015-01-09 13:14:24, atull wrote:
On Wed, 7 Jan 2015, Pavel Machek wrote:
On Tue 2015-01-06 14:13
On Wed, 7 Jan 2015, Pavel Machek wrote:
On Tue 2015-01-06 14:13:37, at...@opensource.altera.com wrote:
+
+What: /sys/class/fpga_manager/fpga/firmware
+Date: October 2014
+KernelVersion: 3.18
+Contact: Alan Tull at...@opensource.altera.com
+Description:
On Fri, 9 Jan 2015, Rob Herring wrote:
On Tue, Jan 6, 2015 at 4:34 PM, atull at...@opensource.altera.com wrote:
On Tue, 6 Jan 2015, Rob Herring wrote:
On Tue, Jan 6, 2015 at 2:13 PM, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
New bindings
From: Alan Tull at...@opensource.altera.com
v8 changes the compatible string for SOCFPGA FPGA managers
to be more chip specific.
altr,fpga-mgr becomes altr,socfpga-fpga-mgr
Thanks,
Alan
Alan Tull (4):
doc: add bindings document for altera fpga manager
fpga manager: add sysfs interface
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
v6 : No change in this patch for v6 of the patch set
v7 : No change in this
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
On Tue, 6 Jan 2015, Rob Herring wrote:
On Tue, Jan 6, 2015 at 2:13 PM, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Rob Herring
On Mon, 22 Dec 2014, Rob Herring wrote:
On Fri, Dec 19, 2014 at 10:45 AM, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : Move bindings to
On Fri, 19 Dec 2014, Greg KH wrote:
On Fri, Dec 19, 2014 at 03:20:59PM +0100, Michal Simek wrote:
Hi Greg,
On 12/18/2014 11:29 PM, at...@opensource.altera.com wrote:
From: Alan Tull at...@opensource.altera.com
Dropping the changes to socfpga DTS and defconfig from this
patch
On Fri, 19 Dec 2014, Steffen Trumtrar wrote:
On Fri, Dec 19, 2014 at 03:05:50PM +0100, Michal Simek wrote:
On 12/19/2014 09:55 AM, Steffen Trumtrar wrote:
Hi!
Just a minor nitpick, but...
On Thu, Dec 18, 2014 at 04:29:08PM -0600, at...@opensource.altera.com
wrote:
From:
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
v6 : No change in this patch for v6 of the patch set
v7 : No change in this
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
From: Alan Tull at...@opensource.altera.com
For after 3.19-rc1 is out.
v7 adds a one line fix from the kbuild test robot and
Michal Simek's signoff.
Thanks,
Alan
Alan Tull (4):
doc: add bindings document for altera fpga manager
fpga manager: add sysfs interface document
staging: fpga
On Thu, 18 Dec 2014, Michal Simek wrote:
Hi Alan,
first of all - there are these kernel-doc warnings.
Info(drivers/staging/fpga/fpga-mgr.c:37): Scanning doc for
fpga_mgr_low_level_state
Warning(drivers/staging/fpga/fpga-mgr.c:43): No description found for return
value of
On Thu, 18 Dec 2014, Michal Simek wrote:
Hi Michal,
+
+ /* Write out remaining non 32-bit chunks. */
+ switch (count) {
+ case 3:
+ socfpga_fpga_data_writel(priv, buffer_32[i++] 0x00ff);
+ break;
+ case 2:
+
From: Alan Tull at...@opensource.altera.com
Dropping the changes to socfpga DTS and defconfig from this
patch set.
Kernel doc fixes and other minor fixes as listed in the patches.
Alan
Alan Tull (4):
doc: add bindings document for altera fpga manager
fpga manager: add sysfs interface
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
v6 : No change in this patch for v6 of the patch set
---
From: Alan Tull at...@opensource.altera.com
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
Acked-by: Michal Simek michal.si...@xilinx.com
---
v2: fpga_manager struct now contains struct device
From: Alan Tull at...@opensource.altera.com
Intended for after 3.19-rc1
v5 includes changes from feedback from Michal, Steffen, Alan, Greg, and the
kbuild test robot.
The driver is under drivers/staging/fpga/
The header is now in include/linux/fpga/
The sysfs doc is in
From: Alan Tull at...@opensource.altera.com
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v2: fpga_manager struct now contains struct device
fpga_manager_register parameters now take
From: Alan Tull at...@opensource.altera.com
Enable FPGA manager for Altera socfpga.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_SOCFPGA/
---
arch/arm/configs/socfpga_defconfig |4
1 file changed, 4 insertions(+)
diff --git
From: Alan Tull at...@opensource.altera.com
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
---
.../Documentation/bindings/altera-fpga-mgr.txt | 17 +
From: Alan Tull at...@opensource.altera.com
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move
From: Alan Tull at...@opensource.altera.com
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
From: Alan Tull at...@opensource.altera.com
Add Altera FGPA manager to device tree.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v5 : remove simple-bus and associated stuff
---
arch/arm/boot/dts/socfpga.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git
On Thu, 11 Dec 2014, One Thousand Gnomes wrote:
On Thu, 11 Dec 2014 09:43:24 +0800
kbuild test robot fengguang...@intel.com wrote:
drivers/staging/fpga/socfpga.c:655:25: sparse: symbol 'socfpga_fpga_ops'
was not declared. Should it be static?
Signed-off-by: Fengguang Wu
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