Signed-off-by: Scott Telford
---
CadencePkg/CadenceCsp.dsc | 4 +-
CadencePkg/CadenceCsp.fdf | 2 +-
.../CadenceCspResetSystemLib.c | 121 +
.../CadenceCspResetSystemLib.inf | 13 +--
4
Add .dsc, .fdf and .dec files for a Cadence CSP platform configured
with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root
Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/CadenceCsp.dsc| 688
017 17:16
> To: Scott Telford
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject: Re: [staging/cadence-aarch64 PATCH v2 6/6] CadencePkg: Add .dsc,
> .fdf and .dec files for Cadence CSP platform.
>
Revised patchset following comments from Leif and Ard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
Scott Telford (6):
CadencePkg: Add libraries for Cadence CSP platform.
CadencePkg: Add library for Cadence UART.
CadencePkg: Add PCI host bridge
Add serial port library to support the Cadence IP6528 UART used in the
Cadence CSP platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/Include/Library/CspSerialPortLib.h | 86
.../CadenceCspSerialPortLib/CspSerialPortLib.c
Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/Sec/AArch64/Arch.c | 25 +++
CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 +++
CadencePkg/Sec/AArch64/Helper.S | 93
CadencePkg/Sec/AArch64/SecEntryPoint.S | 139
CadencePkg/Sec
Add .dsc, .fdf and .dec files for a Cadence CSP platform configured
with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root
Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/CadenceCsp.dsc| 672
Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
This library is derived from
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
.../Library/CadencePciHostBridgeLib
: Scott Telford
---
CadencePkg/Include/Library/CspSysReg.h | 37 ++
.../CadenceCspLib/AArch64/ArmPlatformHelper.S | 55 +
CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 133 +
CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 68
Add ACPI tables for Cadence CSP platform configured with a single
Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/AcpiTables/AcpiTables.inf | 50 ++
CadencePkg/AcpiTables
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 05 June 2017 16:40
> To: Scott Telford
> Cc: edk2-devel@lists.01.org ; Leif Lindholm
> ; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D
> Subject: Re: [staging/cade
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 12:37
> To: Scott Telford
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject:
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 12:12
> To: Ard Biesheuvel
> Cc: Scott Telford ; edk2-devel@lists.01.org de...@ml01.01.org>; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D
> Subject: Re:
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 06 June 2017 11:52
> To: Scott Telford
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg...@linaro.org; af...@apple.com; michael.d.kin...@intel.com
> Subject:
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 05 June 2017 16:25
> To: Scott Telford
> Cc: edk2-devel@lists.01.org ; Leif Lindholm
> ; Graeme Gregory ;
> af...@apple.com; Kinney, Michael D
> Subject: Re: [staging/cade
Hi Ard, sorry for the delay, got sidetracked by other issues.
> If I am reading the code correctly, this UEFI port may execute under
> ATF or may be booted at EL3 directly, right? In the former case, you
> should really be using PSCI for reset instead of poking the system
> registers directly.
No
Hi Leif, sorry for the delay in replying, got sidetracked by other issues.
> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: 05 June 2017 18:11
> To: Scott Telford
> Cc: edk2-de...@ml01.01.org; ard.biesheu...@linaro.org;
> graeme.greg
Telford
Scott Telford (6):
CadencePkg: Add libraries for Cadence CSP platform.
CadencePkg: Add library for Cadence UART.
CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.
CadencePkg: Add SEC phase implementation for Cadence CSP platform.
CadencePkg: Add ACPI tables for
: Scott Telford
---
CadencePkg/Include/Library/CspSysReg.h | 37 ++
.../CadenceCspLib/AArch64/ArmPlatformHelper.S | 62 +
CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 135 +++
CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 76
Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
This library is derived from
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
.../Library/CadencePciHostBridgeLib
Add SEC phase implementation for Cadence CSP platform configured with
a single Cortex-A53 processor and GIC-500.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/Sec/AArch64/Arch.c | 25 +++
CadencePkg/Sec/AArch64
Add ACPI tables for Cadence CSP platform configured with a single
Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/AcpiTables/AcpiTables.inf | 49 +
CadencePkg/AcpiTables
Add .dsc, .fdf and .dec files for a Cadence CSP platform configured
with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root
Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/CadenceCsp.dsc| 711
Add serial port library to support the Cadence IP6528 UART used in the
Cadence CSP platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
CadencePkg/Include/Library/CspSerialPortLib.h | 86
.../CadenceCspSerialPortLib/CspSerialPortLib.c
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 30 May 2017 11:14
> To: Scott Telford
> Cc: Leif Lindholm ; edk2-devel@lists.01.org de...@ml01.01.org>; Tian, Feng ; Zeng, Star
>
> Subject: Re: [edk2] [PATCH] Copy bus scanning workaround from ARM Juno
>
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 26 May 2017 18:38
> To: Leif Lindholm
> Cc: Scott Telford ; edk2-devel@lists.01.org de...@ml01.01.org>; Tian, Feng ; Zeng, Star
>
> Subject: Re: [edk2] [PATCH] Copy bus scanning workaround from ARM Juno
agree there should probably be a more elegant solution, but I don't know the
generic PCI driver code well enough to suggest one at the moment.
Regards,
Scott.
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 23 May 2017 17:42
>
Copy workaround previously in
ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c:PciRbPciRead()
to RootBridgeIoPciAccess(), to avoid spurious multiple detections when
scanning buses.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
Announcing the creation of a new edk2-staging branch for Cadence peripheral
hardware support in AArch64 platforms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford
---
Readme.MD | 27 +++
1 file changed, 27 insertions(+)
create mode
29 matches
Mail list logo
