[fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Michael Schnell
In another topic (now closed) Andrew described that a code similar to HansPeter's example did run correctly on a dual core machine, but produced errors on a machine with more cores. Now I understand that threaded FPC user programs are supposed to be done in a Posix compliant way and

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Mark Morgan Lloyd
Michael Schnell wrote: In another topic (now closed) Andrew described that a code similar to HansPeter's example did run correctly on a dual core machine, but produced errors on a machine with more cores. I've not been reading every message. Definitive URL? OTOH if some synchronization

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Michael Schnell
On 07/01/2011 11:26 AM, Mark Morgan Lloyd wrote: Michael Schnell wrote: In another topic (now closed) Andrew described that a code similar to HansPeter's example did run correctly on a dual core machine, but produced errors on a machine with more cores. I've not been reading every message.

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Vincent Snijders
2011/7/1 Michael Schnell mschn...@lumino.de: On 07/01/2011 11:26 AM, Mark Morgan Lloyd wrote: Michael Schnell wrote: In another topic (now closed) Andrew described that a code similar to HansPeter's example did run correctly on a dual core machine, but produced errors on a machine with more

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Michael Schnell
On 07/01/2011 02:00 PM, Vincent Snijders wrote: I won't call that a definitive URL, but some vague indication. That is more than 200 mails at least. I'd expected you to give a link to the email in the archives where Andrew described a code. So, which link to click on

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Vincent Snijders
2011/7/1 Michael Schnell mschn...@lumino.de: On 07/01/2011 02:00 PM, Vincent Snijders wrote: I won't call that a definitive URL, but some vague indication. That is more than 200 mails at least. I'd expected you to give a link to the email in the archives where Andrew described a code. So,

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Michael Schnell
On 07/01/2011 03:03 PM, Vincent Snijders wrote: So how you expect us to find the description *you* want us to read in all those mails, if even you cannot find it. I can't find it in the backlog website. I did find it in my mailstore (no idea if this helps, though): This is the message of

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Mark Morgan Lloyd
Vincent Snijders wrote: 2011/7/1 Michael Schnell mschn...@lumino.de: On 07/01/2011 02:00 PM, Vincent Snijders wrote: I won't call that a definitive URL, but some vague indication. That is more than 200 mails at least. I'd expected you to give a link to the email in the archives where Andrew

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Andrew Brunner
On Fri, Jul 1, 2011 at 8:51 AM, Mark Morgan Lloyd markmll.fpc-de...@telemetry.co.uk wrote: Fair play, he /has/ said he's mailed Andrew looking for source. I never received such email. But to Michael's defense, Google mail isn't the product it once was. However under the circumstances we've

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Hans-Peter Diettrich
Vincent Snijders schrieb: Michael Schnell wrote: In another topic (now closed) Andrew described that a code similar to HansPeter's example did run correctly on a dual core machine, but produced errors on a machine with more cores. I've not been reading every message. Definitive URL? I

Re: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Andrew Brunner
On Fri, Jul 1, 2011 at 11:44 AM, Hans-Peter Diettrich drdiettri...@aol.com wrote: IMO a linked list can not work flawlessly, until at least a multiple-read-exclusive-write lock is used. While an exclusive-write lock can ensure list consistency, every unsynchronized reader will be fooled by

Re[2]: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread José Mejuto
Hello FPC, Friday, July 1, 2011, 6:44:44 PM, you wrote: HPD This scenario was reflected in my example (bi-linked list update). HPD The very last sentence deserves clarification. When not *all* HPD assignments are protected by a CS, the use of Interlocked assignments HPD only can improve cache

Re: Re[2]: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Andrew Brunner
On Fri, Jul 1, 2011 at 12:48 PM, José Mejuto joshy...@gmail.com wrote: This code will crash at a given time, maybe 1 millisecond, maybe 2 days, but it will crash. Yes. It will fail. Access to a,b are forbidden without acquiring a lock. Cache coherence is maintained by the hardware,

Re: Re[2]: [fpc-devel] SMP 2 core Cache issue with Posix threads

2011-07-01 Thread Jonas Maebe
Hello, This thread is now also moderated. See http://lists.freepascal.org/lists/fpc-other/2011-July/000637.html for the reason why. Please start/continue any discussions about how to safely program in a multithreaded way on the fpc-other list (unless it's about concrete proposals for