Re: Passing the complex args in the GPR's

reference to support this decision ? Thank you ~Umesh On Tue, Jun 6, 2023 at 10:16 PM Segher Boessenkool wrote: > > Hi! > > On Tue, Jun 06, 2023 at 08:35:22PM +0530, Umesh Kalappa wrote: > > Hi Adnrew, > > Thank you for the quick response and for PPC64 too ,we do have

Re: Passing the complex args in the GPR's

at 7:50 AM Umesh Kalappa via Libc-alpha > wrote: > > > > Hi all , > > > > For the test case https://godbolt.org/z/vjs1vfs5W ,we see the mismatch > > in the ABI b/w gcc and clang . > > > > Do we have any supporting documents that second the GCC behavio

Passing the complex args in the GPR's

Hi all , For the test case https://godbolt.org/z/vjs1vfs5W ,we see the mismatch in the ABI b/w gcc and clang . Do we have any supporting documents that second the GCC behaviour over CLANG ? EABI states like In the Power Architecture 64-Bit ELF V2 ABI Specification document (v1.1 from 16 July 20

Re: [PowerPC 64]r12 is not updated to GEP when control transferred from virtual thunk function .

Hi Segher, Please refer the https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90513 . Thank you ~Umesh On Fri, May 17, 2019 at 4:22 AM Segher Boessenkool wrote: > > Hi Umesh, > > On Thu, May 16, 2019 at 06:12:48PM +0530, Umesh Kalappa wrote: > > We are very new to Power abi and

Re: [PowerPC 64]r12 is not updated to GEP when control transferred from virtual thunk function .

On Thu, May 16, 2019 at 9:00 AM Umesh Kalappa wrote: > > >>Can't you get the loader fixed, instead? > Yes we are thinking the same ,question what should be loader semantics here > (update the prologue code to update r12 to Global Entry Point or Update R2 > with toc bas

Re: [PowerPC 64]r12 is not updated to GEP when control transferred from virtual thunk function .

>>Can't you get the loader fixed, instead? Yes we are thinking the same ,question what should be loader semantics here (update the prologue code to update r12 to Global Entry Point or Update R2 with toc base (that don't relay on the R12). ) ~Umesh On Thu, May 16, 2019, 05:22 Segher Boessenkool wr

Re: [PowerPC 64]r12 is not updated to GEP when control transferred from virtual thunk function .

Thank you Eric for the suggestion and say that we support in the loader part ,can you please point on elfv2 reference that says implementation for this specific case. ~Umesh On Wed, May 15, 2019, 21:35 Eric Botcazou wrote: > > like above the control from "_ZThn8_N12Intermediate1vEv" (support

[PowerPC 64]r12 is not updated to GEP when control transferred from virtual thunk function .

Hi All, We have the situation ,where the R12 is pointing to Thunk GEP ,not the current function like .size _ZN12Intermediate1vEv,.-_ZN12Intermediate1vEv .set.LTHUNK0,_ZN12Intermediate1vEv .align 2 .globl _ZThn8_N12Intermediate1vEv .type _ZThn8_N12In

Re: Power 64 ELFv2 w.r.t toc(cmodel=medium) on windows.

018 at 6:57 PM David Edelsohn wrote: > > On Thu, Oct 25, 2018 at 11:53 AM Umesh Kalappa > wrote: > > > > Hi All, > > > > For the below code (test.c) > > > > int foo() > > { > > printf("Hello World"); > > } > >

Re: Power 64 ELFv2 w.r.t toc(cmodel=medium) on windows.

Cced maintainer like David Edelsohn and Segher Boessenkool . Any suggestions/comments for the below query ? Thank you ~Umesh On Thu, Oct 25, 2018 at 9:23 PM Umesh Kalappa wrote: > > Hi All, > > For the below code (test.c) > > int foo() > { > printf("Hello World

Power 64 ELFv2 w.r.t toc(cmodel=medium) on windows.

Hi All, For the below code (test.c) int foo() { printf("Hello World"); } On linux : ccpc -mcpu=e6500 -mno-altivec -mabi=no-altivec -D_WRS_HARDWARE_FP -mabi=elfv2 -mcmodel=med -mhard-float -S test.c linux asm : the constant string fetched like addis 3,2,.LC0@toc@ha addi 3,3,.LC0@toc@l wher

Mips :delay slot filler with store.

Hi All, For the below C code Test.u32pt = u32PtLen; Test.u32pn = u32PtCnt; Test.pstpk = pstPt; Test.psteo = pstEgrInfo; Test.e = 1; Test.pstfi = pstFi ; return foo(&Test, AclAction); where "Test" is the struct type . the generated code for mips (with -fno-dela

warning: conversion from ‘int’ to ‘char’ may change value

Hi All, When we try to compile the below case from trunk gcc we get the below warning (-Wconversion) i.e void start(void) { char n = 1; char n1 = 0x01; n &= ~n1; } $xgcc -S warn.c -nostdinc -Wconversion warning: conversion from ‘int’ to ‘char’ may change value [-Wconversion] n &= ~n1;

Re: O2 Agressive Optimisation by GCC

> > On Freitag, 20. Juli 2018 14:19:12 CEST Umesh Kalappa wrote: >> > > Hi All , >> > > >> > > We are looking at the C sample i.e >> > > >> > > extern int i,j; >> > > >> > > int tes

Re: O2 Agressive Optimisation by GCC

47 PM, Richard Biener wrote: > On July 20, 2018 7:59:10 PM GMT+02:00, Martin Sebor wrote: >>On 07/20/2018 06:19 AM, Umesh Kalappa wrote: >>> Hi All , >>> >>> We are looking at the C sample i.e >>> >>> extern int i,j; >>> >>> int te

O2 Agressive Optimisation by GCC

Hi All , We are looking at the C sample i.e extern int i,j; int test() { while(1) { i++; j=20; } return 0; } command used :(gcc 8.1.0) gcc -S test.c -O2 the generated asm for x86 .L2: jmp .L2 we understand that,the infinite loop is not deterministic ,compiler is fr

Re: Subnormal float support in armv7(with -msoft-float) for intrinsics

Will do, thanks. Thanks On Tue, Jul 17, 2018, 3:24 PM Ramana Radhakrishnan < ramana@googlemail.com> wrote: > On Tue, Jul 17, 2018 at 10:41 AM, Umesh Kalappa > wrote: > > Hi Nagy, > > > > Please help us with your comments on the attached patch for the issue >

Re: Subnormal float support in armv7(with -msoft-float) for intrinsics

Hi Nagy, Please help us with your comments on the attached patch for the issue (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86512) Thank you and waiting for your inputs on the same. ~Umesh On Fri, Jul 13, 2018 at 1:22 PM, Umesh Kalappa wrote: > Thank you and issue raised at >

Re: Subnormal float support in armv7(with -msoft-float) for intrinsics

Thank you and issue raised at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86512 ~Umesh On Thu, Jul 12, 2018 at 9:33 PM, Szabolcs Nagy wrote: > On 12/07/18 16:20, Umesh Kalappa wrote: >> >> Hi everyone, >> >> we have our source base ,that was compiled for armv7 on gc

Subnormal float support in armv7(with -msoft-float) for intrinsics

Hi everyone, we have our source base ,that was compiled for armv7 on gcc8.1 with soft-float and for following input a=0x0010 b=0x0001 result = a - b ; we are getting the result as "0x000e" and with -mhard-float (disabled the flush to zero mode ) we are getti

Re: Fwd: GCC 8.1 :Store Merge pass issue (-fstore-merging).

Thank you Jakub ,the attached patch in the PR86492 fixes the issue. Appreciate your quick response here . ~Umesh On Wed, Jul 11, 2018 at 10:17 PM, Jakub Jelinek wrote: > On Wed, Jul 11, 2018 at 09:48:07PM +0530, Umesh Kalappa wrote: >> Cc'ed Kyrill. > > Mailing list is not

Re: Fwd: GCC 8.1 :Store Merge pass issue (-fstore-merging).

Thank you Jakub and my bad sure next time. Umesh On Wed, Jul 11, 2018, 10:17 PM Jakub Jelinek wrote: > On Wed, Jul 11, 2018 at 09:48:07PM +0530, Umesh Kalappa wrote: > > Cc'ed Kyrill. > > Mailing list is not the right medium to report bugs. > I've filed http://gcc.

Fwd: GCC 8.1 :Store Merge pass issue (-fstore-merging).

Cc'ed Kyrill. -- Forwarded message - From: Umesh Kalappa Date: Wed, Jul 11, 2018, 7:37 PM Subject: GCC 8.1 :Store Merge pass issue (-fstore-merging). To: Hi Everyone , We have the below case ,where store marge pass doing the invalid optimization (thats our observatio

GCC 8.1 :Store Merge pass issue (-fstore-merging).

Hi Everyone , We have the below case ,where store marge pass doing the invalid optimization (thats our observations on powerpc ) ,i.e C case : typedef unsigned int UINT32; typedef union { UINT32 regVal; struct { UINT32 mask:1; UINT32 a:1; UINT32 :6;

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

Ok, thanks for the clarification jakub. Umesg On Mon, May 7, 2018, 2:08 PM Jakub Jelinek wrote: > On Mon, May 07, 2018 at 01:58:48PM +0530, Umesh Kalappa wrote: > > CCed Jakub, > > > > Agree that float division don't touch memory ,but fdiv result (stack > > &

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

CCed Jakub, > Hi Alex, > Agree that float division don't touch memory ,but fdiv result (stack > register ) is stored back to a memory i.e fResult . > > So compiler barrier in the inline asm i.e ::memory should prevent the > shrinkage of instructions like "fstps fResult(%rip)"behind the

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

Hi Alex , Agree that float division don't touch memory ,but fdiv result (stack register ) is stored back to a memory i.e fResult . So compiler barrier in the inline asm i.e ::memory should prevent the shrinkage of instructions like "fstps fResult(%rip)"behind the fence ? BTW ,if we mak

Replacement for the .stabs directive

Hello Everyone , We have the legacy code ,that uses the .stabs directive quiet often in the source code like .stabs "symbol_name", 100, 0, 0, 0 + .label_one f; .label_one stmt and ,the above code is wrapped with the inline asm in the c source file . we are using clang 3.8(with lto)

Re: ARM gold unknown option.

On top of that , How do i enable the Byte Invariant Addressing mode for gold ?? Thank you ~Umesh On Tue, May 17, 2016 at 11:04 AM, Umesh Kalappa wrote: > Hi All , > > We are migrating to the gold linker and see the below issue > > > bash-4.1$ /auto/compiler-migration/bin/a

ARM gold unknown option.

Hi All , We are migrating to the gold linker and see the below issue bash-4.1$ /auto/compiler-migration/bin/armeb-linux-gnueabi-ld.gold --be8 /auto/compiler-migration/bin/armeb-linux-gnueabi-ld.gold: --be8: unknown option Any help ,will be appreciated . Thank you ~Umesh

Re: Change the arrch64 abi ...(Custom /Specific change)

04/2016 08:55 AM, Umesh Kalappa wrote: >> >> We are in process of changing the gcc compiler for aarch64 abi ,w.r.t >> varargs function arguments handling. >> >> default(LP64) ,where 1,2,4 bytes args are promoted to word size i.e 4 >> bytes ,we need to change th

Change the arrch64 abi ...(Custom /Specific change)

Hi All, We are in process of changing the gcc compiler for aarch64 abi ,w.r.t varargs function arguments handling. default(LP64) ,where 1,2,4 bytes args are promoted to word size i.e 4 bytes ,we need to change these behaviour to 8 bytes (double word). we are looking both hooks like PROMOTE_MO

Re: PIE/PIC issue ...w.r.t linker variable

Hi Kyrill , Thank you for the info ,before i file a bug ,need to confirm its a bug or not . Thank you ~Umesh On Fri, Feb 12, 2016 at 3:00 PM, Kyrill Tkachov wrote: > Hi, > > > On 12/02/16 09:19, Umesh Kalappa wrote: >> >> Hi Guys , >> >> we do have a issue

PIE/PIC issue ...w.r.t linker variable

Hi Guys , we do have a issue with below code ,When we enabled the pie (-fpie/pie) option i.e main.c extern int *my_ptr ; int main() { return *my_ptr; } foo.s .syntax unified .cpu cortex-m0 .fpu softvfp .thumb .global my_ptr .global my_var .data .align 2 .type my_pt

Re: ldm/stm bus error

last byte > of a (similarly for b). Neither of these addresses can fault, even if > they are beyond the end of the object itself. Anyway, such a fault > would be a segmentation fault, not a bus error. > > R. > >> On Mon, May 18, 2015 at 4:50 PM, Richard Earnshaw >> wrote:

ldm/stm bus error

Hi All, Getting a bus/hard error for the below case ,make sense since ldm/stm expects the address to be word aligned . bash-4.1$ cat test.c struct test { char c; int i; } __attribute__((packed)); struct test a,b; int main() { a =b ; //here compiler is not sure that a or

Unnamed Struct / Union

Hi All , GCC 4.8.3 ,pop up with below error /home/i16382/an.c:13:18: error: duplicate member 'bOriginator' unsigned bOriginator; ^ for the case union { struct { unsigned bStatusType; unsigned bOriginator; }; struct { unsigne

Re: string constant of the constant pool entry..

Thank you richard for the inputs . ~Umesh On Wed, Mar 4, 2015 at 3:29 AM, Richard Sandiford wrote: > Umesh Kalappa writes: >> Hi All, >> >> I'm trying to fetch the string constant from the constant pool entry >> for the symbol_ref rtx like >>

string constant of the constant pool entry..

Hi All, I'm trying to fetch the string constant from the constant pool entry for the symbol_ref rtx like c sample int i; int main() { printf("%d",i); } rtl is (gdb) p debug_rtx(val) (symbol_ref/f:SI ("*.LC0") [flags 0x2] ) corresponding asm .section.rodata,code .alig

string constant of the constant pool entry..

Hi All, I'm trying to fetch the string constant from the constant pool entry for the symbol_ref rtx like c sample int i; int main() { printf("%d",i); } rtl is (gdb) p debug_rtx(val) (0xb7da4da0) (symbol_ref/f:SI ("*.LC0") [flags 0x2] ) corresponding asm .section.rodata,code

libgcc_s_sjlj-1 and libstdc++-6 dependency...

Hi All, Was configured and build gcc 4.8.3 for windows on linux using mingw . configure options as ../../src45x/gcc/configure --build=i686-pc-linux-gnu --host=i686-w64-mingw32 --with-dwarf2 --with-newlib --with-gnu-as --with-gnu-ld --enable-cxx-flags=-mno-smart-io --enable-lto --enable-fixed-poi

forcing to emit absolute addresses in the .debug_loc setion

Hi Guys, Myself was very new to dwarf debugging format and recently we migrate GCC compiler to 4.8.3 toolchain from 4.5.2 ans using same binutils 2.23.51. we are seeing the weird issue with .debug_loc entries and assembler pop up with below error /tmp/ccUj1tbg.s: Assembler messages: /tmp/ccU

Re: Optimized Allocation of Argument registers

Ajit, Please check it out the -fshrink-wrap option. ~Umesh On Mon, Nov 24, 2014 at 5:17 PM, Ajit Kumar Agarwal wrote: > All: > > The optimization of reducing save and restore of the callee and caller saved > register has been the attention Of > increasing the performance of the benchmark. Th

error: ‘ggc_alloc_cleared_machine_function’ was not declared in this scope

Hi All , Tried with gcc 4.8.3 build for mips as $../src/gcc-4.8-2014.05/configure --target=mips --enable-languages=c,c++ $make all-gcc g++ -c -g -O2 -DIN_GCC -DCROSS_DIRECTORY_STRUCTURE -fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall -Wwrite-strings -Wcast-qual -Wmissing-fo

About Code coverage Algorithms.

Hi All, Good day for everyone . We benchmarked the code coverage algorithms like a)Optimal Edge Profiling (ftp://ftp.cs.wisc.edu/pub/techreports/1991/TR1031.pdf .) that are adopted by GCC and LLVM b)Dominator Leaf instrumentation(http://users.sdsc.edu/~mtikir/publications/papers/issta02.pdf)

Attributes for var_decl and fun_decl.

Dear All, We ported gcc 4.8.1 for custom hardware and we have target specific attributes like io for variables and interrupt for functuions and many more. We are able to fetch the attributes for variables like look_up(DECL_ATTRIBUTES(node),attr_name) for typedef variables we are fetching attri

Re: Stack offset computation for incoming arguments.

Dear Eric, Really Appreciate your reply here and made the following changes like #define ARG_POINTER_REGNUM 8 //Fake hard reg #define FRAME _POINTER_REGNUM 9 // Fake hard reg #define SP_REG 10 #define ELIMINABLE_REGS { {ARG_POINTER_REGNUM,STACK_POINTER_REGNUM},\

Re: Stack offset computation for incoming arguments.

Dear Eric, As advised given by you ,we defind the following marcos like #define ARG_POINTER_REGNUM 9 #define FRAME_POINTER_REGNUM 8 #define STACK_POINTER_REGNUM 10 #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { FRAME_POINT

Re: Stack offset computation for incoming arguments.

Dear Eric, As advised given by you ,we defind the following marcos like #define ARG_POINTER_REGNUM 9 #define FRAME_POINTER_REGNUM 8 #define STACK_POINTER_REGNUM 10 #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { FRAME_POINT

ELIMINABLE_REGS and INITIAL_ELIMINATION_OFFSET effectiveness.

Dear All, We are porting 4.8.1 to the one of out private backend and defined the macros like #define ELIMINABLE_REGS \ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}\ #define INITIAL_ELIMINATION_O

error: unrecognizable insn:

Dear All, We are porting the gcc 4.8.1 for our private target . The compiler pops up with below error . error: unrecognizable insn: (insn 22 21 32 6 (set (reg:HI 30 [ D.1532 ]) (plus:HI (symbol_ref:HI ("stringArray") ) (const_int -1 [0x]))) -1 (nil)) altcon_014.c

Blcopy for outgoing arguments.

Hi All, Good day there. We are porting the gcc 4.8.1 and defined the calling conventions like If(sizeof(arg) < = 2) Pass with reg. Else Pass by stack. The problem is that the code is bloated for the

Change the calling conventions only for the intrinsic functions.

Hi All , We are porting GCC 4.8.1 for the customized hardware, where the current calling convention used as arguments are passed by stack and return value by register. But we do have some intrinsic functions(that are supplied by hardware folks ) which has the calling convention like both argu

Re: Stack offset computation for incoming arguments.

Thank you Eric for the inputs and will make the required changes. Thank you Again ~Umesh On Fri, Apr 25, 2014 at 9:58 PM, Eric Botcazou wrote: >> #define FIRST_PARM_OFFSET(FNDECL) (get_frame_size() + >> STARTING_FRAME_OFFSET + RETURN_BYTES ) > > I don't think that you can define FIRST_PARM_OFF

Variadic functions arguments passing

Hi All, In our private port ,we define function_arg hook to pass the first three args in the reg and rest will go to stack. But for variadic functions the arguments need to pass through the stack. How we can achieve this ?? Any inputs will be appreciate. Thank you ~Umesh

Stack offset computation for incoming arguments.

Hi All, Our private backend has the macro defined as #define FIRST_PARM_OFFSET(FNDECL) (get_frame_size() + STARTING_FRAME_OFFSET + RETURN_BYTES ) #define STARTING_FRAME_OFFSET 1 #define STACK_POINTER_REGNUM10 #define FRAME_POINTER_REGNUM STACK_POINTER_REGNUM #define ARG_POINTER_REGNUM

Re: Code emitted was bloated with no optimisation.

ley writes: >> On 04/10/2014 04:12 PM, Umesh Kalappa wrote: >> >>> Please somebody from the group can share their thoughts and will be >>> appricate the same. >> >> But unoptimized code is expected to be large. Why do you expect >> otherwise? > > S

Re: Code emitted was bloated with no optimisation.

, BC ld BC, DE ld HL, WA ld (SP+0), HL ld WA, 20 ld HL, (SP+0) ld (a+i), WA Anyidea why it so ?? Thank you in advance ~Umesh On Thu, Apr 10, 2014 at 8:54 PM, Andrew Haley wrote: > On 04/10/2014 04:12 PM, Umesh Kala

Code emitted was bloated with no optimisation.

Hi there, we ported gcc 4.8.1 to our ptivate target and the code is bloated for the array access as shown below C file : int a[10]; int i; test() { a[9] = 10; a[i] = 20; } xgcc -O2 -S test.c _test: ld (_a+18), 10 ;a[9] = 10; ld WA, (_i) ; a[i] = 20; add WA

-fleading-underscore is not working as expected.

Dear All , Was enabled the switch "-fleading-underscore" to emit the global symbol name with prefix _ . The respective C source file int a=10; int b=10,c; int test() { c =a+b ; tes(); return c ; } and respective asm file .global _a .section.dat

Re: RTL Optimisations

Wed, Mar 26, 2014 at 7:42 PM, Georg-Johann Lay wrote: > Am 03/25/2014 01:28 PM, schrieb Jeff Law: > >> On 03/25/14 06:23, Umesh Kalappa wrote: >>> >>> Dear All, >>> >>> The GCC source reference 4.8.1 will synthesized some of the double >>>

RTL Optimisations

Dear All, The GCC source reference 4.8.1 will synthesized some of the double word operations(SI mode) like add /sub in the below case from the word size (HI) patterns, (code snippet) expand_binop_directly function in the optabs.c. /* These can be done a word at a time by propagating carries. */

Re: Reg Alloc Problem.

BASE (preferred) for the r21 pseudo,i'm looking for the cause in our backend,but mean while anyone in the group can share there experience w.r.t that will help me to solve issue asap. Thank you ~Umesh On Wed, Mar 12, 2014 at 7:30 PM, Umesh Kalappa wrote: > Hi All, > > We are porting

New .rodata section.

Hi All , We are porting gcc4.8.1 to the new target and we created the new .rodata section w.r.t flags by get_unnamed_section() . Now we need to associate the global %object data of type .word or .byte to the created .rodata section and also we need to emit the .rodata section in the asm fil

Reg Alloc Problem.

Hi All, We are porting the gcc 4.8.1 to the new target and which has the pair 16 bit registers like AB or CD or EF and we modeled it in reg_class as AB,CD and DE 16 bit pair_regs and CD ,EF as 16 bit base_regs and A,B,C,D E and F as 8 bit as general_regs. We are stuck with below issues like

type promotion

Hi All, Was porting gcc 4.8.1 to the private target which has 8 bit regs and can be used as pair for 16bit like AB ,CD but not BC or AD. I was stuck in the type promotion like int i; unsigned char c; int test () { i =c; } defined the zero_extendqihi2 pattern for the above c construct lik

Enable debug info

Dear All, We need to support the debug info emit for our private port on gcc 4.8.1. I was in impression using option -g in the commandline by defualt ,will emit the dwarf debugging symbols and the info ,But i was wrong here. Anyone in the group point me some references or through some lights o

Re: Invalid code emitted

My bad Ian, Thanks for the input and the target was private and gcc 4.8.1 version used and your are on same page on reg pairing . Let me have a look on the port . Thanks Again ~Umesh On Tue, Jan 21, 2014 at 8:12 PM, Ian Lance Taylor wrote: > On Tue, Jan 21, 2014 at 12:52 AM, Umesh Kala

Invalid code emitted

Hi All , The following C code snippet unsigned char c ; int d ; int test () { d = c; return d; } below is the RTL without optimisation enabled (insn 6 5 0 (set (reg:QI 18 [ c.0 ]) (mem/c:QI (symbol_ref:HI ("c") ) [0 c+0 S1 A8])) cnv.c:5 -1 (nil)) (insn 7 6 8 (set (reg:QI 19

Unoptimal code.

Hi All, Below is the patterns defined for the mov and add instruction . [(set (match_operand:HI 0 "general_mov_operand" "=r,rRA") (match_operand:HI 1 "general_mov_operand" "rRAi,ri"))] "" { } ) (define_insn "addhi3" [(set (match_operand:HI 0 "register_operand" "=A

[Warning] Signed mistach for basic datatype.

Hi All , The below sample caught my attention i.e int a ; unsigned int b; int func() { return a =b; } the compiler didn't warn me about the signed mismatch in the above case. where as int *a ; unsigned int *b; int func() { a =b; return *a; } compiler warns me as warning: pointer targets in a

Make SImode as default mode for INT type.

Hi all, We are re-targeting the gcc 4.8.1 to the 16 bit core ,where word =int = short = pointer= 16 , char = 8 bit and long =32 bit. We model the above requirement as #define BITS_PER_UNIT 8 #define BITS_PER_WORD 16 #define UNITS_PER_WORD 2 #define POINTER_SIZE

Re: function attributes

Wed, Oct 16, 2013 at 2:26 PM, Nagaraju Mekala wrote: > Yes.. I still had no luck. > Do you have any thoughts on this?? > > On Wed, Oct 16, 2013 at 2:05 PM, Umesh Kalappa > wrote: >> You still stuck with this issue ??? >> >> ~Umesh >> >> On Tue,

Re: function attributes

You still stuck with this issue ??? ~Umesh On Tue, Oct 15, 2013 at 9:08 PM, Ian Lance Taylor wrote: > On Tue, Oct 15, 2013 at 8:04 AM, Nagaraju Mekala > wrote: >> Hi Ian, >> >> Thanks for the reply. >> >> On Fri, Oct 11, 2013 at 10:31 PM, Ian Lance Taylor wrote: >>> On Fri, Oct 11, 2013 at

GCC IRA support for Register Banks.

Dear All, Did gcc provide any hook to support register bank like Our private target has two banks of register file like A and B registers under Bank-0 and A and B (same name weired ha ) registers under Bank-1. asm sample like load A ,mem-0//By default the register referred from ba

Re: GCC retargeting

me and i'm really pardon me for bothering you guys here. Thanks and waiting for someone from expert group to through some lights here ~Umesh On Wed, Oct 9, 2013 at 7:40 PM, wrote: > > > On Oct 9, 2013, at 5:24 AM, Umesh Kalappa wrote: > > > Dear Group , > > >

GCC retargeting

Dear Group , We are re-targeting the GCC to the CISC target ,which has the eight 8-bit registers and same register set can used as pair register for 16 bit computation i.e four 16-bits . Any one in the group tell me ,How do i model this requirement using the target macros like REG_CLASS_NA

cortex-m3(gcc.4.6.3)

Dear Group, The below asm is generated for target cortex-m3 (gcc-4.6.3) main: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 push {r3, r4, r5, lr} bl vAlgTNoOptimize movs r0, #170 bl vFnCall bl vAlgTOptimize ldr r4, .L22 add

Invalid store semantics

Dear All, I'm looking up the below problem in our private backend. During the RTL expansion the below rtl has been emitted.. (insn 6 5 7 (set (reg:SI 23) (const_int 10 [0xa])) algt_001.c:41 -1 (nil)) (insn 7 6 8 (set (reg:SI 24) (unspec:SI [ (mem/c/i:SI (symbol_ref:SI ("lsucCnt2.1746") [flags 0

RTL insns set differences

Dear Group, Need a favour from you all ,Im very new to gcc framework such and learning the same , I was looking at the RTL insns sets by dumping the c.144.exapnd dump file before reload pass for the various target and I do see the difference in the RTL insns set for two different targets for below