On Thu, 2020-10-22 at 18:03 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Map IEEE 128-bit long double built-in functions
>
> This patch is revised from the first and second versions of the patch posted.
> It now uses the names that are not in the user's namespace (i.e. __sinieee128
>
for trunk?
THanks,
-Will
PR target/91903
2020-10-26 Will Schmidt
gcc/ChangeLog:
* config/rs6000/rs6000-call.c (rs6000_expand_binup_builtin): Add
clauses for CODE_FOR_vsx_xvcvuxddp_scale and
CODE_FOR_vsx_xvcvsxddp_scale to the parameter checking code.
gcc/testsuite/ChangeLog
[PATCH 2/2, rs6000, v2] VSX load/store rightmost element operations
Hi,
This adds support for the VSX load/store rightmost element operations.
This includes the instructions lxvrbx, lxvrhx, lxvrwx, lxvrdx,
stxvrbx, stxvrhx, stxvrwx, stxvrdx; And the builtins
vec_xl_sext() /* vector load sign
On Thu, 2020-10-08 at 09:36 +1030, Alan Modra via Gcc-patches wrote:
> Implement more two insn constants. rotate_and_mask_constant covers
> 64-bit constants that can be formed by rotating a 16-bit signed
> constant, rotating a 16-bit signed constant masked on left or right
> (rldicl and rldicr),
On Thu, 2020-10-08 at 09:27 +1030, Alan Modra via Gcc-patches wrote:
> The aim of this patch is to make rtx_costs for SETs closer to
> insn_cost for SETs. One visible effect on powerpc code is increased
> if-conversion.
>
> * config/rs6000/rs6000.c (rs6000_rtx_costs): Reduce cost of SET
>
On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will, Segher:
>
> This patch adds support for converting to/from 128-bit integers and
> 128-bit decimal floating point formats using the new P10 instructions
> dcffixqq and dctfixqq. The new instructions are only used on P10 HW,
> otherwise
On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will, Segher:
>
> Patch 4 adds the vector 128-bit integer shift instruction support for
> the V1TI type.
>
> The changes from the previous version include:
>
> Fixed up the change log entry issues noted by Will.
>
> Regression tests reran
On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will, Segher:
>
> Add support for converting to/from 128-bit integers and 128-bit
> decimal floating point formats.
>
> The updates from the previous version of the patch:
>
> Just a fix for the change log per Will's comments.
>
> No
On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will and Segher:
>
> This is the rest of the second patch which adds the 128-bit integer
> support for divide, modulo, shift, compare of 128-bit
> integers instructions and builtin support.
>
> In the last round of changes, the flag for the
On Mon, 2020-10-05 at 11:52 -0700, Carl Love wrote:
> Will, Segher:
>
>
>
> The following changes were made from the previous version:
>
> Per Will's comments, I split the bug fix from patch 2 into a separate
> patch. This patch is the bug fix for the vec_rlnm builtin.
I recommend trying to
On Mon, 2020-10-05 at 11:51 -0700, Carl Love wrote:
> Will, Segher:
>
> Patch 1, adds the 128-bit sign extension instruction support and
> corresponding builtin support.
>
> I updated the change log per the comments from Will.
>
> Patch has been retested on Power 9 LE.
>
> Pet me know if it
Hi,
Rename our BU_P10_MISC_2 built-in define macro to be
BU_P10_POWERPC64_MISC_2. This more accurately reflects
that the macro includes the RS6000_BTM_POWERPC64 entry
that is not present in the other BU_P10_MISC macros,
and matches the style we used for the P7 equivalent.
Should be
On Mon, 2020-10-05 at 17:23 -0300, Tulio Magno Quites Machado Filho via
Gcc-patches wrote:
> Ping?
+cc Segher :-)
>
> Tulio Magno Quites Machado Filho via Gcc-patches
> writes:
>
> > Replace them with a whitespace in order to avoid artifacts in the HTML
> > document.
> >
> > 2020-08-19
On Fri, 2020-09-04 at 12:52 -0300, Raoni Fassina Firmino via Gcc-patches wrote:
> Changes since v1[1]:
> - Fixed english spelling;
> - Fixed code-style;
> - Changed match operand predicate in feclearexcept and feraiseexcept;
> - Changed testcase options;
> - Minor changes in test code to
On 9/25/20 6:50 PM, Segher Boessenkool wrote:
On Fri, Sep 25, 2020 at 03:34:49PM -0500, will schmidt wrote:
On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote:
No, it cannot.
This is used for pdepd/pextd/cntlzdm/cnttzdm/cfuged, all of which do
need 64-bit registers to do anything
On Fri, 2020-09-25 at 12:36 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Sep 24, 2020 at 03:35:24PM -0500, will schmidt wrote:
> > We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the
> > define for
> > our P10 MISC 2 builtin definition. This do
On Thu, 2020-09-24 at 19:40 -0500, Segher Boessenkool wrote:
> On Thu, Sep 24, 2020 at 11:04:38AM -0500, will schmidt wrote:
> > [PATCH 2/2, rs6000] VSX load/store rightmost element operations
> >
> > Hi,
> > This adds support for the VSX load/store right
[PATCH, rs6000] correct an erroneous blip in the BU_P10_MISC define
Hi,
We have extraneous BTM entry (RS6000_BTM_POWERPC64) in the define for
our P10 MISC 2 builtin definition. This does not exist for the '0',
'1' or '3' definitions. It appears to me that this was erroneously
copied from
On Mon, 2020-09-21 at 16:57 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 5 adds the 128-bit integer to/from 128-floating point
> conversions. This patch has to invoke the routines to use the 128-
> bit
> hardware instructions if on Power 10 or use software routines if
> running on a pre
On Mon, 2020-09-21 at 16:56 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 4 adds the vector 128-bit integer shift instruction support for
> the V1TI type.
>
> The following changes were made from the previous version.
>
> Renamed VSX_TI to VEC_TI, put def in vector.md. Didn't get it
>
On Mon, 2020-09-21 at 16:56 -0700, Carl Love wrote:
> Segher, Will:
>
> Add support for converting to/from 128-bit integers and 128-bit
> decimal floating point formats.
A more wordy blurb here clarifying what the patch does would be useful.
i.e. this adds support for dcffixqq and dctfixqq
On Mon, 2020-09-21 at 16:56 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 1, adds the 128-bit sign extension instruction support and
> corresponding builtin support.
>
> No changes from the previous version.
>
> The patch has been tested on
>
> powerpc64le-unknown-linux-gnu (Power 9 LE)
On Mon, 2020-09-21 at 16:56 -0700, Carl Love wrote:
> Will, Segher:
>
> Add support for divide, modulo, shift, compare of 128-bit
> integers instructions and builtin support.
>
> The following are the changes from the previous version of the patch.
>
> The TARGET_TI_VECTOR_OPS was removed per
[PATCH 2/2, rs6000] VSX load/store rightmost element operations
Hi,
This adds support for the VSX load/store rightmost element operations.
This includes the instructions lxvrbx, lxvrhx, lxvrwx, lxvrdx,
stxvrbx, stxvrhx, stxvrwx, stxvrdx; And the builtins
vec_xl_sext() /* vector load sign extend
[PATCH, rs6000] int128 sign extention instructions (partial prereq)
Hi
This is a sub-set of the 128-bit sign extension support patch series
that I believe will be fully implemented in a subsequent patch from Carl.
This is a necessary pre-requisite for the vector-load/store rightmost
element
On Tue, 2020-08-11 at 12:23 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 5 adds the 128-bit integer to/from 128-floating point
> conversions. This patch has to invoke the routines to use the 128-bit
> hardware instructions if on Power 10 or use software routines if
> running on a pre Power
On 9/16/20 12:09 PM, Segher Boessenkool wrote:
On Wed, Sep 16, 2020 at 08:36:35AM -0500, Bill Schmidt wrote:
This is a cleanup requested by Segher in a previous review. Most
uses of rs6000_pcrel_p are called for the current function. A
specialized version for cfun is more efficient
think it's worth keeping
around in case we have a late discovery where we need it.)
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for trunk?
Thanks,
Bill
2020-09-16 Bill Schmidt
gcc/
* config/rs6000/predicates.md
On 9/16/20 5:32 AM, Segher Boessenkool wrote:
On Tue, Sep 15, 2020 at 08:38:42PM -0500, Bill Schmidt wrote:
The description in rs6000-builtin.def provides for a builtin named
__builtin_altivec_xst_len_r. However, it is hand-defined in
altivec_init_builtins as __builtin_xst_len_r, against
; committed as obvious.
2020-09-15 Bill Schmidt
gcc/
* config/rs6000/rs6000-call.c (altivec_init_builtins): Fix name
of __builtin_altivec_xst_len_r.
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 77c7a1149fb..a8b520834c7 100644
--- a/gcc
On Tue, 2020-09-15 at 10:49 +0930, Alan Modra via Gcc-patches wrote:
> The existing "case AND" in this function is not sufficient for
> optabs.c:avoid_expensive_constant usage, where the AND is passed in
> outer_code.
>
> * config/rs6000/rs6000.c (rs6000_rtx_costs): Move costing for
>
On Tue, 2020-09-15 at 10:49 +0930, Alan Modra via Gcc-patches wrote:
> This patch series fixes a number of issues in rs6000_rtx_costs, the
> aim being to provide costing somewhat closer to reality. Probably
> the
> most important patch of the series is patch 4, which just adds a
> comment.
On Fri, 2020-09-11 at 12:37 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Sep 11, 2020 at 09:44:54AM -0500, will schmidt wrote:
> > As reported, the recently added pr96139 tests will fail on older
> > targets
> > because the tests are missing the app
Hi,
As reported, the recently added pr96139 tests will fail on older targets
because the tests are missing the appropriate -mvsx or -maltivec options.
This adds the options and clarifies the dg-require statements.
sniff-regtested OK when specifying older targets
On Fri, 2020-09-04 at 03:47 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Sep 04, 2020 at 08:55:43AM +0200, Richard Biener wrote:
> > On Thu, Sep 3, 2020 at 8:10 PM Segher Boessenkool
> > wrote:
> > > On Thu, Sep 03, 2020 at 10:37:33AM -0500, will schmidt wro
On Wed, 2020-09-02 at 05:13 -0500, Segher Boessenkool wrote:
> Hi Will,
>
> On Tue, Sep 01, 2020 at 09:00:20PM -0500, will schmidt wrote:
> > This corrects an issue with the powerpc vector long long
> > subtypes.
> > As reported by SjMunroe in PR96139. When buildi
y regtested on assorted power7,power8,
power8 targets. Another sniff test in the queue to verify a last
minute testcase tweak.
OK for trunk?
Thanks
-Will
PR target/96139
2020-09-01 Will Schmidt
gcc/Changelog:
* config/rs6000/rs6000-call.c (rs6000_init_b
On Mon, 2020-08-31 at 14:43 +0800, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> Power9 supports vector with length in bytes load/store, this patch
> is to teach check_effective_target_vect_len_load_store to take it
> and its laters as effective vector with length targets.
>
> Also supplement the
On Mon, 2020-08-31 at 04:06 -0500, Xiong Hu Luo via Gcc-patches wrote:
> vec_insert accepts 3 arguments, arg0 is input vector, arg1 is the value
> to be insert, arg2 is the place to insert arg1 to arg0. This patch adds
> __builtin_vec_insert_v4si[v4sf,v2di,v2df,v8hi,v16qi] for vec_insert to
> not
On Fri, 2020-08-28 at 08:08 -0700, Carl Love wrote:
> GCC maintainers:
>
Hi,
> The defines for vec_popcnt, bvec_popcnth, vec_popcntw, vec_popcntd in
s/bvec/vec/
> gcc/config/rs6000/altivec.h are not listed in the Power 64-Bi ELF V2
> ABI specification revision 1.4, May 10, 2017. They are
It turns out that the target hook that this is supposed to satisfy
disappeared in 2004. Probably time to retire it.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions; committed as obvious.
Thanks,
Bill
2020-08-28 Bill Schmidt
gcc/
* config/rs6000/rs6000
Remove unnecessary tests before copying function address to r12, as
requested by Segher.
Bootstrapped and tested on powerpc64le-unknown-linx-gnu with no
regressions, committed as obvious.
Thanks,
Bill
2020-08-28 Bill Schmidt
gcc/
* config/rs6000/rs6000.c (rs6000_call_aix): Remove
On 8/28/20 7:25 AM, Alan Modra wrote:
On Fri, Aug 28, 2020 at 01:17:27AM -0500, Segher Boessenkool wrote:
1) Very many unnecessary moves are generated during expand *anyway*, a
few more will not hurt;
2) In practice we always generate a move from a pseudo into r12 here,
never a copy from r12
On Wed, 2020-08-26 at 22:46 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Add power10 xscmp{eq,gt,ge}qp support.
>
> This patch adds the conditional move support. In adding the conditional move
> support, the optimizers will be able to convert things like:
>
> a = (b > c) ? b
On Wed, 2020-08-26 at 22:45 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Add power10 xsmaxcqp/xsmincqp support.
>
> This patch adds support for the ISA 3.1 (power10) IEEE 128-bit "C" minimum and
> maximum functions. Because of the NaN differences, the built-in functions
> will
>
On Wed, 2020-08-26 at 22:44 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Rename functions for min, max, cmove.
>
> This patch renames the functions that generate the ISA 3.0 C minimum, C
> maximum, and conditional move instructions to use a better name than just
> using
> a _p9
On Wed, 2020-08-26 at 22:43 -0400, Michael Meissner via Gcc-patches wrote:
> PowerPC: Change cmove function return to bool.
>
> In doing the other work for adding ISA 3.1 128-bit minimum, maximum, and
> conditional move support, I noticed the two functions that process conditional
> moves return
Hi!
On 8/27/20 1:41 PM, Segher Boessenkool wrote:
Hi!
On Thu, Aug 27, 2020 at 08:21:34AM -0500, Bill Schmidt wrote:
+ /* For ELFv2, r12 and CTR need to hold the function address
+ for an indirect call. */
+ if (GET_CODE (func_desc) != SYMBOL_REF && DEFAULT_ABI == A
Prior to P10, ELFv2 hasn't implemented nonlocal sibcalls. Now that we do,
we need to be sure that r12 is set up prior to such a call.
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no
regressions. Is this okay for trunk?
Thanks,
Bill
2020-08-27 Bill Schmidt
gcc/
PR
On Mon, 2020-08-24 at 14:39 -0700, Carl Love wrote:
> Segher:
>
> On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> > On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > > I think your current code is fine; I hadn't
On 8/24/20 11:01 PM, Michael Meissner wrote:
On Sat, Aug 22, 2020 at 07:05:51PM -0500, Bill Schmidt wrote:
What is necessary in order to allow this optimization to occur
earlier is to make this hidden dependency explicit. When the
relocation is inserted, we have to change the "pld" i
On 8/20/20 6:33 PM, Segher Boessenkool wrote:
Hi!
On Tue, Aug 18, 2020 at 02:31:41AM -0400, Michael Meissner wrote:
In order to do this, the pass that converts the load address and load/store
must occur late in the compilation cycle.
That does not follow afaics.
Let me see if I can help
I failed to mention that this has been bootstrapped and tested on
powerpc64le-unknown-linux-gnu, with no regressions. Is this ok for trunk?
Thanks,
Bill
On 8/19/20 9:40 AM, Bill Schmidt via Gcc-patches wrote:
A function compiled with the PC-relative addressing model does not
require r2
cannot make a sibcall to a callee that
does not.
2020-08-19 Bill Schmidt
gcc/
* config/rs6000/rs6000-logue.c (rs6000_decl_ok_for_sibcall):
Sibcalls are always legal when the caller doesn't preserve r2.
gcc/testsuite/
* gcc.target/powerpc/pcrel-sibcall-1.c: Adjust
On 8/17/20 12:13 PM, Carl Love wrote:
Segher, Bill, Peter:
On Fri, 2020-08-14 at 19:42 -0500, Segher Boessenkool wrote:
Do the names agree with the (future) documentation now?
Did not double check on the documentation.
Someone should...
Looking at the box document "Proposed function
On Fri, 2020-08-14 at 17:59 -0500, Aaron Sawdey via Gcc-patches wrote:
Hi,
> This patch adds a few new instructions to inline expansion of
> memcpy/memmove. Generation of all these is controlled by
s/is/are/ ?
> the option -mblock-ops-unaligned-vsx which is set on by default if the
> target
On Tue, 2020-08-11 at 12:23 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 5 adds the 128-bit integer to/from 128-floating point
> conversions. This patch has to invoke the routines to use the 128-bit
> hardware instructions if on Power 10 or use software routines if
> running on a pre Power
On Tue, 2020-08-11 at 12:23 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 4 adds 128-bit integer shift instruction support.
I suggest having a few more words here to better describe what this
patch is doing.
i.e.
This is adding the VEC_I128 iterator which contains the V1TI and TI
types,
On Tue, 2020-08-11 at 12:22 -0700, Carl Love wrote:
> Segher, Will:
>
> Path 3 adds support for converting to/from 128-bit integers and 128-bit
> decimal floating point formats.
>
> Carl Love
>
Some cosmetic comments below. overall lgtm.
Thanks,
-Will
>
>
On Thu, 2020-08-13 at 17:55 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Aug 13, 2020 at 05:11:11PM -0500, will schmidt wrote:
> > > > That is probably a level of detail that is not
> > > > really needed in the GCC code comment. Probably best to just
&
On Tue, 2020-08-11 at 12:22 -0700, Carl Love wrote:
> Segher, Will:
>
> Patch 2, adds support for divide, modulo, shift, compare of 128-bit
> integers. The support adds the instruction and builtin support.
>
> Carl Love
>
>
>
On Thu, 2020-08-13 at 13:29 -0500, Segher Boessenkool wrote:
> On Thu, Aug 13, 2020 at 11:09:10AM -0700, Carl Love wrote:
> > The builtins
> >
> > vector signed int vec_signexti (vector signed char a)
> > vector signed long long vec_signextll (vector signed char a)
> > vector signed int
On 8/13/20 2:24 PM, Carl Love wrote:
Bill:
On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote:
Hi Carl,
Thanks for cleaning up the consistency issue. The new names and
related
adjustments LGTM.
Are there no affected test cases that need adjusting? That
surprises
me. For example, didn't
On 8/13/20 11:12 AM, Carl Love wrote:
GCC maintainers:
The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
XVCVSPBF16 need to be restricted to P10.
The macro expansions BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3 expand
the name field as "__builtin_altivec_". These macro
On 8/10/20 3:30 AM, Jonathan Wakely via Gcc wrote:
Hi Matt,
The best thing to do here is file a bug report with the code to reproduce it:
https://gcc.gnu.org/bugzill
Thanks
Also, be sure to follow the instructions at https://gcc.gnu.org/bugs/.
Bill
On Sat, 8 Aug 2020 at 23:01, Soul
On 7/30/20 12:15 PM, will schmidt wrote:
On Mon, 2020-07-27 at 09:14 -0500, Bill Schmidt wrote:
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add power9,
power9-vector, and power9-64 builtins.
---
gcc/config/rs6000/rs6000-builtin
On Mon, 2020-07-27 at 09:14 -0500, Bill Schmidt wrote:
> From: Bill Schmidt
>
> 2020-07-26 Bill Schmidt
>
> * config/rs6000/rs6000-builtin-new.def: Add power9,
> power9-vector, and power9-64 builtins.
> ---
> gcc/config/rs6000/rs60
tests on powerpc64le-unknown-linux-gnu Power8LE, with
other regression tests still in progress on some other powerpc platforms.
OK for trunk?
Thanks,
-Will
[gcc]
2020-07-29 Will Schmidt
* config/rs6000/altivec.h (vec_test_lsbb_all_ones): New define.
(vec_test_lsbb_all_zeros): New
On Tue, 2020-05-26 at 11:12 -0500, will schmidt via Gcc-patches wrote:
> Hi,
>
> Add support for new instructions to test LSB by Byte.
>
> Tested on powerpc64le-unknown-linux-gnu with no
> regressions. (power7BE, power8LE, power8BE, power9LE).
Ping.
I note that I'
.
Meantime, please reply to wschm...@linux.ibm.com for this patch series.
Thanks!
Bill
Forwarded Message
Subject: [PATCH 00/29] rs6000: Auto-generate builtins from descriptions
[V2]
Date: Mon, 27 Jul 2020 09:13:46 -0500
From: Bill Schmidt
To: gcc-patches@
Just a reminder this patch series exists and wants a review. :-)
Bill
On 7/27/20 9:13 AM, Bill Schmidt wrote:
From: Bill Schmidt
This is a slight reworking of the patches posted on June 17. I have
made a couple of improvements, but the general arrangement of the patches
is the same
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin.def: Add comments.
* config/rs6000/rs6000-call.c: Likewise.
---
gcc/config/rs6000/rs6000-builtin.def | 15 +++
gcc/config/rs6000/rs6000-call.c | 166 +++
2 files changed
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-call.c (rs6000-builtins.h): New #include.
(rs6000_init_builtins): Call rs6000_autoinit_builtins.
---
gcc/config/rs6000/rs6000-call.c | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/rs6000
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add ieee128-hw, dfp,
crypto, and htm builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 217 +++
1 file changed, 217 insertions(+)
diff --git a/gcc/config/rs6000
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add power8-vector
builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 417 +++
1 file changed, 417 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add power9,
power9-vector, and power9-64 builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 354 +++
1 file changed, 354 insertions(+)
diff --git a/gcc/config/rs6000
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add remaining AltiVec
builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 843 +++
1 file changed, 843 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (ovld_stanza): New struct.
(MAXOVLDSTANZAS): New defined constant.
(ovld_stanzas): New filescope variable.
(curr_ovld_stanza): Likewise.
(MAXOVLDS): New defined constant
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config.gcc (powerpc*-*-*): Add rs6000-builtins.o to extra_objs.
* config/rs6000/t-rs6000 (rs6000-gen-builtins.o): New target.
(rbtree.o): Likewise.
(rs6000-gen-builtins): Likewise.
(rs6000-builtins.c
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add power7 and
power7-64 builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 39
1 file changed, 39 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (write_fntype): New
function.
(write_fntype_init): New stub function.
(write_init_bif_table): Likewise.
(write_init_ovld_table): New function.
(write_init_file
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add VSX builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 840 +++
1 file changed, 840 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def
b/gcc/config
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (write_defines_file):
Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c
b/gcc/config/rs6000
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (complete_vector_type): New
function.
(complete_base_type): Likewise.
(construct_fntype_id): Likewise.
(parse_bif_entry): Call construct_fntype_id
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (write_init_bif_table):
Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 153
1 file changed, 153 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-gen
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c
(write_autogenerated_header): New function.
(write_bif_enum): Likewise.
(write_ovld_enum): Likewise.
(write_decls): Likewise.
(write_extern_fntype): Likewise
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (parse_bif_attrs):
Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 86 +
1 file changed, 86 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (typemap): New struct.
(TYPE_MAP_SIZE): New defined constant.
(type_map): New filescope variable; initialize.
(map_token_to_type_node): New function.
(write_type_node
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: Add always, power5,
and power6 builtins.
---
gcc/config/rs6000/rs6000-builtin-new.def | 78
1 file changed, 78 insertions(+)
diff --git a/gcc/config/rs6000/rs6000
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (parse_args): New function.
(parse_prototype): Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 143
1 file changed, 143 insertions(+)
diff --git a/gcc/config
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (MININT): New defined
constant.
(exit_codes): New enum.
(consume_whitespace): New function.
(advance_line): Likewise.
(safe_inc_pos): Likewise
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (void_status): New enum.
(basetype): Likewise.
(typeinfo): New struct.
(handle_pointer): New function.
(match_basetype): New stub function
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rbtree.c: New file.
* config/rs6000/rbtree.h: New file.
---
gcc/config/rs6000/rbtree.c | 233 +
gcc/config/rs6000/rbtree.h | 51
2 files changed, 284 insertions
From: Bill Schmidt
This patch adds a tiny subset of the built-in and overload descriptions.
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-builtin-new.def: New.
* config/rs6000/rs6000-overload.def: New.
---
gcc/config/rs6000/rs6000-builtin-new.def | 179
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (match_basetype):
Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c
b
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (rbtree.h): New #include.
(num_bifs): Likewise.
(num_ovld_stanzas): Likewise.
(num_ovlds): Likewise.
(exit_codes): Add more enum values.
(parse_codes): New enum
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (bif_file): New filescope
variable.
(ovld_file): Likewise.
(header_file): Likewise.
(init_file): Likewise.
(defines_file): Likewise.
(pgm_path): Likewise
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (restriction): New enum.
(typeinfo): Add restriction field.
(match_const_restriction): Implement.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 136
1 file
From: Bill Schmidt
Add header commentary explaining the purpose of rs6000-gen-builtins.c,
along with an initial set of includes.
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c: New.
---
gcc/config/rs6000/rs6000-gen-builtins.c | 141
1 file
From: Bill Schmidt
2020-07-26 Bill Schmidt
* config/rs6000/rs6000-gen-builtins.c (bif_stanza): New enum.
(curr_bif_stanza): Likewise.
(stanza_entry): New struct.
(stanza_map): New initialized filescope variable.
(enable_string): Likewise
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