-Original Message-
From: Hans-Peter Nilsson [mailto:h...@bitrange.com]
Sent: 26 March 2013 17:43
To: Paulo Matos
Cc: gcc@gcc.gnu.org
Subject: RE: Modeling predicate registers with more than one bit
What do you mean by source modes?
The SI and HI in subsi3 and subhi3. IIRC you
-Original Message-
From: Hans-Peter Nilsson [mailto:h...@bitrange.com]
Sent: 26 March 2013 17:43
To: Paulo Matos
Cc: gcc@gcc.gnu.org
Subject: RE: Modeling predicate registers with more than one bit
Unfortunately undocumented, but UTSL, for example
gcc/config/mips/mips-modes.def
Hi, sorry for the delay of this reply but just returned from paternity leave.
Have you had a look at the SH backend? SH cores have a T Bit
register, which functions as carry bit, over/underflow, comparison
result and branch condition register. In the SH backend it's treated as
a fixed
Hi, sorry for the delay of this reply but just returned from paternity leave.
-Original Message-
From: Hans-Peter Nilsson [mailto:h...@bitrange.com]
Sent: 05 March 2013 01:45
To: Paulo Matos
Cc: gcc@gcc.gnu.org
Subject: Re: Modeling predicate registers with more than one bit
On Tue, 26 Mar 2013, Paulo Matos wrote:
-Original Message-
From: Hans-Peter Nilsson [mailto:h...@bitrange.com]
Sent: 05 March 2013 01:45
To: Paulo Matos
Cc: gcc@gcc.gnu.org
Subject: Re: Modeling predicate registers with more than one bit
Except for CCmodes being dependent
On Thu, 28 Feb 2013, Paulo Matos wrote:
Hello,
I am looking at how to correctly model in GCC predicate
registers that have more than one bit and the value set into to
the predicate register after a comparison depends on the size
of the comparison.
I have looked into GCC backends but
Hi,
On Thu, 2013-02-28 at 11:10 +, Paulo Matos wrote:
Hello,
I am looking at how to correctly model in GCC predicate registers that
have more than one bit and the value set into to the predicate register
after a comparison depends on the size of the comparison.
I have looked into GCC
