Add compatibility implementations of _mm_blend_epi16 and _mm_blendv_epi8
intrinsics.
Respective test cases are copied almost verbatim (minor changes to
the dejagnu head lines) from i386.
2019-07-19 Paul A. Clarke
[gcc]
* config/rs6000/smmintrin.h (_mm_blend_epi16): New.
This Go frontend patch by Than McIntosh stops exporting bodies for
functions marked "go:noinline". The current Mark_inline_candidates
helper looks only at budget when deciding to mark a function or method
as inline (with the proviso that IR constructs not yet supported by
the inliner are given
On targets with permissive alignment requirements GCC sometimes
lowers stores of short (between two and 16 bytes), power-of-two
char sequences to single integer stores of the corresponding
width. This happens for sequences of ordinary character stores
as well as for some calls to memcpy.
It sounds reasonable to overload std::copy_n for istreambuf_iterator.
* include/bits/stl_algo.h (copy_n(istreambuf_iterator<>, _Size,
_OIte)):
New declaration.
* include/bits/streambuf_iterator.h (istreambuf_iterator<>): Declare
std::copy_n for istreambuf_iterator of char types
(2nd sent attempt as text this time.)
Good spot, fixed with attached patch, committed as trivial.
2019-07-19 François Dumont
* include/bits/stl_tempbuf.h (__detail::__return_temporary_buffer): Fix
sized deallocation size computation.
On 7/19/19 9:46 PM, Morwenn Ed wrote:
If I'm not
Hi Steve,
On Sun, Jul 14, 2019 at 12:07:58PM +0200, Thomas Koenig wrote:
OK, so here is a new version.
I think the discussion has shown that enlaring the buffer makes sense,
and that the buffer size for unformatted seems to be too bad.
I've reversed the names of the environment variables
This strips out (%< wise) a few driver specs that are only specifying a default
state.
Also warn on an option now ignored, and add some comments to the driver specs
section. Update the comments to explain why we can’t process all the driver
specs
here.
Tested on x86-64-darwin,
applied to
If I'm not mistaken this patch allocates N*sizeof(_Tp) bytes of storage and
deallocates N bytes when sized deallocation is enabled?
Shouldn't __return_temporary_buffer deallocate N*sizeof(_Tp) instead to match
the value passed to new?
De :
Segher Boessenkool writes:
> On Fri, Jul 19, 2019 at 10:55:59AM +0100, Richard Sandiford wrote:
>> Jozef Lawrynowicz writes:
>> > Is the downside of this macro implementation compared to a DEFHOOKPOD
>> > mainly
>> > just the maintainability/readability of the added code?
>>
>> Macros are
Steve Ellcey writes:
> Here is version two of my patch to fix simd attribute handling on
> aarch64. Unlike the first patch where I swapped the order of the
> calls to targetm.simd_clone.adjust and simd_clone_adjust_return_type,
> in this one I remove the (conditional) call to
While looking at BZ 80576 I realized a few things.
First for STRNCPY we know the exact count of bytes written and we can
treat it just like MEMCPY and others, both in terms of removing/trimming
them and in terms of using them to allow removal of other stores.
This patch adds support for those
On Fri, Jul 19, 2019 at 10:55:59AM +0100, Richard Sandiford wrote:
> Jozef Lawrynowicz writes:
> > Is the downside of this macro implementation compared to a DEFHOOKPOD mainly
> > just the maintainability/readability of the added code?
>
> Macros are essentially the "old way" and target hooks
Here is version two of my patch to fix simd attribute handling on
aarch64. Unlike the first patch where I swapped the order of the
calls to targetm.simd_clone.adjust and simd_clone_adjust_return_type,
in this one I remove the (conditional) call to build_distinct_type_copy
from
Hi!
On Fri, Jul 19, 2019 at 10:21:06AM +0800, Kewen.Lin wrote:
> on 2019/7/19 上午3:48, Segher Boessenkool wrote:
> > On Thu, Jul 18, 2019 at 01:44:36PM +0800, Kewen.Lin wrote:
> >> on 2019/7/17 下午9:40, Segher Boessenkool wrote:
> >>> On Wed, Jul 17, 2019 at 04:32:15PM +0800, Kewen.Lin wrote:
>
As suggested by Jakub in the PR, add missing vector one_cmpl2 to
mmx.md. A generic fix is in the works by Jakub.
2019-07-19 Uroš Bizjak
PR target/91204
* config/i386/mmx.md (one_cmpl2): New expander.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to
Hi,
this patch fixes bug in recursive_inlining noticed by Feng Xue.
Bootstrapped/regtested x86_64-linux, comitted.
Honza
Index: ChangeLog
===
--- ChangeLog (revision 273602)
+++ ChangeLog (working copy)
@@ -1,3 +1,8 @@
Hi,
this patch adds bare bones of disambiguation of access paths via
ARRAY_REF. Similarly to COMPONENT_REF we need a matched ARRAY_REF size
and prove that indexes are actually different.
This adds about 20 new disambiguations to tramp3d.
Bootstrapped/regtested x86_64-linux, OK?
*
On 14.06.19 15:09, Gaius Mulley wrote:
>
> Hello,
>
> here is version two of the patches which introduce Modula-2 into the
> GCC trunk. The patches include:
>
> (*) a patch to allow all front ends to register a lang spec function.
>(included are patches for all front ends to provide
Ping.
On Fri, Jul 12, 2019 at 04:16:38PM -0400, Marek Polacek wrote:
> In order to fix 89906 in GCC 8, we need to backport 86098.
> I think the patch is safe to be backported.
>
> Tested x86_64-linux, ok for 8?
>
> 2018-06-12 Jason Merrill
>
> PR c++/86098 - ICE with template
Not really my area, but FWIW...
Prathamesh Kulkarni writes:
> Hi,
> The attached patch tries to fix PR91166.
> Does it look OK ?
> Bootstrap+test in progress on aarch64-linux-gnu and x86_64-unknown-linux-gnu.
>
> Thanks,
> Prathamesh
>
> 2019-07-17 Prathamesh Kulkarni
>
> PR
On 19/07/2019 12:35, Richard Biener wrote:
On Fri, 19 Jul 2019, Andre Vieira (lists) wrote:
On 15/07/2019 11:54, Richard Biener wrote:
On Mon, 15 Jul 2019, Andre Vieira (lists) wrote:
On 12/07/2019 11:19, Richard Biener wrote:
On Thu, 11 Jul 2019, Andre Vieira (lists) wrote:
I
Another issue in partial-def VN.
Bootstrap / regtest running on x86_64-unknown-linux-gnu.
Richard.
2019-07-19 Richard Biener
PR tree-optimization/91211
* tree-ssa-sccvn.c (vn_walk_cb_data::push_partial_def): Fix
memset encoding size.
*
The following fixes cselim.
Bootstrapped/tested on x86_64-unknown-linux-gnu, applied.
Richard.
2019-07-19 Richard Biener
PR tree-optimization/91200
* tree-ssa-phiopt.c (cond_store_replacement): Check we have
no PHI nodes in middle-bb.
*
On Fri, 19 Jul 2019, Andre Vieira (lists) wrote:
>
>
> On 15/07/2019 11:54, Richard Biener wrote:
> > On Mon, 15 Jul 2019, Andre Vieira (lists) wrote:
> >
> > >
> > >
> > > On 12/07/2019 11:19, Richard Biener wrote:
> > > > On Thu, 11 Jul 2019, Andre Vieira (lists) wrote:
> > >
> > >
> > >
Cleanup the logical DImode operations since the current implementation is way
too complicated. Thumb-1, Thumb-2, VFP/Neon and iwMMXt all work differently,
resulting in a bewildering number of expansions, patterns and splits across
several md files. All this complexity is counterproductive and
After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags. The associated macro was already
__ARM_FEATURE_SVE2_BITPERM, so only the feature flag itself
needs to change.
Tested on aarch64-linux-gnu and
On 15/07/2019 11:54, Richard Biener wrote:
On Mon, 15 Jul 2019, Andre Vieira (lists) wrote:
On 12/07/2019 11:19, Richard Biener wrote:
On Thu, 11 Jul 2019, Andre Vieira (lists) wrote:
I have code that can split the condition and alias checks in
'vect_loop_versioning'. For this
On Fri, 19 Jul 2019 10:55:59 +0100
Richard Sandiford wrote:
> Jozef Lawrynowicz writes:
> > On Fri, 19 Jul 2019 09:31:15 +0100
> > Richard Sandiford wrote:
> >
> >> Jozef Lawrynowicz writes:
> >> >
> >> > From 82eadcdcbb8914b06818f7c8a10156336518e8d1 Mon Sep 17 00:00:00 2001
> >> > From:
On Fri, 19 Jul 2019 12:24:57 +0200
Jakub Jelinek wrote:
> On Fri, Jul 19, 2019 at 11:17:51AM +0100, Jozef Lawrynowicz wrote:
> > That is something I considered in previous discussion here:
> > https://gcc.gnu.org/ml/gcc-patches/2019-07/msg00372.html
> >
> > But it seemed like this could
On Fri, Jul 19, 2019 at 11:17:51AM +0100, Jozef Lawrynowicz wrote:
> That is something I considered in previous discussion here:
> https://gcc.gnu.org/ml/gcc-patches/2019-07/msg00372.html
>
> But it seemed like this could potentially be a useful feature for other
> targets
> that wish to enable
On Fri, 19 Jul 2019 11:54:43 +0200
Jakub Jelinek wrote:
> On Fri, Jul 19, 2019 at 10:39:52AM +0100, Jozef Lawrynowicz wrote:
> > > > 2019-07-18 Jozef Lawrynowicz
> > > >
> > > > PR target/70320
> > > > * doc/tm.texi.in: Document new macro
> > > >
Installed as obvious.
Andreas.
* config/abi/post/m68k-linux-gnu/baseline_symbols.txt: Update.
diff --git a/libstdc++-v3/config/abi/post/m68k-linux-gnu/baseline_symbols.txt
b/libstdc++-v3/config/abi/post/m68k-linux-gnu/baseline_symbols.txt
index 2af971a5696..1b4fbffa9e4 100644
---
Jozef Lawrynowicz writes:
> On Fri, 19 Jul 2019 09:31:15 +0100
> Richard Sandiford wrote:
>
>> Jozef Lawrynowicz writes:
>> >
>> > From 82eadcdcbb8914b06818f7c8a10156336518e8d1 Mon Sep 17 00:00:00 2001
>> > From: Jozef Lawrynowicz
>> > Date: Wed, 17 Jul 2019 11:48:23 +0100
>> > Subject:
On Fri, Jul 19, 2019 at 10:39:52AM +0100, Jozef Lawrynowicz wrote:
> > > 2019-07-18 Jozef Lawrynowicz
> > >
> > > PR target/70320
> > > * doc/tm.texi.in: Document new macro CASE_INSENSITIVE_REGISTER_NAMES.
> > > * doc/tm.texi: Likewise.
> > > * defaults.h: Define
On Thu, 18 Jul 2019 16:55:59 -0500
Segher Boessenkool wrote:
> Hi!
Hi Segher,
>
> On Thu, Jul 18, 2019 at 08:45:38PM +0100, Jozef Lawrynowicz wrote:
> > PR target/70320
> > * doc/tm.texi.in: Document new macro CASE_INSENSITIVE_REGISTER_NAMES.
> > * doc/tm.texi: Likewise.
>
>
On Fri, 19 Jul 2019 09:31:15 +0100
Richard Sandiford wrote:
> Jozef Lawrynowicz writes:
> >
> > From 82eadcdcbb8914b06818f7c8a10156336518e8d1 Mon Sep 17 00:00:00 2001
> > From: Jozef Lawrynowicz
> > Date: Wed, 17 Jul 2019 11:48:23 +0100
> > Subject: [PATCH] Implement
On 5/15/19 1:39 PM, Christophe Lyon wrote:
The recent stack_protect_combined_set_insn and
stack_protect_combined_test_insn force recomputing of GOT base, but
need to take into account that in FDPIC mode, the PIC register is
fixed by the ABI (r9).
2019-XX-XX Christophe Lyon
*
On 5/15/19 1:39 PM, Christophe Lyon wrote:
Since FDPIC currently supports arm and thumb-2 modes only, these tests
fail because they enforce an architecture version that doesn't match
these restrictions.
This patch introduces new values for the arm_arch effective-target
(v4t_thumb, v5t_thumb,
On 5/15/19 1:39 PM, Christophe Lyon wrote:
uclibc defines bswap_32, so use a different name in this test.
2019-XX-XX Christophe Lyon
gcc/testsuite/
* gcc.target/arm/pr43698.c (bswap_32): Rename as my_bswap_32.
Ok.
This can go in independently of the others.
Thanks,
On 5/15/19 1:39 PM, Christophe Lyon wrote:
Some tests have the "nonpic" guard, but pass on
arm*-*-uclinuxfdpiceabi because it is in PIE mode by default. Rather
than adding this target to all these tests, add the "pie_enabled"
effective target.
2019-XX-XX Christophe Lyon
On 5/15/19 1:39 PM, Christophe Lyon wrote:
Add *-*-uclinux* to tests that work on this target.
2019-XX-XX Christophe Lyon
gcc/testsuite/
* g++.dg/abi/forced.C: Add *-*-uclinux*.
* g++.dg/abi/guard2.C: Likewise.
* g++.dg/ext/cleanup-10.C: Likewise.
*
On 5/15/19 1:39 PM, Christophe Lyon wrote:
Some tests fail on arm*-*-uclinuxfdpiceabi because it generates PIC
code and they don't support it: skip them. They also fail on
arm*-linux* when forcing -fPIC.
2019-XX-XX Christophe Lyon
gcc/testsuite/
*
On 5/15/19 1:39 PM, Christophe Lyon wrote:
In FDPIC mode, r9 is saved in addition to other registers, so update
the expected patterns accordingly.
Ok.
Thanks,
Kyrill
2019-XX-XX Christophe Lyon
Mickaël Guêné
* gcc/testsuite/
* gcc.target/arm/interrupt-1.c:
Hi Christophe,
On 5/15/19 1:39 PM, Christophe Lyon wrote:
Several tests cannot work on ARM-FDPIC for various reasons: skip them,
or skip some directives.
gcc.dg/20020312-2.c: Skip since it forces -fno-pic.
gcc.target/arm/:
* Skip since r9 is clobbered by assembly code:
20051215-1.c
Need to think more about that one. I'm leaving the testcase in,
it compiles somewhat slowly (6s for -O0 optimized cc1 with checking)
but still reasonable due to the other fix for said PR.
Applied.
Richard.
2019-07-19 Richard Biener
PR tree-optimization/91207
Revert
On Fri, 19 Jul 2019, Jakub Jelinek wrote:
> Hi!
>
> As mentioned in the PR, we ICE on the following testcase.
> The problem is that offset_address (in this particular case) does
> update_temp_slot_address (XEXP (memref, 0), new_rtx);
> new_rtx = change_address_1 (memref, VOIDmode, new_rtx,
Jozef Lawrynowicz writes:
> The attached patch adds a new target macro called
> CASE_INSENSITIVE_REGISTER_NAMES, which allows the case of register names
> used in an asm statement clobber list, or given in a command line option, to
> be
> disregarded when comparing with the register names
Hi!
As mentioned in the PR, we ICE on the following testcase.
The problem is that offset_address (in this particular case) does
update_temp_slot_address (XEXP (memref, 0), new_rtx);
new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false);
where the first call inserts the address into
We shouldn't complain that a dependent type is incomplete.
Tested x86_64-pc-linux-gnu, applying to trunk.
* pt.c (invalid_nontype_parm_type_p): Check for dependent class type.
---
gcc/cp/pt.c | 2 ++
gcc/testsuite/g++.dg/cpp2a/nontype-class21.C | 10
A non-type template parameter of class type used in an expression has
const-qualified type; the pt.c hunks deal with this difference from the
unqualified type of the parameter declaration. WAhen we use such a
parameter as an argument to another template, we don't want to confuse
things by copying
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