On Thu, 1 Oct 2020, Jan Hubicka wrote:
> Hi
> > > + if (!fnspec.arg_specified_p (arg))
> > > +;
> > > + else if (!fnspec.arg_used_p (arg))
> > > +flags = EAF_UNUSED;
> > > + else
> > > +{
> > > + if (!fnspec.arg_direct_p (arg))
> >
> > negated test
> >
> > > + flags |= EAF_DI
This is a follow up to PR95586 which fixed only the ICE that occurred
when using derived types in an implicit statement. The ICE occurred
because an attempt was made to determine kind for types that do not have
kinds.
This patch ensures that kind is only determined for types that support kind
On Thu, 1 Oct 2020, Tom de Vries wrote:
> [ was: Re: [committed][testsuite] Re-enable pr94600-{1,3}.c tests for arm ]
>
> On 10/1/20 7:38 AM, Hans-Peter Nilsson wrote:
> > On Wed, 30 Sep 2020, Tom de Vries wrote:
> >> I've analyzed the compilation on strict-alignment target arm-eabi, and
> >
> > A
On 10/1/20 5:26 AM, Richard Biener wrote:
On Wed, 30 Sep 2020, Jason Merrill wrote:
On 9/28/20 3:09 PM, Jason Merrill wrote:
On 9/28/20 3:56 AM, Richard Biener wrote:
On Fri, 25 Sep 2020, Jason Merrill wrote:
On 9/25/20 2:30 AM, Richard Biener wrote:
On Thu, 24 Sep 2020, Jason Merrill wrot
On Tue, Aug 25, 2020 at 12:39 PM Jim Wilson wrote:
> On Wed, Aug 19, 2020 at 1:02 AM Joshua via Gcc-patches
> wrote:
> > * config/riscv/riscv.c (asan_shadow_offset): Implement the offset
> > of asan shadow memory for risc-v.
> > (asan_shadow_offset): new macro definition.
>
> Whe
On Thu, Oct 1, 2020 at 8:02 PM Andrew MacLeod wrote:
>
> On 10/1/20 5:30 PM, David Edelsohn wrote:
> >>> * config/rs6000/rs6000-call.c: Include value-range.h.
> >>> * config/rs6000/rs6000.c: Likewise.
> >> This is okay for trunk, thanks! (It is trivial and obvious as well, so
> >> please just com
On 10/1/20 5:30 PM, David Edelsohn wrote:
* config/rs6000/rs6000-call.c: Include value-range.h.
* config/rs6000/rs6000.c: Likewise.
This is okay for trunk, thanks! (It is trivial and obvious as well, so
please just commit things like this without prior approval.)
This patch is not the correct
From: Thomas Rodgers
Updated patch incorporating latest feedback.
Add support for -
* atomic_flag::wait/notify_one/notify_all
* atomic::wait/notify_one/notify_all
* counting_semaphore
* binary_semaphore
* latch
libstdc++-v3/ChangeLog:
* include/Makefile.am (bits_headers): Add
This Go frontend patch set varargs correctly for the type of method
expression. This fixes https://golang.org/issue/41737. Bootstrapped
and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline
and GCC 10 branch.
Ian
8e23cd3a2d23ad851938bf7015fc97539d65a8c6
diff --git a/gcc/go/gofronte
On Thu, 24 Sep 2020, Michael Meissner via Gcc-patches wrote:
> To map the math functions, typically this patch changes l to f128.
> However there are some exceptions that are handled with this patch.
glibc 2.32 added __*ieee128 names for the *f128 functions, to allow the
long double functions to
On Thu, 24 Sep 2020, Tobias Burnus wrote:
> Hi all,
>
> we got the user comment that it is far from obvious to
> use -foffload=-latomic if the following error shows up:
>
> unresolved symbol __atomic_compare_exchange_16
> collect2: error: ld returned 1 exit status
> mkoffload: fatal error:
Hi!
On Thu, Oct 01, 2020 at 11:03:37PM +0930, Alan Modra wrote:
> during RTL pass: fwprop1
> gcc.dg/pr82596.c: In function 'test_cststring':
> gcc.dg/pr82596.c:27:1: internal compiler error: in decompose, at rtl.h:2282
>
> -m32 gcc/testsuite/gcc.dg/pr82596.c fails along with other tests after
> a
Hi Alan,
On Fri, Oct 02, 2020 at 07:06:46AM +0930, Alan Modra wrote:
> > > I was looking at it again today
> > > with the aim of converting this ugly macro to a function, and spotted
> > > the duplication in freebsd64.h. Which has some bit-rot.
> > >
> > > Do you like the following? rs6000_linu
No one is interested in the mangled name of the C++20 template parameter
object for a class NTTP. So instead of printing
required for the satisfaction of ‘positive’ [with T =
X<::_ZTAXtl5ratioLin1ELi2EEE>]
let's print
required for the satisfaction of ‘positive’ [with T = X<{-1, 2}>]
I don
Hi Segher,
On Thu, Oct 01, 2020 at 01:22:07PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Oct 01, 2020 at 10:57:48PM +0930, Alan Modra wrote:
> > On Wed, Sep 30, 2020 at 03:56:32PM -0500, Segher Boessenkool wrote:
> > > On Wed, Sep 30, 2020 at 05:01:45PM +0930, Alan Modra wrote:
> > > >
> > * config/rs6000/rs6000-call.c: Include value-range.h.
> > * config/rs6000/rs6000.c: Likewise.
>
> This is okay for trunk, thanks! (It is trivial and obvious as well, so
> please just commit things like this without prior approval.)
This patch is not the correct long-term solution, as I explai
On Thu, Oct 01, 2020 at 08:08:01AM +0200, Richard Biener wrote:
> On Wed, 30 Sep 2020, Segher Boessenkool wrote:
>
> > On Wed, Sep 30, 2020 at 09:02:34AM +0200, Richard Biener wrote:
> > > On Tue, 29 Sep 2020, Segher Boessenkool wrote:
> > > > I don't see much about optabs in the docs either. Add
There are only a couple of asserts remaining using this macro, and
nothing using TYPE_HIDDEN_P. Killed thusly.
gcc/cp/
* cp-tree.h (DECL_ANTICIPATED): Adjust comment.
(DECL_HIDDEN_P, TYPE_HIDDEN_P): Delete.
* tree.c (ovl_insert): Delete DECL_HIDDEN_P assert.
Hi,
When running:
...
$ gcc.sh src/gcc/testsuite/gcc.target/nvptx/abi-complex-arg.c -S -dP
...
we have in abi-complex-arg.s:
...
//(insn 3 5 4 2
// (set
//(reg:QI 23)
//(truncate:QI (reg:SI 22))) "abi-complex-arg.c":38:1 29 {truncsiqi2}
// (nil))
cvt.u32.u32 %r23, %r2
On Thu, Oct 01, 2020 at 08:59:12PM +0200, Martin Liška wrote:
> Since a889e06ac68 the following fails.
>
> In file included from ../../gcc/tree-ssa-propagate.h:25:0,
> from ../../gcc/config/rs6000/rs6000.c:78:
> ../../gcc/value-query.h:90:31: error: ‘irange’ has not been declared
I'm going to install the following 3 tested backports.
Martin
>From 0d91a9613ca1c4b8b11d668a1b8e1a6a37c41b7a Mon Sep 17 00:00:00 2001
From: Martin Liska
Date: Fri, 25 Sep 2020 16:21:34 +0200
Subject: [PATCH 3/3] gcov: fix streaming of HIST_TYPE_IOR histogram type.
gcc/ChangeLog:
PR gcov-profi
Since a889e06ac68 the following fails.
In file included from ../../gcc/tree-ssa-propagate.h:25:0,
from ../../gcc/config/rs6000/rs6000.c:78:
../../gcc/value-query.h:90:31: error: ‘irange’ has not been declared
virtual bool range_of_expr (irange &r, tree name, gimple * = NULL) =
Hi!
On Thu, Oct 01, 2020 at 10:57:48PM +0930, Alan Modra wrote:
> On Wed, Sep 30, 2020 at 03:56:32PM -0500, Segher Boessenkool wrote:
> > On Wed, Sep 30, 2020 at 05:01:45PM +0930, Alan Modra wrote:
> > > * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
> > > set -mcmodel=small
Sorry for the slow review.
HAO CHEN GUI via Gcc-patches writes:
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 513fc5fe295..6f5bf8d7d73 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -9315,10 +9315,10 @@ mips_select_rtx_section (machine_mode mode
Hi,
as the FIXME which this patch removes states, the current code does
not work when a call with multiple speculative targets gets resolved
through parameter tracking during inlining - it feeds the inliner an
edge it has already dealt with. The patch makes the code which should
prevent it aware
On 10/1/20 9:34 AM, Aldy Hernandez wrote:
On 10/1/20 3:22 PM, Andrew MacLeod wrote:
> On 10/1/20 5:05 AM, Aldy Hernandez via Gcc-patches wrote:
>>> Thanks for doing all this! There isn't anything I don't understand
>>> in the sprintf changes so no questions from me (well, almost none).
>>>
This PR points out that when we're invoking a non-static member function
on a null instance during constant evaluation, we should reject.
cxx_eval_call_expression calls cxx_bind_parameters_in_call which
evaluates function arguments, but it won't detect problems like these.
Well, ok, so use integer
Christophe Lyon writes:
> On Wed, 30 Sep 2020 at 12:53, Richard Sandiford via Gcc-patches
> wrote:
>>
>> movti lacked an way of zeroing an FPR, meaning that we'd do:
>>
>> mov x0, 0
>> mov x1, 0
>> fmovd0, x0
>> fmovv0.d[1], x1
>>
>> instead of just
Signed-off-by: Alejandro Colomar
---
man7/system_data_types.7 | 40
1 file changed, 40 insertions(+)
diff --git a/man7/system_data_types.7 b/man7/system_data_types.7
index e545aa1a0..5f9aa648f 100644
--- a/man7/system_data_types.7
+++ b/man7/system_data_t
Signed-off-by: Alejandro Colomar
---
man3/__int128.3 | 1 +
1 file changed, 1 insertion(+)
create mode 100644 man3/__int128.3
diff --git a/man3/__int128.3 b/man3/__int128.3
new file mode 100644
index 0..db50c0f09
--- /dev/null
+++ b/man3/__int128.3
@@ -0,0 +1 @@
+.so man7/system_data_ty
Signed-off-by: Alejandro Colomar
---
man7/system_data_types.7 | 35 +++
1 file changed, 35 insertions(+)
diff --git a/man7/system_data_types.7 b/man7/system_data_types.7
index 5f9aa648f..3cf3f0ec9 100644
--- a/man7/system_data_types.7
+++ b/man7/system_data_types.
Hi Michael,
I think this might be ready for a patch.
I'm done for today :-)
Cheers,
Alex
Alejandro Colomar (4):
system_data_types.7: Add '__int128'
__int128.3: New link to system_data_types(7)
system_data_types.7: Add 'unsigned __int128'
unsigned-__int128.3: New link to system_data_ty
Signed-off-by: Alejandro Colomar
---
man3/unsigned-__int128.3 | 1 +
1 file changed, 1 insertion(+)
create mode 100644 man3/unsigned-__int128.3
diff --git a/man3/unsigned-__int128.3 b/man3/unsigned-__int128.3
new file mode 100644
index 0..db50c0f09
--- /dev/null
+++ b/man3/unsigned-__in
Hi all,
I'd like to add a prefer_advsimd_autovec internal tune_flag that makes GCC pick
Advanced SIMD over SVE for autovectorisation.
No CPU tuning uses it yet, but I'd like to add this to the GCC 8 and 9 branches
only as SVE autovectorisation is less mature there and CPUs
may want to prefer Adv
On 01/10/2020 18.04, Olivier Hainque wrote:
> Hello,
>
> This patch is a proposal to add an if-exists-then-else
> builtin spec function, which tests for the existence of
> a file and returns one or the other of the following
> arguments depending on the result of the test.
>
Hello,
could you pleas
Qing Zhao writes:
> Hi, Richard,
>
> To answer the question, which registers should be included in “ALL”.
> I studied X86 hard register set in more details. And also consulted with
> H.J.Lu, And found:
>
> In the current x86 implementation, mask registers, MM0-MM7 registers, and
> ST0-ST7 regis
Alex Coplan writes:
> Hi Christophe,
>
> On 08/09/2020 10:14, Christophe Lyon wrote:
>> On Mon, 17 Aug 2020 at 11:00, Alex Coplan wrote:
>> >
>> > gcc/ChangeLog:
>> >
>> > * config/aarch64/aarch64.md
>> > (*adds__): Ensure extended operand
>> > agrees with width of extensi
Hello,
This patch is a proposal to add an if-exists-then-else
builtin spec function, which tests for the existence of
a file and returns one or the other of the following
arguments depending on the result of the test.
This differs from the existing if-exists or
if-exists-else function which retur
Kyrylo Tkachov writes:
>> -Original Message-
>> From: Andrea Corallo
>> Sent: 01 October 2020 15:36
>> To: gcc-patches@gcc.gnu.org
>> Cc: Richard Earnshaw ; Kyrylo Tkachov
>> ; Christophe Lyon
>> Subject: Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead
>> Loop tests
>>
On 10/1/20 3:22 PM, Andrew MacLeod wrote:
> On 10/1/20 5:05 AM, Aldy Hernandez via Gcc-patches wrote:
>>> Thanks for doing all this! There isn't anything I don't understand
>>> in the sprintf changes so no questions from me (well, almost none).
>>> Just some comments:
>> Thanks for your commen
Hi, Richard,
To answer the question, which registers should be included in “ALL”.
I studied X86 hard register set in more details. And also consulted with
H.J.Lu, And found:
In the current x86 implementation, mask registers, MM0-MM7 registers, and
ST0-ST7 registers are not zeroed.
The reasons
Hi Richard,
> -Original Message-
> From: Richard Sandiford
> Sent: 01 October 2020 15:10
> To: gcc-patches@gcc.gnu.org
> Cc: ni...@redhat.com; Richard Earnshaw ;
> Ramana Radhakrishnan ; Kyrylo
> Tkachov
> Subject: [PATCH] arm: Add missing vec_cmp and vcond patterns
>
> This patch does
> -Original Message-
> From: Andrea Corallo
> Sent: 01 October 2020 15:36
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Kyrylo Tkachov
> ; Christophe Lyon
> Subject: Re: [PATCH PR96375] arm: Fix testcase selection for Low Overhead
> Loop tests
>
> Andrea Corallo writes:
>
>
Andrea Corallo writes:
> Hi all,
>
> I'd like to submit the following patch to fix PR96375 ([11 regression]
> arm/lob[2-5].c fail on some configurations).
>
> It fix the observed regression making sure -mthumb is always used and
> allowing Low Overhead Loop tests to be executed only on cortex-M p
I noticed that the following changes from this paper were not yet
implemented.
OK to commit after testing on x86_64-pc-linux-gnu finishes successfully?
libstdc++-v3/ChangeLog:
* include/bits/stl_iterator.h (reverse_iterator::iter_move):
Define for C++20 as per P0896.
(rev
Hi
> > + if (!fnspec.arg_specified_p (arg))
> > +;
> > + else if (!fnspec.arg_used_p (arg))
> > +flags = EAF_UNUSED;
> > + else
> > +{
> > + if (!fnspec.arg_direct_p (arg))
>
> negated test
>
> > + flags |= EAF_DIRECT;
> > + if (!fnspec.arg_noescape_p (arg))
> > + fla
Hi all,
This patch adds the +rng feature to the Neoverse V1 entry. It exists in the GCC
11 and 10 branches, but was missed out on GCC 9 and 8 as those didn't support
the rng intrinsic then, but they do now.
Bootstrapped and tested on aarch64-none-linux-gnu.
Committing to GCC 8.
Thanks,
Kyrill
Hi all,
This patch adds the +rng feature to the Neoverse V1 entry. It exists in the GCC
11 and 10 branches, but was missed out on GCC 9 and 8 as those didn't support
the rng intrinsic then, but they do now.
Bootstrapped and tested on aarch64-none-linux-gnu.
Committing to GCC 9 and an appropriat
This patch does several things at once:
(1) Add vector compare patterns (vec_cmp and vec_cmpu).
(2) Add vector selects between floating-point modes when the
values being compared are integers (affects vcond and vcondu).
(3) Add vector selects between integer modes when the values being
c
On Thu, 1 Oct 2020, Jan Hubicka wrote:
> Hi,
> this patch adds the simple class for parsing fnspec attribute. I plan
> to add support for generating and modifying it too (it is used by
> fortran and I plan to make modref to detect noclobbers and stuff).
> Verification is disabled until we fix rem
I discovered pushdecl_top_level was not setting the decl's context,
and we ended up with namespace-scope decls with NULL context. That
broke modules. Then I discovered a couple of places where we set the
context to a FUNCTION_DECL, which is also wrong. AFAICT the literals
in question belong in
during RTL pass: fwprop1
gcc.dg/pr82596.c: In function 'test_cststring':
gcc.dg/pr82596.c:27:1: internal compiler error: in decompose, at rtl.h:2282
-m32 gcc/testsuite/gcc.dg/pr82596.c fails along with other tests after
applying rtx_cost patches, which exposed a backend bug.
legitimize_address wh
On Wed, Sep 30, 2020 at 03:56:32PM -0500, Segher Boessenkool wrote:
> On Wed, Sep 30, 2020 at 05:01:45PM +0930, Alan Modra wrote:
> > * config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
> > set -mcmodel=small for -mno-minimal-toc when pcrel.
>
> > - SET_CMODEL (CMODEL_
On 10/1/20 5:05 AM, Aldy Hernandez via Gcc-patches wrote:
Thanks for doing all this! There isn't anything I don't understand
in the sprintf changes so no questions from me (well, almost none).
Just some comments:
Thanks for your comments on the sprintf/strlen API conversion.
The current call
This avoids using VMAT_CONTIGUOUS with single-element interleaving
when using V1mode vectors. Instead keep VMAT_ELEMENTWISE but
continue to avoid load-lanes and gathers.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
2020-10-01 Richard Biener
PR tree-optimiz
Hi
the ICE with -fno-ipa-modref is caused by fact that execute method has
early exit for non-existent summary that forgets to free ipa-prop edge
summaries. I moved the freeing code to free-fnsummary pass that is more
robust way of handling this.
Bootstrapped/regtested x86_64-linux, comitted.
gcc
On 01.10.20 11:13, Jakub Jelinek wrote:
> Hi!
>
> The following patch fixes
> -FAIL: gcc.dg/pr94780.c (internal compiler error)
> -FAIL: gcc.dg/pr94780.c (test for excess errors)
> -FAIL: gcc.dg/pr94842.c (internal compiler error)
> -FAIL: gcc.dg/pr94842.c (test for excess errors)
> on s390x-linux
Hi,
this patch adds the simple class for parsing fnspec attribute. I plan
to add support for generating and modifying it too (it is used by
fortran and I plan to make modref to detect noclobbers and stuff).
Verification is disabled until we fix remaining fortran specifier
(I got a promised help at
This change reworks the condition variables support for VxWorks
to address the very legit points raised by Rasmus in
https://gcc.gnu.org/pipermail/gcc/2020-May/232524.html
While some of the issues were taken care of by the use of semFlush,
a few others were indeed calling for adjustments.
We f
It turns out I'd already found lookup_and_check_tag's control flow
confusing, and had refactored it on the modules branch. For instance,
it continually checks 'if (decl &&$ condition)' before finally getting
to 'else if (!decl)'. why not just check !decl first and be done?
Well, it is done thus
On 01/10/20 08:50 +0100, Jonathan Wakely wrote:
On 01/10/20 09:30 +0200, Christophe Lyon via Libstdc++ wrote:
On Wed, 30 Sep 2020 at 22:44, Jonathan Wakely wrote:
On 30/09/20 16:03 +0100, Jonathan Wakely wrote:
On 29/09/20 13:51 +0200, Christophe Lyon via Libstdc++ wrote:
On Sat, 26 Sep 202
This patch moves the recent entry for Neoverse N2 down and adds a
comment in order to preserve the existing order/structure in
arm-cpus.in.
Bootstrapped and tested on arm-linux-gnueabihf.
Committing as obvious.
Alex
---
gcc/ChangeLog:
* config/arm/arm-cpus.in: Fix ordering, move Neove
[ was: Re: [committed][testsuite] Re-enable pr94600-{1,3}.c tests for arm ]
On 10/1/20 7:38 AM, Hans-Peter Nilsson wrote:
> On Wed, 30 Sep 2020, Tom de Vries wrote:
>
>> [ was: Re: [committed][testsuite] Require non_strict_align in
>> pr94600-{1,3}.c ]
>>
>> On 9/30/20 4:53 AM, Hans-Peter Nilsson
Hello,
This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m,
vaddq_x, vcmpeqq_m,
vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m,
vcmpltq,
vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p,
vmaxnmvq,
vmaxnmvq_p, v
This change reworks CPP_BUILTINS_SPEC for powerpc-vxworks to
prepare for the upcoming addition of 32 and 64 bit ports for
VxWorks 7r2.
This has been used in gcc-9 based production compilers for a
year on both vxworks 7 and 6.9. Also passed a build & test sequence
for powerpc-vxworks 7 and 6.9 with
On Wed, 30 Sep 2020, Jason Merrill wrote:
> On 9/28/20 3:09 PM, Jason Merrill wrote:
> > On 9/28/20 3:56 AM, Richard Biener wrote:
> >> On Fri, 25 Sep 2020, Jason Merrill wrote:
> >>
> >>> On 9/25/20 2:30 AM, Richard Biener wrote:
> On Thu, 24 Sep 2020, Jason Merrill wrote:
>
> > On
Hi!
The following patch fixes
-FAIL: gcc.dg/pr94780.c (internal compiler error)
-FAIL: gcc.dg/pr94780.c (test for excess errors)
-FAIL: gcc.dg/pr94842.c (internal compiler error)
-FAIL: gcc.dg/pr94842.c (test for excess errors)
on s390x-linux. The fix is essentially the same as has been applied t
> Thanks for doing all this! There isn't anything I don't understand
> in the sprintf changes so no questions from me (well, almost none).
> Just some comments:
Thanks for your comments on the sprintf/strlen API conversion.
>
> The current call statement is available in all functions that take
>
> -Original Message-
> From: Alex Coplan
> Sent: 01 October 2020 09:28
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 8] aarch64: Add support for Neoverse N2 CPU
>
> This patch backports the AArch64 support for Arm's N
> -Original Message-
> From: Alex Coplan
> Sent: 01 October 2020 09:25
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Kyrylo Tkachov
> Subject: [PATCH][GCC 9] aarch64: Add support for Neoverse N2 CPU
>
> This patch backports the AArch64 support for Arm's N
This patch backports the AArch64 support for Arm's Neoverse N2 CPU to
GCC 8.
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu.
OK for GCC 8 branch?
Thanks,
Alex
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse N2.
* config/aarch64/aarch64-tun
On Wed, 30 Sep 2020 at 12:53, Richard Sandiford via Gcc-patches
wrote:
>
> movti lacked an way of zeroing an FPR, meaning that we'd do:
>
> mov x0, 0
> mov x1, 0
> fmovd0, x0
> fmovv0.d[1], x1
>
> instead of just:
>
> moviv0.2d, #0
>
> mo
This patch backports the AArch64 support for Arm's Neoverse N2 CPU to
GCC 9.
Testing:
* Bootstrapped and regtested on aarch64-none-linux-gnu.
OK for GCC 9 branch?
Thanks,
Alex
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse N2.
* config/aarch64/aarch64-tun
SRA tends to use VIEW_CONVERT_EXPR when replacing bool fields with
unsigned char fields. Those are not handled in vector bool pattern
detection causing vector true values to leak. The following fixes
this by turning those into b ? 1 : 0 as well.
Bootstrapped and tested on x86_64-unknown-linux-gn
On 01/10/20 09:30 +0200, Christophe Lyon via Libstdc++ wrote:
On Wed, 30 Sep 2020 at 22:44, Jonathan Wakely wrote:
On 30/09/20 16:03 +0100, Jonathan Wakely wrote:
>On 29/09/20 13:51 +0200, Christophe Lyon via Libstdc++ wrote:
>>On Sat, 26 Sep 2020 at 21:42, Jonathan Wakely via Gcc-patches
>> w
On Wed, 30 Sep 2020 at 22:44, Jonathan Wakely wrote:
>
> On 30/09/20 16:03 +0100, Jonathan Wakely wrote:
> >On 29/09/20 13:51 +0200, Christophe Lyon via Libstdc++ wrote:
> >>On Sat, 26 Sep 2020 at 21:42, Jonathan Wakely via Gcc-patches
> >> wrote:
> >>>
> >>>Glibc 2.32 adds a global variable that
On Wed, Sep 30, 2020 at 6:28 PM Jakub Jelinek wrote:
>
> On Wed, Sep 30, 2020 at 06:06:31PM +0200, Florian Weimer wrote:
> > This is what I came up with. It is not valid to set ix86_arch to
> > PROCESSOR_GENERIC, which is why PTA_NO_TUNE is still needed.
>
> Ok, LGTM, but would prefer Uros to hav
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