On Thu, 4 May 2023, Jason Merrill wrote:
> On 5/4/23 09:59, Richard Biener wrote:
> >
> > I've previously sent
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608077.html
> > adding ADDR_EXPR_NONZERO and there were comments from Jason
> > where I just realized I ignored ARRAY_REF for
Hi!
I've noticed 4 typos in comments, fixed thusly.
Tested on x86_64-linux and i686-linux, committed to trunk as obvious.
2023-05-05 Jakub Jelinek
* builtins.cc (do_mpfr_ckconv, do_mpc_ckconv): Fix comment typo,
mpft_t -> mpfr_t.
* fold-const-call.cc (do_mpfr_ckconv,
Hi!
The previous patch just added basic intrinsic ranges for sqrt
([-0.0, +Inf] +-NAN being the general result range of the function
and [-0.0, +Inf] the general operand range if result isn't NAN etc.),
the following patch intersects those ranges with particular range
computed from argument or res
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq.
(MVE_FP_VABDQ_ONLY): New.
(mve_insn): Add vabd.
* config/arm/mve.md (mve_vabdq_f): Move into ...
(@mve_q_f): ... this.
(mve_vabdq_m_f): Remove.
---
gcc
Factorize vqrshlq, vrshlq so that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New.
(mve_insn): Add vqrshl, vrshl.
* config/arm/mve.md (mve_vqrshlq_n_)
(mve_vrshlq_n_): Merge into ...
This patch adds the binary_round_lshift shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_round_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_round_lshift): New.
---
gcc/config/arm/arm-mve-builtins-shapes.
This patch adds the binary_lshift_r shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_lshift_r): New.
* config/arm/arm-mve-builtins-shapes.h (binary_lshift_r): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 41
Factorize vqshlq and vshlq so that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N)
(MVE_SHIFT_N, MVE_SHIFT_R): New.
(mve_insn): Add vqshl, vshl.
* config/arm/mve.md (mve_vqshlq_n_)
Introduce a function that will be used to build vshl intrinsics. They
are special because they have to handle MODE_r.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-functions.h (class
unspec_mve_function_exact_insn_vshl): New.
---
gcc/config/arm/arm-mve-b
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins.cc (has_inactive_argument)
(finish_opt_n_resolution): Handle MODE_r.
* config/arm/arm-mve-builtins.def (r): New mode.
---
gcc/config/arm/arm-mve-builtins.cc | 8 ++--
gcc/config/arm/arm-mve-builti
This patch adds the binary_lshift shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_lshift): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 57 ++
Implement vabdq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N): New.
(vabdq): New.
* config/arm/arm-mve-builtins-base.def (vabdq): New.
* config/arm/arm-mve-builtins-base.h
Implement vqrdmulhq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vqrdmulhq): New.
* config/arm/arm-mve-builtins-base.def (vqrdmulhq): New.
* config/arm/arm-mve-builtins-base.h (vqrdmulhq): New.
This patch adds the binary_rshift shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_rshift): New.
---
gcc/config/arm/arm-mve-builtins-shapes.cc | 36 ++
This patch adds the binary_rshift_narrow_unsigned shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc
(binary_rshift_narrow_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_rshift_narrow_unsigned): New
Factorize vsrhrq vrshrq so that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_VSHRQ_M_N, MVE_VSHRQ_N): New.
(mve_insn): Add vrshr, vshr.
* config/arm/mve.md (mve_vshrq_n_)
(mve_vrshrq_n_): Merge into ...
Implement vrshlq, vqrshlq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vqrshlq, vrshlq): New.
* config/arm/arm-mve-builtins-base.def (vqrshlq, vrshlq): New.
* config/arm/arm-mve-builtins-base.h (vqrs
Factorize vmaxq and vminq so that they use the same pattern.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MAX_MIN_SU): New.
(max_min_su_str): New.
(max_min_supf): New.
* config/arm/mve.md (mve_vmaxq_s, mve_vmaxq_u)
(mve_vminq_s, mve_
Factorize vqrshrunb, vqrshrunt, vqshrunb, vqshrunt so that they use
existing patterns.
2022-09-08 Christophe Lyon
gcc/
* config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ,
VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
(MVE_SHRN_M_N): Likewise.
(mve_insn): Add vqr
Implement vmaxq and vminq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_NO_F): New.
(vmaxq, vminq): New.
* config/arm/arm-mve-builtins-base.def (vmaxq, vminq): New.
* conf
This patch adds the binary_rshift_narrow shape description.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_rshift_narrow):
New.
* config/arm/arm-mve-builtins-shapes.h (binary_rshift_narrow): New.
---
gcc/config/arm/arm-mve-built
Implement vqrshrunbq, vqrshruntq, vqshrunbq, vqshruntq using the new
MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_U_F): New.
(vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New.
* config/arm/ar
Factorize vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq, vshrntq, vshrnbq,
vrshrnbq and vrshrntq so that they use the same pattern.
Introduce iterator for *shrn* so that we can use the same
pattern despite the different "s", "u" and "i" suffixes.
2022-09-08 Christophe Lyon
gcc/
* c
Implement vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq,
vqrshrnbq, vqrshrntq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_F): New.
(vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshr
Implement vqshlq, vshlq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_R): New.
(vqshlq, vshlq): New.
* config/arm/arm-mve-builtins-base.def (vqshlq, vshlq): New.
* config/ar
Implement vshrq and vrshrq using the new MVE builtins framework.
2022-09-08 Christophe Lyon
gcc/
* config/arm/arm-mve-builtins-base.cc (vrshrq, vshrq): New.
* config/arm/arm-mve-builtins-base.def (vrshrq, vshrq): New.
* config/arm/arm-mve-builtins-base.h (vrshrq
Hi!
[Putting Bernhard, Honza, Segher in CC, as they are eager to test this,
based on recent comments on IRC.] ;-P
First, establish the parallel testing infrastructure -- while still
hard-coding the number of parallel slots to one.
On 2015-05-08T10:40:02+0200, I wrote:
> On Thu, 7 May 2015 13:3
Hi!
On 2023-05-05T10:55:41+0200, I wrote:
> [Putting Bernhard, Honza, Segher in CC, as they are eager to test this,
> based on recent comments on IRC.] ;-P
> First, establish the parallel testing infrastructure -- while still
> hard-coding the number of parallel slots to one.
> OK to push the
Hi!
As mentioned in the PR, save_expr seems to be very optimistic when
some expression is invariant, which can result in various wrong-code
issues.
The problem is with the TREE_READONLY (t) && !TREE_SIDE_EFFECTS (t)
case in tree_invariant_p_1. TREE_READONLY (t) in that case says
that the object s
On Wed, 3 May 2023 at 08:44, Richard Biener wrote:
> On Tue, 2 May 2023, Christophe Lyon wrote:
>
> > Hi Richard,
> >
> > On Fri, 28 Apr 2023 at 14:41, Richard Biener via Gcc-patches <
> > gcc-patches@gcc.gnu.org> wrote:
> >
> > > This adds a scatter vectorization capability to the vectorizer
> >
On 5/5/23 10:00, Jakub Jelinek wrote:
Hi!
The previous patch just added basic intrinsic ranges for sqrt
([-0.0, +Inf] +-NAN being the general result range of the function
and [-0.0, +Inf] the general operand range if result isn't NAN etc.),
the following patch intersects those ranges with par
On Fri, May 05, 2023 at 11:06:31AM +0200, Aldy Hernandez wrote:
> > +/* Compute FUNC (ARG) where FUNC is a mpfr function. If RES_LOW is
> > non-NULL,
> > + set it to low bound of possible range if the function is expected to
> > have
> > + ULPS precision and similarly if RES_HIGH is non-NULL
On Fri, May 5, 2023 at 11:14 AM Jakub Jelinek wrote:
>
> On Fri, May 05, 2023 at 11:06:31AM +0200, Aldy Hernandez wrote:
> > > +/* Compute FUNC (ARG) where FUNC is a mpfr function. If RES_LOW is
> > > non-NULL,
> > > + set it to low bound of possible range if the function is expected to
> > >
This patch adds LUI instruction from mips16e2
with corresponding test.
gcc/ChangeLog:
* gcc/config/mips/mips.cc(mips_symbol_insns_1): Generates LUI
instruction.
(mips_const_insns): Same as above.
(mips_output_move): Same as above.
(mips_output_function_prologue):
This patch adds LWL/LWR, SWL/SWR instructions with their
corresponding tests.
gcc/ChangeLog:
* gcc/config/mips/mips.cc(mips_expand_ins_as_unaligned_store):
Add logics for generating instruction.
* gcc/config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for
ISA_HAS_MIPS16E2.
This patch adds MOVx instructions from mips16e2
(movn,movz,movtn,movtz) with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for
ISA_HAS_MIPS16E2.
* config/mips/mips.md(*mov_on_): Add logics for
MOVx insts.
(*mov_on__mips16e2): G
The mips16e2 ASE uses eight general-purpose registers
from mips32, with some special-purpose registers,
these registers are GPRs: s0-1, v0-1, a0-3, and
special registers: t8, gp, sp, ra.
As mentioned above, the special register gp is
used in mips16e2, which is the global pointer register,
it is us
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
This series of patches adds all instructions of MIPS16E2 ASE.
Jie Mei (8):
MIPS: Add basic support for mips16e2
MIPS: Add MOVx instructions support for mips16e2
MIPS: Add ins
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
It defines new special instructions for increasing
code density (e.g. Extend, PC-relative instructions, etc.).
This patch adds basic support for mips16e2 used by the
following series
There are shortened bitwise instructions in the mips16e2 ASE,
for instance, ANDI, ORI/XORI, EXT, INS etc. .
This patch adds these instrutions with corresponding tests.
gcc/ChangeLog:
* gcc/config/mips/constraints.md(Yz): New constraints for mips16e2.
* gcc/config/mips/mips-protos
The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.
gcc/ChangeLog:
* gcc/config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
for ISA_HAS_MIPS16E2.
(ISA_HAS_SYNC): Same as above.
This patch adds CACHE instruction from mips16e2
with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.c(mips_9bit_offset_address_p): Restrict the
address register to M16_REGS for MIPS16.
(BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
(AVAIL_MIPS16E2_OR_NON_MI
* Jonathan Wakely via Libstdc:
> We could use strtod for a single-threaded target (i.e.
> !defined(_GLIBCXX_HAS_GTHREADS) by changing the global locale using
> setlocale, instead of changing the per-thread locale using uselocale.
This is not generally safe because the call to setlocale is still
o
On Fri, 5 May 2023 at 10:43, Florian Weimer wrote:
> * Jonathan Wakely via Libstdc:
>
> > We could use strtod for a single-threaded target (i.e.
> > !defined(_GLIBCXX_HAS_GTHREADS) by changing the global locale using
> > setlocale, instead of changing the per-thread locale using uselocale.
>
> Thi
On Fri, May 05, 2023 at 11:04:09AM +0200, Jakub Jelinek via Gcc-patches wrote:
> As mentioned in the PR, save_expr seems to be very optimistic when
> some expression is invariant, which can result in various wrong-code
> issues.
> The problem is with the TREE_READONLY (t) && !TREE_SIDE_EFFECTS (t)
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 01/23] arm: [MVE intrinsics] add binary_round_lshift shape
>
> This patch
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 02/23] arm: [MVE intrinsics] factorize vqrshlq vrshlq
>
> Factorize vqrshl
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 03/23] arm: [MVE intrinsics] rework vrshlq vqrshlq
>
> Implement vrshlq, v
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 04/23] arm: [MVE intrinsics] factorize vqshlq vshlq
>
> Factorize vqshlq a
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 05/23] arm: [MVE intrinsics] rework vqrdmulhq
>
> Implement vqrdmulhq usin
Updated the PATCH v2 with x86 bootstrap and regression test passed.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617449.html
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Li, Pan2 via Gcc-patches
Sent: Thursday, May 4, 2023 4:44 PM
To: juzhe.zh...@rivai.ai; gcc-patches
C
Here's a patch to skip/xfail the bits that are expected to fail on
aarch64-vxworks.
[libstdc++] [testsuite] xfail double-prec from_chars for ldbl
When long double is wider than double, but from_chars is implemented
in terms of double, tests that involve the full precision of long
double are expe
On Fri, May 05, 2023 at 11:55:41AM +0200, Jakub Jelinek via Gcc-patches wrote:
> Looking at the Ada cases (I admit I don't really understand why it isn't
> vectorized, the IL is so different from the start because of the extra
> SAVE_EXPRs that it is very hard to diff stuff), the case where save_ex
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 06/23] arm: [MVE intrinsics] factorize vabdq
>
> 2022-09-08 Christophe Ly
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 07/23] arm: [MVE intrinsics] rework vabdq
>
> Implement vabdq using the ne
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 08/23] arm: [MVE intrinsics] add binary_lshift shape
>
> This patch adds t
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 09/23] arm: [MVE intrinsics] add support for MODE_r
>
This is missing a d
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 10/23] arm: [MVE intrinsics] add binary_lshift_r shape
>
> This patch adds
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 11/23] arm: [MVE intrinsics] add
> unspec_mve_function_exact_insn_vshl
>
>
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 12/23] arm: [MVE intrinsics] rework vqshlq vshlq
>
> Implement vqshlq, vsh
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 13/23] arm: [MVE intrinsics] factorize vmaxq vminq
>
> Factorize vmaxq and
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 14/23] arm: [MVE intrinsics] rework vmaxq vminq
>
> Implement vmaxq and vm
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 15/23] arm: [MVE intrinsics] add binary_rshift_narrow shape
>
> This patch
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 16/23] arm: [MVE intrinsics] factorize vshrntq vshrnbq
> vrshrnbq vrshrntq
On Fri, 5 May 2023 at 11:39, Alexandre Oliva wrote:
> Here's a patch to skip/xfail the bits that are expected to fail on
> aarch64-vxworks.
>
OK for trunk and gcc-13, thanks.
>
>
> [libstdc++] [testsuite] xfail double-prec from_chars for ldbl
>
> When long double is wider than double, but from
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 17/23] arm: [MVE intrinsics] rework vshrnbq vshrntq
> vrshrnbq vrshrntq vqs
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 18/23] arm: [MVE intrinsics] add
> binary_rshift_narrow_unsigned shape
>
>
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 19/23] arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt
> vqshrunb vqshr
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq
> vqshrunbq vqshr
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 21/23] arm: [MVE intrinsics] add binary_rshift shape
>
> This patch adds t
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 22/23] arm: [MVE intrinsics] factorize vsrhrq vrshrq
>
> Factorize vsrhrq
> -Original Message-
> From: Christophe Lyon
> Sent: Friday, May 5, 2023 9:40 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ;
> Richard Earnshaw ; Richard Sandiford
>
> Cc: Christophe Lyon
> Subject: [PATCH 23/23] arm: [MVE intrinsics] rework vshrq vrshrq
>
> Implement vshrq and v
Probably added for symmetry with out_mode/out_n but at the end not used.
That function was added in commit
r13-6423-gce9cd7258d0 amdgcn: Enable SIMD vectorization of math functions
Tested the removal by building with that patch applied.
OK for mainline?
Tobias
-
Siemens Electro
On 05/05/2023 12:10, Tobias Burnus wrote:
Probably added for symmetry with out_mode/out_n but at the end not used.
That function was added in commit
r13-6423-gce9cd7258d0 amdgcn: Enable SIMD vectorization of math
functions
Tested the removal by building with that patch applied.
OK for mainl
On 5/5/23 06:45, Jakub Jelinek wrote:
On Fri, May 05, 2023 at 11:55:41AM +0200, Jakub Jelinek via Gcc-patches wrote:
Looking at the Ada cases (I admit I don't really understand why it isn't
vectorized, the IL is so different from the start because of the extra
SAVE_EXPRs that it is very hard to
Hello,
Le 05/05/2023 à 10:00, Jakub Jelinek via Gcc-patches a écrit :
Hi!
The previous patch just added basic intrinsic ranges for sqrt
([-0.0, +Inf] +-NAN being the general result range of the function
and [-0.0, +Inf] the general operand range if result isn't NAN etc.),
the following patch in
Hello,
Le 01/05/2023 à 18:29, Harald Anlauf via Fortran a écrit :
Dear all,
the attached patch is mostly self-explaining: we mishandled the
overloading of intrinsic binary operators in the case the actual
operands were of intrinsic numeric type and the ranks of the
operands were not conformable
On Fri, May 05, 2023 at 01:38:48PM +0200, Mikael Morin wrote:
> I think there is something wrong with the handling of NAN and lower bounds
> in op1_range. If the lhs has positive lower bound and can be nan, op1
> should have -inf lower bound regardless of lhs's lower bound value.
Oops, you're rig
For SSE2 targets the expander unpacks input elements into the correct
position in the V4SI vector and emits PMULUDQ instruction. The output
elements are then shuffled back to their positions in the V2SI vector.
For SSE4 targets PMULLD instruction is emitted directly.
gcc/ChangeLog:
* config
There's handling in vectorizable_operation for POINTER_DIFF_EXPR
requiring conversion of the result of the unsigned operation to
a signed type. But that's conditional on the "default" kind of
vectorization. In this PR it's shown the emulated vector path
needs it and I think the masked operation c
Hi kito,
Could you please help to share any suggestion about the PATCH? Comparing the V1
and V2.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, May 3, 2023 7:18 PM
To: Jeff Law ; Kito Cheng
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; Andrew Waterman
I will take V1 and commit to trunk after my local test is done :)
On Fri, May 5, 2023 at 8:30 PM Li, Pan2 wrote:
>
> Hi kito,
>
> Could you please help to share any suggestion about the PATCH? Comparing the
> V1 and V2.
>
> Pan
>
>
> -Original Message-
> From: Li, Pan2
> Sent: Wednesday,
Ok, sounds good. Thank you!
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, May 5, 2023 8:37 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET
I will take V1 and commi
> This looks pretty reasonable to me. Are there any patches left in
> this series that need review? I'm very much looking forward to
> build time provements related to this patch, particularly for
> targets that I bootstrap with qemu emulation -- we take multiple
> hours
Rename index_register_operand predicate to what it really does.
No functional change.
gcc/ChangeLog:
* config/i386/predicates.md (register_no_SP_operand):
Rename from index_register_operand.
(call_register_operand): Update for rename.
* config/i386/i386.md (*lea_general_[1234]):
LGTM, committed to trunk with few changelog adjustments and few extra comments.
On Fri, May 5, 2023 at 2:33 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is to fix following case:
> void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond)
> {
> size_t vl = 101;
> if (co
Just one minor comment otherwise LGTM.
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 45a63cab9c9..1a35e02796d 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3793,6 +3793,14 @@ riscv_get_arg_info (struct riscv_arg_info *info, const
>
On Fri, May 05, 2023 at 07:38:45AM -0400, Jason Merrill wrote:
> On 5/5/23 06:45, Jakub Jelinek wrote:
> > + if (TREE_READONLY (t) && !TREE_SIDE_EFFECTS (t))
> > +{
> > + /* Return true for const qualified vars, but for members or array
> > +elements without side-effects return true o
From: Juzhe-Zhong
This patch is fixing my recent optimization patch:
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:
vsetvli a5,a4, e8,m1
..
vsetvli zero,a5,
Plz re-titile with some description rather than `Fix PR` :)
On Fri, May 5, 2023 at 9:52 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is fixing my recent optimization patch:
> https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
>
> In that patch, the new_info = par
From: Juzhe-Zhong
This patch is depending on
https://patchwork.sourceware.org/project/gcc/patch/20230504054544.203366-1-juzhe.zh...@rivai.ai/
Fix codes according to comments of Kito.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_get_arg_info): Move RVV type argument
handling outside.
From: Juzhe-Zhong
This patch is fixing my recent optimization patch:
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf
In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:
vsetvli a5,a4, e8,m1
..
vsetvli zero,a5,
Hi Juzhe,
I wasn't yet able to check this locally so just some minor comment nits:
> +/* Return the vectorization machine mode for RVV according to LMUL. */
> +machine_mode
> +preferred_simd_mode (scalar_mode mode)
> +{
> + /* We only enable auto-vectorization when TARGET_MIN_VLEN < 128 &&
> +
pushed to trunk, thanks :)
On Thu, May 4, 2023 at 5:12 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> This patch try to legitimise the const0_rtx (aka zero register)
> as the base register for the RVV indexed load/store instructions
> by allowing the const as the operand of the indexed RT
pushed v1 to trunk
On Fri, May 5, 2023 at 8:46 PM Li, Pan2 via Gcc-patches
wrote:
>
> Ok, sounds good. Thank you!
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Friday, May 5, 2023 8:37 PM
> To: Li, Pan2
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
>
Thank you!
-Original Message-
From: Kito Cheng
Sent: Friday, May 5, 2023 10:52 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH v2] RISC-V: Legitimise the const0_rtx for RVV indexed
load/store
pushed to trun
From: Juzhe-Zhong
Address comments from Robin.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (preferred_simd_mode): Fix comments.
* config/riscv/riscv.cc (riscv_get_arg_info): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix function name.
This patch has broken GCC bootstrap on AIX. It appears to rely upon, or
complain about, the command "seq":
/nasfarm/edelsohn/install/GCC12/bin/g++ -std=c++11 -g -DIN_GCC
-fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
-Wno-narrowing -Wwrite-strings -Wcast-qual -Wno-format
-Wmiss
On Wed, Apr 19, 2023 at 11:58 AM Jin Ma wrote:
>
> This patch adds the 'Zfa' extension for riscv, which is based on:
> https://github.com/riscv/riscv-isa-manual/commits/zfb
>
> https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da
>
> The binutils-gdb for '
On 5/5/23 08:59, David Edelsohn via Gcc-patches wrote:
This patch has broken GCC bootstrap on AIX. It appears to rely upon, or
complain about, the command "seq":
/nasfarm/edelsohn/install/GCC12/bin/g++ -std=c++11 -g -DIN_GCC
-fno-exceptions -fno-rtti -fasynchronous-unwind-tables -W -Wall
-
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