gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
Remove the sym+addend form from the SYMBOL_PCREL64 type symbol.
(loongarch_output_mi_thunk): Add code model extreme support.
(loongarch_option_override_internal): Supports option combina
When cmodel=extreme, since the symbol address is obtained through four
instructions,
errors may occur in some cases during linking. Therefore, in order to ensure
that
the instructions for obtaining the symbol address are together, macro
instructions
are used to obtain the symbol address when cmo
Instructions pcalau12i, addi.d, lu32i.d and lu52i.d must be adjancent so that
the
linker can infer the PC of pcalau12i to apply relocations to lu32i.d and
lu52i.d.
Otherwise, the results would be incorrect if these four instructions are not in
the same 4KiB page.
See the link for details:
https:
Ccmp is not used if the result of the and/ior is used by both
a GIMPLE_COND and a GIMPLE_ASSIGN. This improves the code generation
here by using ccmp in this case.
Two changes is required, first we need to allow the outer statement's
result be used more than once.
The second change is that during t
This patch implenments more vec_init optabs that can handle two LSX vectors
producing a LASX
vector by concatenating them. When an lsx vector is concatenated with an LSX
const_vector of
zeroes, the vec_concatz pattern can be used effectively. For example as below
typedef short v8hi __attribute__
For zero_extendqisi2 and zero_extendqidi2, use andi instead of bstrpick.w,
because andi is 6 times faster than bstrpick.w.
gcc/ChangeLog:
* config/loongarch/loongarch.md:
(zero_extend2): Rename to ..
(zero_extendhi2): .. this, use hi.
(zero_extendqihi2): Rename to
For instruction xvpermi.q, unused bits in operands[3] need be set to 0 to avoid
causing undefined behavior on LA464.
gcc/ChangeLog:
* config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-xvpremi.c: Rem
LEON now uses the standard V8 membar patterns that contains an ldstub
instruction. This instruction needs to be aligned properly when the
GR712RC errata workaround is enabled.
gcc/ChangeLog:
* config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat
membar_storeload as atomic
* con
This is to handle the membar_empty instruction that can be generated
when compiling for UT699.
gcc/ChangeLog:
* config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated
as empty
---
gcc/config/sparc/sparc.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/spar
From: Andreas Larsson
LEON5 has a deeper write-buffer and hence stb is not enough to flush a
write out. For compatibility, use the default V8 approach for both
LEON3 and LEON5.
This reverts commit 49cc765db35a5a21cab2aece27a44983fa70b94b,
"sync.md (*membar_storeload_leon3): New insn."
gcc/Chang
pr88077 fails on SPARC since char HeaderStr[1] in pr88077_1.c and
long HeaderStr in pr88077_0.c differs in alignment.
warning: alignment 4 of normal symbol `HeaderStr' in c_lto_pr88077_0.o is
smaller than 8 used by the common definition in c_lto_pr88077_1.o
gcc/testsuite/ChangeLog:
* gcc
Target features constants from loongarch-def.h are currently defined as macros.
Switch to enums for better look in the debugger.
gcc/ChangeLog:
* config/loongarch/loongarch-def.h: Define constants with
enums instead of Macros.
---
gcc/config/loongarch/loongarch-def.h | 115 ++
This patchset performs some code cleanup, and is bootstrapped and regtested
on loongarch64-linux-gnu.
Yang Yujie (4):
LoongArch: Handle ISA evolution switches along with other options
LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
LoongArch: Use enums for constants
LoongArch: Simplif
Since we do not need printing or manual parsing of this option,
(whether in the driver or for target attributes to be supported later)
it can be handled in the .opt file framework.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
argument string d
LoongArch ISA manual v1.10 suggests that software should not depend on
the ISA version number for marking processor features. The ISA version
number is now defined as a collective name of individual ISA evolutions.
Since there is a independent ISA evolution mask now, we can drop the
version inform
gcc/ChangeLog:
* config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
variable with the common la_ prefix.
* config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
flags as saved using TargetVariable.
* config/loongarch/loongarch.opt: Same.
Yes, as Juzhe said I had run all the riscv regression, but without RTL check.
I will fix it.
Sorry for forgetting to enable RTL checking for testing.
Thanks Juzhe for helping me reverse this commit.
From: juzhe.zh...@rivai.ai
Date: 2024-01-05 11:28
To: palmer
CC: gcc-patches; kito.cheng; Kito.c
- Change the default vectorization "-mlasx" option to "-mlsx" because there
are many non-aligned memory accesses when using 256-bit vectorization.
- The following detection procedure is added to the target-supports.exp file:
1.check_effective_target_scalar_all_fma
2.check_effective_target_vect_in
From: Liwei Xu
This patch optimize byte swaps in vectors using SSE2 instructions.
It targets 8-byte and 16-byte vectors, efficiently handling patterns like
__builtin_shufflevector(v, v, 1, 0, 3, 2, ...).
PR target/107563
gcc/ChangeLog:
* config/i386/i386-expand.cc (expand_vec
While working on fixing a bug, I notice this following code has redundant move:
#include "riscv_vector.h"
void
f (float x, float y, void *out)
{
float f[4] = { x, x, x, y };
vfloat32m1_t v = __riscv_vle32_v_f32m1 (f, 4);
__riscv_vse32_v_f32m1 (out, v, 4);
}
Before this patch:
f:
vs
In the LoongArch architecture, the reason for not adding the 128-bit
vector-width-*hi* instruction template in the GCC back end is that it causes
program performance loss, so we can only add the "-mlasx" compilation option
to use 256-bit vectorization functions in test files.
gcc/testsuite/ChangeL
When binutils does not support vector instruction sets, the test program fails
because it does not recognize vectorization at the assembly stage. Therefore,
the default run behavior of the program is deleted, so that the behavior of
the program depends on whether the software supports vectorization
On the LoongArch architecture, an error was found in the
bind_c_array_params_2.f90 file because there was no proper assembly code
for the regular expression detection function call, such as bl %plt(myBindC).
gcc/testsuite/ChangeLog:
* gfortran.dg/bind_c_array_params_2.f90: Add code test r
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-82.c: Add the LoongArch architecture to the
object detection framework.
* gcc.dg/vect/vect-83.c: Dito.
---
gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +-
gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +-
2 files changed, 2 insertions(+),
In the GCC of LoongArch architecture, the detection function of common
vectorization test cases is enabled. The following detection procedure
is added to the target-supports.exp file:
1.check_effective_target_scalar_all_fma
2.check_effective_target_vect_int
3.check_effective_target_vect_intfloat_c
On the LoongArch architecture, the above four test cases need to be waived
during testing. There are two situations:
1. The function of fma-{3,6}.c test is to find the value of c-a*b, but on
the LoongArch architecture, the function of the existing fnmsub instruction
is to find the value of -(a*b -
Before modifying the test behavior of the program, dg-do is set to assemble in
vect-bic-bitmask-{12,23}.c. However, when the binutils library does not support
the vector instruction set, it will FAIL to recognize the vector instruction
and fail item will appear in the assembly stage. So set the pro
v1->v2:
On the basis of v1, the reason of the analysis problem is described in detail.
When using binutils, which does not support vectorization, and the gcc compiler
toolchain, which does support vectorization, the following two types of error
problems occur in gcc regression testing.
1.Failur
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
Remove the sym+addend form from the SYMBOL_PCREL64 type symbol.
(loongarch_output_mi_thunk): Add code model extreme support.
(loongarch_option_override_internal): Supports option combina
Instructions pcalau12i, addi.d, lu32i.d and lu52i.d must be adjancent so that
the
linker can infer the PC of pcalau12i to apply relocations to lu32i.d and
lu52i.d.
Otherwise, the results would be incorrect if these four instructions are not in
the same 4KiB page.
See the link for details:
https:
When cmodel=extreme, since the symbol address is obtained through four
instructions,
errors may occur in some cases during linking. Therefore, in order to ensure
that
the instructions for obtaining the symbol address are together, macro
instructions
are used to obtain the symbol address when cmo
I have reverted those 2 commits:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=960c2620db254a1edc2cd61e608df73073b3de0d
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b3ec98d458f2b285bb7b3fa4fcd93fd830fee069
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2024-01-05 11:24
To: juzhe.zhong
We (me and kito) has reviewed vector-crypto.
I believe Wang Feng has done && passed the regression (with no RTL check), but
he just didn't enable RTL check I guessed.
(By default, RTL check is disabled in riscv-gnu-toolchain, developers need to
enable it manually).
It's ok to revert the patch,
On Thu, 04 Jan 2024 19:17:21 PST (-0800), juzhe.zh...@rivai.ai wrote:
Hi, Wang Feng.
Your patch has some ICEs:
FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler error: RTL
check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, at
config/riscv/riscv-v.cc:4930)
FAIL:
Hi, Wang Feng.
Your patch has some ICEs:
FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler error: RTL
check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, at
config/riscv/riscv-v.cc:4930)
FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (test for excess errors)
FAI
Hans-Peter Nilsson wrote:
On Wed, 3 Jan 2024, Jacob Bachmeyer wrote:
Comments before I start on an implementation?
I'd suggest to await the conclusion of the debate: I *think*
I've proved that dg-timeout-factor is already active as intended
(all parts of a test), specifically when th
On 1/4/24 18:02, Nathaniel Shead wrote:
On Thu, Jan 04, 2024 at 05:42:34PM -0500, Jason Merrill wrote:
On 1/4/24 17:24, Nathaniel Shead wrote:
On Thu, Jan 04, 2024 at 03:31:50PM -0500, Jason Merrill wrote:
On 1/2/24 17:40, Nathaniel Shead wrote:
Static data members marked 'inline' should be e
1). We not only have vashl_optab,vashr_optab,vlshr_optab which vectorize shift
with vector shift amount,
that is, vectorization of 'a[i] >> x[i]', the shift amount is loop variant.
2). But also, we have ashl_optab, ashr_optab, lshr_optab which can vectorize
shift with scalar shift amount,
that is
This patch try to fix the bug when HAVE_ATOMIC_FETCH_ADD is
not defined in dec_waiting_unlocked function. As io.h does
not include async.h, the WRLOCK and RWUNLOCK macros are
undefined.
libgfortran/ChangeLog:
* io/io.h (dec_waiting_unlocked): Use
__gthread_rwlock_wrlock/__gthread_
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/ri
On Thu, Jan 4, 2024 at 2:11 PM Jonathan Wakely wrote:
>
> On Sat, 23 Dec 2023 at 23:06, Ken Matsui wrote:
> >
> > This patch uses _GLIBCXX_USE_BUILTIN_TRAIT macro instead of __has_builtin
> > in the type_traits header for traits that have a corresponding fallback
> > non-built-in implementation.
On 1/4/24 02:11, Jakub Jelinek wrote:
Hi!
We expand __builtin_popcount* (x) == 1 as
x ^ (x - 1) > x - 1, either unconditionally in tree-ssa-math-opts.cc
if we don't have a direct optab support for popcount, or during
expansion where we compare the costs of comparison of the popcount
against o
On Thu, Jan 04, 2024 at 05:42:34PM -0500, Jason Merrill wrote:
> On 1/4/24 17:24, Nathaniel Shead wrote:
> > On Thu, Jan 04, 2024 at 03:31:50PM -0500, Jason Merrill wrote:
> > > On 1/2/24 17:40, Nathaniel Shead wrote:
> > > > Static data members marked 'inline' should be emitted in TUs where they
>
On 1/4/24 17:24, Nathaniel Shead wrote:
On Thu, Jan 04, 2024 at 03:31:50PM -0500, Jason Merrill wrote:
On 1/2/24 17:40, Nathaniel Shead wrote:
Static data members marked 'inline' should be emitted in TUs where they
are ODR-used. We need to make sure that statics imported from modules
are corre
On Thu, 2024-01-04 at 14:32 -0800, Palmer Dabbelt wrote:
> > +proc check_effective_target_ifn_copysign { } {
> > + return [check_cached_effective_target_indexed ifn_copysign {
> > + expr {
> > +(([istarget i?86-*-*] || [istarget x86_64-*-*])
> > + && [is-effective-target sse])
> >
Am 03.01.2024 um 00:12 schrieb Björn Schäpers:
Am 30.11.2023 um 20:53 schrieb Ian Lance Taylor:
On Fri, Jan 20, 2023 at 2:55 AM Björn Schäpers wrote:
From: Björn Schäpers
Fixes https://github.com/ianlancetaylor/libbacktrace/issues/53, except
that libraries loaded after the backtrace_initial
On Thu, 04 Jan 2024 10:20:25 PST (-0800), tamar.christ...@arm.com wrote:
> Hi All,
>
> currently GCC does not treat IFN_COPYSIGN the same as the copysign tree expr.
> The latter has a libcall fallback and the IFN can only do optabs.
>
> Because of this the change I made to optimize copysign only wo
On Thu, Jan 04, 2024 at 03:31:50PM -0500, Jason Merrill wrote:
> On 1/2/24 17:40, Nathaniel Shead wrote:
> > Static data members marked 'inline' should be emitted in TUs where they
> > are ODR-used. We need to make sure that statics imported from modules
> > are correctly added to the 'pending_sta
On Thu, 4 Jan 2024, Patrick Palka wrote:
> On Sat, 23 Dec 2023, Ken Matsui wrote:
>
> > This patch optimizes the compilation performance of std::is_pointer
> > by dispatching to the new __is_pointer built-in trait.
> >
> > libstdc++-v3/ChangeLog:
> >
> > * include/bits/cpp_type_traits.h (__
On Sat, 23 Dec 2023 at 22:07, Ken Matsui wrote:
>
> This patch optimizes the compilation performance of std::is_pointer
> by dispatching to the new __is_pointer built-in trait.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/cpp_type_traits.h (__is_pointer): Use
> __is_pointer built
On Sat, 23 Dec 2023 at 23:06, Ken Matsui wrote:
>
> This patch uses _GLIBCXX_USE_BUILTIN_TRAIT macro instead of __has_builtin
> in the type_traits header for traits that have a corresponding fallback
> non-built-in implementation. This macro supports to toggle the use of
> built-in traits in the
On Sat, 23 Dec 2023, Ken Matsui wrote:
> This patch optimizes the compilation performance of std::is_pointer
> by dispatching to the new __is_pointer built-in trait.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/cpp_type_traits.h (__is_pointer): Use
> __is_pointer built-in trait. O
On Sat, 23 Dec 2023, Ken Matsui wrote:
> This patch uses _GLIBCXX_USE_BUILTIN_TRAIT macro instead of __has_builtin
> in the type_traits header for traits that have a corresponding fallback
> non-built-in implementation. This macro supports to toggle the use of
> built-in traits in the type_traits
On 1/4/24 02:34, Jakub Jelinek wrote:
Hi!
The following testcase ICEs when rslt is SSA_NAME_OCCURS_IN_ABNORMAL_PHI
and we call replace_uses_by with a INTEGER_CST def, where it ICEs on:
if (e->flags & EDGE_ABNORMAL
&& !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (val))
be
On 1/4/24 02:23, Mikael Pettersson wrote:
emit_library_call_value_1 calls emit_push_insn with NULL_TREE
for TYPE. Sometimes emit_push_insn needs to assign a temp with
that TYPE, which causes a segfault.
Fixed by computing the TYPE from MODE when needed.
Original patch by Thorsten Otto.
gcc
I have successfully bootstrapped and regtested the patch on loongarch64-
linux-gnu. The test cases in the patch (intended for RISC-V) also works
on LoongArch per my manual testing.
On Mon, 2024-01-01 at 14:04 -0700, Jeff Law wrote:
> I know we're deep into stage3 and about to transition to stage4
On Sun, 3 Dec 2023, Nathaniel Shead wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
>
> -- >8 --
>
> The TYPE_DECL_SUPPRESS_DEBUG and DECL_EXTERNAL flags use the same
> underlying bit. This is causing confusion when attempting to determine
> the interface for a streamed
On 1/2/24 17:40, Nathaniel Shead wrote:
Static data members marked 'inline' should be emitted in TUs where they
are ODR-used. We need to make sure that statics imported from modules
are correctly added to the 'pending_statics' map so that they get
emitted if needed, otherwise the attached testca
On 1/4/24 06:36, Stefan Schulze Frielinghaus wrote:
I have successfully bootstrapped and regtested the patch on s390. Out
of curiosity I also ran some benchmarks which didn't show much changes
except in one case which I will have to analyze further. If there is
anything interesting I will re
On 12/31/23 21:03, Andrew Pinski wrote:
For boolean types, `a ^ b` is a valid form for `a != b`. This means for
gimple_bitwise_inverted_equal_p, we catch some inverted value forms. This
patch extends inverted_equal_p to allow matching of `^` with the
corresponding `==`. Note in the testcase pr
On 1/2/24 12:41, Ilya Leoshkevich wrote:
gccint recommends using ASM_OUTPUT_FUNCTION_LABEL in
ASM_DECLARE_FUNCTION_NAME, but many implementations use
ASM_OUTPUT_LABEL instead. It's inconsistent and prevents changes to
ASM_OUTPUT_FUNCTION_LABEL from affecting the respective targets.
---
gcc/
On Wed, 3 Jan 2024, Nathaniel Shead wrote:
> Linaro CI tells me that this patch caused regressions on ARM. I don't
> have an ARM machine available to test on, but it appears to have been
> caused by attempting to stream vtables as static data members, and ARM
> having different behaviour with rega
On Thu, Jan 4, 2024 at 5:51 AM Radek Barton wrote:
>
> Hello, everyone.
>
>
> Our "Arm64 on Windows Ecosystem" team is currently working on adding
> aarch64-w64-mingw32 target and we've noticed that recent commit adding SME
> support (https://gcc.gnu.org/pipermail/gcc-cvs/2023-December/394915.ht
libstdc++-v3/ChangeLog:
* include/std/generator (_Stateless_alloc): Rename typename _A
to _All.
---
Pushed as obvious.
Happy new year, have a lovely day!
libstdc++-v3/include/std/generator | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/libstdc++-v3/inc
libstdc++-v3/ChangeLog:
* include/std/generator (_Subyield_state::_M_jump_in): Fix typo
reported by Will Hawkins .
---
libstdc++-v3/include/std/generator | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/include/std/generator
b/libstdc++-v3/include/
Hi All,
currently GCC does not treat IFN_COPYSIGN the same as the copysign tree expr.
The latter has a libcall fallback and the IFN can only do optabs.
Because of this the change I made to optimize copysign only works if the
target has impemented the optab, but it should work for those that have
On Wed, 3 Jan 2024, Nathaniel Shead wrote:
> Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
>
> -- >8 --
>
> The attached testcase Patrick found in PR c++/112899 ICEs because it is
> attempting to write a variable initializer that is no longer in the
> static_aggregates map.
>
This fixes the avr-specific attributes io, io_low and address,
that are all basically the same except that io and io_low imply
assertions on allowed addressing modes.
It also improves some diagnostics.
Johann
--
gcc/
PR target/112952
* config/avr/avr.cc (avr_handle_addr_attribu
Thanks! I am trying to re-write by calling __builtin_clear_padding. But I
found gimple_fold_builtin_clear_padding seems only work before SSA pass.
Should I remove the assertion?
On the other hand, since ATOMIC_COMPARE_EXCHANGE will only work for simple
reg type. excluding vector or complex types,
Hello Thomas,
On 12/18/23 17:58, Thomas Schwinge wrote:
--- a/libgrust/configure.ac
+++ b/libgrust/configure.ac
-# AM_ENABLE_MULTILIB(, ..)
+AM_ENABLE_MULTILIB(, ..)
Such a change was applied eventually, and is necessary for target builds
-- but potentially harmful for host builds. OK to
From: Raiki Tamura
This commit adds a new function intended for checking the XID properties
of a possibly unicode character, as well as the accompanying enum
describing the possible properties.
libcpp/ChangeLog:
* charset.cc (cpp_check_xid_property): New.
* include/cpplib.h
Hi Joseph,
Thanks for the review!
On 12/18/23 20:00, Joseph Myers wrote:
On Fri, 8 Sep 2023, Arthur Cohen wrote:
+ if (c < 0x80)
+ {
+if (('A' <= c && c <= 'Z') || ('a' <= c && c <= 'z'))
+ return CPP_XID_START | CPP_XID_CONTINUE;
+if (('0' <= c && c <= '9') || c == '_')
+ return
I plan to push this as obvious.
There are also 32 other files that match "^# .*licenses/>\. *\*/$" in
the repo, mostly .exp files in the testsuite. I'm not changing them,
only the Python files under contrib.
-- >8 --
These Python scripts have "*/" at the end of the license header comment
blocks,
On Fri, 2023-12-15 at 01:59 +0100, Mark Wielaard wrote:
> Hi David,
>
> On Thu, Dec 14, 2023 at 10:01:39AM -0500, David Malcolm wrote:
> > > Once your patch is in please feel free to sent an email to
> > > build...@sourceware.org
> > > https://sourceware.org/mailman/listinfo/buildbot
> > > And we'
Hi,
this patch adds new option -falign-all-functions which works like
-falign-functions, but applies to all functions including those in cold
regions. As discussed in the PR log, this is needed for atomically
patching function entries in the kernel.
An option would be to make -falign-function man
On Wed, 2024-01-03 at 00:41 +, Joseph Myers wrote:
> On Tue, 2 Jan 2024, David Malcolm wrote:
>
> > > > + #print(f'{url_suffix=} {index_text=}')
> > >
> > > Various commented-out or "if 0" debugging code like this should
> > > probably
> > > be removed (or made into an actual runtime
As another followup to r14-6057-g12b67d1e13b3cf, optionally add SARIF
property bags to threadFlowLocation objects when writing out diagnostic
paths, and add analyzer-specific properties to them.
This was useful for debugging PR analyzer/112790.
Successfully bootstrapped & regrtested on x86_64-pc-
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Successful run of analyzer integration tests on x86_64-pc-linux-gnu.
Pushed to trunk as r14-6918-g5743e1899d5964.
gcc/analyzer/ChangeLog:
PR analyzer/112790
* checker-event.cc (class inlining_info): Move to...
*
Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Successful run of analyzer integration tests on x86_64-pc-linux-gnu.
Pushed to trunk as r14-6917-gdb5b01d282a0e3.
gcc/analyzer/ChangeLog:
PR analyzer/113222
* access-diagram.cc (valid_region_spatial_item::add_boundaries
I intend to commit this as obvious later today.
-- >8 --
contrib/ChangeLog:
* unicode/gen_wcwidth.py: Add sys.argv[0] to usage error.
---
contrib/unicode/gen_wcwidth.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/unicode/gen_wcwidth.py b/contrib/unicode/g
Hello, everyone.
Our "Arm64 on Windows Ecosystem" team is currently working on adding
aarch64-w64-mingw32 target and we've noticed that recent commit adding SME
support (https://gcc.gnu.org/pipermail/gcc-cvs/2023-December/394915.html) is
using .hidden and .size pseudo-ops that are not sup
Thanks, verified and pushed to the trunk!
On Thu, Dec 28, 2023 at 10:12 AM KuanLin Chen wrote:
>
> According to spec, fmv.h checks if the input operands are correctly
> NaN-boxed. If not, the input value is treated as an n-bit canonical NaN.
> This patch fixs the issue that operands returned by
I have successfully bootstrapped and regtested the patch on s390. Out
of curiosity I also ran some benchmarks which didn't show much changes
except in one case which I will have to analyze further. If there is
anything interesting I will reach back to you.
Cheers,
Stefan
On Mon, Jan 01, 2024 at
On Thu, 4 Jan 2024 at 12:01, Arsen Arsenović wrote:
>
>
> Jonathan Wakely writes:
>
> > On Thu, 21 Dec 2023 at 21:26, Arsen Arsenović wrote:
> >> +
> >> +template
> >> +concept _Stateless_alloc =
> >> (allocator_traits<_A>::is_always_equal::value
> >> + && d
Consider this following case:
void
f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
{
for (int i = 0; i < n; i++)
{
int tmp = b[i] + 15;
int tmp2 = tmp + b[i];
c[i] = tmp2 + b[i];
d[i] = tmp + tmp2 + b[i];
}
}
Current dynamic LMUL cos
Jonathan Wakely writes:
> On Thu, 21 Dec 2023 at 21:26, Arsen Arsenović wrote:
>> +
>> +template
>> +concept _Stateless_alloc = (allocator_traits<_A>::is_always_equal::value
>> + && default_initializable<_A>);
>
> The _A here is a BADNAME and needs to be mor
> -Original Message-
> From: Kyrylo Tkachov
> Sent: Thursday, January 4, 2024 11:12 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com
> Subject: RE: [PATCH 20/21]Arm: Add Advanced SIMD cbranch implementation
>
> Hi
Hi Tamar,
> -Original Message-
> From: Tamar Christina
> Sent: Thursday, January 4, 2024 11:06 AM
> To: Tamar Christina ; gcc-patches@gcc.gnu.org
> Cc: nd ; Ramana Radhakrishnan
> ; Richard Earnshaw
> ; ni...@redhat.com; Kyrylo Tkachov
>
> Subject: RE: [PATCH 20/21]Arm: Add Advanced SIMD
Ping,
---
Hi All,
This adds an implementation for conditional branch optab for AArch32.
The previous version only allowed operand 0 but it looks like cbranch
expansion does not check with the target and so we have to implement all.
I therefore did not commit it. This is a larger version. I've
On Thu, 21 Dec 2023 at 21:26, Arsen Arsenović wrote:
> +
> +template
> +concept _Stateless_alloc = (allocator_traits<_A>::is_always_equal::value
> + && default_initializable<_A>);
The _A here is a BADNAME and needs to be more than one letter.
FAIL: 17_intro/b
On Thu, Jan 4, 2024 at 10:18 AM juzhe.zh...@rivai.ai
wrote:
>
> \ No newline at end of file
>
> Each file needs newline.
>
> I am not able to review arch stuff. This needs kito.
>
> Besides, Andrew Pinski want us defer theadvector to GCC-15.
Maybe I misread this (sorry if so), but I though that w
Hi!
The following testcase ICEs when rslt is SSA_NAME_OCCURS_IN_ABNORMAL_PHI
and we call replace_uses_by with a INTEGER_CST def, where it ICEs on:
if (e->flags & EDGE_ABNORMAL
&& !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (val))
because val is not an SSA_NAME. One way would
在 2024/1/4 下午5:05, chenglulu 写道:
在 2024/1/4 下午12:05, Xi Ruoyao 写道:
On Thu, 2024-01-04 at 11:58 +0800, chenglulu wrote:
在 2024/1/4 上午11:51, Xi Ruoyao 写道:
On Wed, 2023-12-27 at 16:46 +0800, Lulu Cheng wrote:
+(define_insn "movdi_pcrel64"
+ [(set (match_operand:DI 0 "register_operand" "=&r")
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extens
emit_library_call_value_1 calls emit_push_insn with NULL_TREE
for TYPE. Sometimes emit_push_insn needs to assign a temp with
that TYPE, which causes a segfault.
Fixed by computing the TYPE from MODE when needed.
Original patch by Thorsten Otto.
gcc/
2024-01-03 Thorsten Otto
Mika
\ No newline at end of file
Each file needs newline.
I am not able to review arch stuff. This needs kito.
Besides, Andrew Pinski want us defer theadvector to GCC-15.
I have no strong opinion here.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-04 17:15
收件人： 钟居哲; Jeff Law; gcc-patches
抄送： ji
Hi Juzhe,
So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
Joshua
--
发件人：钟居哲
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law;
"cooper.joshua";
"gcc-pa
Hi!
We expand __builtin_popcount* (x) == 1 as
x ^ (x - 1) > x - 1, either unconditionally in tree-ssa-math-opts.cc
if we don't have a direct optab support for popcount, or during
expansion where we compare the costs of comparison of the popcount
against one vs. the above expression.
As mentioned i
On Thu, Jan 4, 2024 at 1:03 AM Srinivas Yadav
wrote:
>
>
> Hi,
>
> Thanks a lot for the review. Sorry for the very late reply.
>
> The following are my comments on the feedback.
>
>>
>> The main thing that worries me is:
>>
>> #if _GLIBCXX_SIMD_HAVE_SVE
>> constexpr inline int __sve_vectorized
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