[PATCH v5] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

This patch adds the 'Zfa' extension for riscv, which is based on: ( https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 ) latest 'Zfa' change on the master branch of the RISC-V ISA Manual as of this writing. The Wiki Page (details): ( https://github.com/a4lg

[PATCH] RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.

MAX_MATCH_SCORE is not assigned anywhere except initialized to 0, causing BEST_MATCH_MULTI_LIB to always be 0 or -1, which will cause the result of TARGET_COMPUTE_MULTILIB hook to fail. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: --- gcc/common/config/riscv/riscv-common.cc | 5

[PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.

The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain potential risks: When the architecture adds pre-processing to `define_insn "adddi3"`, such as `define_expend "adddi3"`, the gen_expand will be automatically called here, causing the patern to emit directly, which will ca

[PATCH] RISC-V: Fixbug for fsflags instruction error using immediate.

The pattern mistakenly believes that fsflags can use immediate numbers, but in fact it does not support it. Immediate numbers should use fsflagsi. For example: __builtin_riscv_fsflags(4); The following error occurred: /tmp/ccoWdWqT.s: Assembler messages: /tmp/ccoWdWqT.s:14: Error: illegal operand

[PATCH v2] RISC-V: Fixbug for fsflags instruction error using immediate.

The pattern mistakenly believes that fsflags can use immediate numbers, but in fact it does not support it. Immediate numbers should use fsflagsi. For example: __builtin_riscv_fsflags(4); The following error occurred. /tmp/ccoWdWqT.s: Assembler messages: /tmp/ccoWdWqT.s:14: Error: illegal operand

Re: [PATCH] RISC-V: Fixbug for fsflags instruction error using immediate.

> Hi Jin, > > this looks reasonable. Would you mind adding (small) test cases > still to make sure we don't accidentally reintroduce the problem? > > Regards > Robin Ok, I have already sent the v2 version, please review it again, thanks. Link: https://gcc.gnu.org/pipermail/gcc-patches/2023-Ju

[PATCH v3] RISC-V: Fixbug for fsflags instruction error using immediate.

The pattern mistakenly believes that fsflags can use immediate numbers, but in fact it does not support it. Immediate numbers should use fsflagsi. For example: __builtin_riscv_fsflags(4); The following error occurred. /tmp/ccoWdWqT.s: Assembler messages: /tmp/ccoWdWqT.s:14: Error: illegal operand

Re: [PATCH v3] RISC-V: Fixbug for fsflags instruction error using immediate.

> - [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)] > + [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r")] UNSPECV_FSCSR)] > > If you don't allow immediate value in range 0 ~ 31, it should be > "register_operand" instead of "csr_operand". > > I think direc

Re: Re: [PATCH v3] RISC-V: Fixbug for fsflags instruction error using immediate.

> So I guess you should change `fscsr` to `fscsr%i0` instead of dropping > K from the constraint list? > Sorry, you are right. I thought you were talking about fsflags, but I didn't notice it was fscsr. I'll correct it right away. > On Wed, Jul 26, 2023 at 11:42 AM juzhe.zh...@rivai.ai > wrote:

[PATCH v4] RISC-V: Fixbug for fsflags instruction error using immediate.

The pattern mistakenly believes that fsflags can use immediate numbers, but in fact it does not support it. Immediate numbers should use fsflagsi. For example: __builtin_riscv_fsflags(4); The following error occurred. /tmp/ccoWdWqT.s: Assembler messages: /tmp/ccoWdWqT.s:14: Error: illegal operand

Re: [PATCH] RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE.

> On 5/29/23 06:46, Jeff Law wrote: > > > > > > On 5/29/23 05:01, Jin Ma wrote: > >> Reference: > >> https://github.com/gcc-mirror/gcc/commit/d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5 > >> > >> RISC-V should also be implemented to handle no_insn patterns for > >> pipelining. > >> > >> gcc/Change

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

> Hi Jin Ma, > > On 5/16/23 00:06, jinma via Gcc-patches wrote: > > On 5/15/23 07:16, Jin Ma wrote: > >> > >> Do we also need to check Z[FDH]INX too? > >> > >> Otherwise it looks pretty good. We just need to wait for everything to > >> freeze and finalization on the assembler interface. > >> > >>

[PATCH v10] RISC-V: Add support for the Zfa extension

This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2023-April/127060.html What needs special explanation is: 1, According to riscv-spec, "The FCVTMO

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

> > Hi Jin Ma, > > > > On 5/16/23 00:06, jinma via Gcc-patches wrote: > > > On 5/15/23 07:16, Jin Ma wrote: > > >> > > >> Do we also need to check Z[FDH]INX too? > > >> > > >> Otherwise it looks pretty good. We just need to wait for everything to > > >> freeze and finalization on the assembler in

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

Additional links： v10, the patch that needs to be reviewed again: http://patchwork.ozlabs.org/project/gcc/patch/20230814055033.1995-1-ji...@linux.alibaba.com/ v9 and the previous review comments: http://patchwork.ozlabs.org/project/gcc/patch/20230515131628.953-1-ji...@linux.alibaba.com/ Zfa patch

[PATCH v2] In the pipeline, USE or CLOBBER should delay execution if it starts a new live range.

CLOBBER and USE does not represent real instructions, but in the process of pipeline optimization, they will wait for transmission in ready list like other insns, without considering resource conflicts and cycles. This results in a multi-issue CPU architecture that can be issued at any time if othe

RE: [2/2] RISC-V: Constant FP Optimization with 'Zfa'

Hi Tsukasa, What a coincidence, I also implemented zfa extension, which also includes fli related instructions :) links: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627294.html > + if (!TARGET_HARD_FLOAT || !TARGET_ZFA) > +return result; > + switch (GET_MODE (x)) > +{ > +

Re: [2/2] RISC-V: Constant FP Optimization with 'Zfa'

On 2023/08/15 12:38, Tsukasa OI wrote: > > On 2023/08/14 21:51, Jin Ma wrote: > >> Hi Tsukasa, > >> What a coincidence, I also implemented zfa extension, which also > >> includes fli related instructions :) > > > > Hi, I'm glad to know that someone is working on this extension more > > comprehe

[PATCH] RISC-V: Added zvfh support for zfa extensions.

This is a follow-up for the zfa extension, added according to the recommendations for zvfh and patch of Tsukasa OI . At the same time, zfa-fli-5.c of which is also based on the patch. Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627284.html https://gcc.gnu.org/pipermail/gcc-patches

Re: [PATCH v2] In the pipeline, USE or CLOBBER should delay execution if it starts a new live range.

ping Ref: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627341.html https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621296.html

Re: [PATCH] In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range.

ping: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619951.html Ref: http://patchwork.ozlabs.org/project/gcc/patch/20230323080734.423-1-ji...@linux.alibaba.com/

Re: [PATCH] In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range.

> On 5/29/23 04:51, Jin Ma wrote: > >Unrecog insns (such as CLOBBER, USE) does not represent real > > instructions, but in the > > process of pipeline optimization, they will wait for transmission in ready > > list like > > other insns, without considering resource conflicts and cycles. This

[PATCH] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.

gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions. * config/riscv/riscv.md (riscv_frcsr): New patterns. (riscv_fscsr): Likewise. gcc/testsuite/Chang

[PATCH v2] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.

In order to avoid interrupt functions to change the FCSR, it needs to be saved and restored at the beginning and end of the function. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in i

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

> diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index ebc1ed7d7e4..2b3ff1f5b8e 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -102,6 +102,8 @@ static const riscv_implied_info_t riscv_i

Re: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

> diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md > index 5b70ab20758..6349f032bc8 100644 > --- a/gcc/config/riscv/iterators.md > +++ b/gcc/config/riscv/iterators.md > @@ -61,10 +61,15 @@ > ;; Iterator for hardware-supported floating-point modes. > (define_mode_iterator

[PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2023-April/127060.html What needs special explanation is: 1, The immediate number of the instruct

[PATCH] Fix type error of 'switch (SUBREG_BYTE (op)).'

For example: (define_insn "mov_lowpart_sidi2" [(set (match_operand:SI0 "register_operand" "=r") (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))] "TARGET_64BIT" "mov\t%0,%1") (define_insn "mov_highpart_sidi2" [(set (match_operand:SI0 "register_ope

[PATCH] RISC-V: Remove trailing spaces on lines.

gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Remove trailing spaces on lines. * config/riscv/riscv.cc (riscv_legitimize_move): Likewise. * config/riscv/riscv.h (enum reg_class): Likewise. * config/riscv/riscv.md: Likewise. --- gcc/common/config/ris

[PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

When testing a extension, it is often necessary for a certain program not to need some kind of extension, such as the bitmanip extension, to evaluate the performance or codesize of the extension. However, the current multilib rules will report an error when it is not a superset of the MULTILIB_REQU

Re: [PATCH] Fix type error of 'switch (SUBREG_BYTE (op)).'

> > On 5/17/23 03:03, Jin Ma wrote: > >> For example: > >> (define_insn "mov_lowpart_sidi2" > >>[(set (match_operand:SI0 "register_operand" "=r") > >> (subreg:SI (match_operand:DI 1 "register_operand" " r") 0))] > >>"TARGET_64BIT" > >>"mov\t%0,%1") > >> > >> (defin

[PATCH] RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks.

When the last insn1 of BB1 and the first insn2 of BB2 are fusion, insn2 will clear all dependencies in the function chain_to_prev_insn, resulting in insn2 may mov to any BB, and the program calculation result is wrong. gcc/ChangeLog: * sched-deps.cc (sched_macro_fuse_insns): Insns should

[PATCH] RISC-V: Add the option "-mno-multilib-check" to disable multilib checks.

When testing a extension, it is often necessary for a certain program not to need some kind of extension, such as the bitmanip extension, to evaluate the performance or codesize of the extension. However, the current multilib rules will report an error when it is not a superset of the MULTILIB_REQU

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

> > When testing a extension, it is often necessary for a certain program not to > > need some kind of extension, such as the bitmanip extension, to evaluate the > > performance or codesize of the extension. However, the current multilib > > rules > > will report an error when it is not a superset

Re: [PATCH] RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation.

> > > > When testing a extension, it is often necessary for a certain program > > > > not to > > > > need some kind of extension, such as the bitmanip extension, to > > > > evaluate the > > > > performance or codesize of the extension. However, the current multilib > > > > rules > > > > will rep

[PATCH] In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range.

Unrecog insns (such as CLOBBER, USE) does not represent real instructions, but in the process of pipeline optimization, they will wait for transmission in ready list like other insns, without considering resource conflicts and cycles. This results in a multi-issue CPU architecture that can be

[PATCH] RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE.

Reference: https://github.com/gcc-mirror/gcc/commit/d0bc0cb66bcb0e6a5a5a31a9e900e8ccc98e34e5 RISC-V should also be implemented to handle no_insn patterns for pipelining. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): New function. (TARGET_SCHED_VARIABLE_ISS

[RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.

hi, Are there any new developments about Zfb? Are there any plans to implement the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in llvm, maybe we should do the same on gcc. Ref: https://reviews.llvm.org/D151313 https://reviews.llvm.org/D150929

[PATCH] In the ready lists of pipeline, put unrecog insns (such as CLOBBER, USE) at the latest to issue.

Unrecog insns (such as CLOBBER, USE) does not represent real instructions, but in the process of pipeline optimization, they will wait for transmission in ready list like other insns, without considering resource conflicts and cycles. This results in a multi-issue CPU architecture that can be

[PATCH] RISC-V: Adjust the parsing order of extensions to be consistent with riscv-spec and binutils.

The current order of gcc and binutils parsing extensions is inconsistent. According to latest risc-v spec, the canonical order in which extension names must appear in the name string specified in Table 29.1 is different from before. In the latest table, non-standard extensions must be listed aft

[PATCH] Fixed typo.

gcc/ada/ChangeLog: * gcc-interface/utils.cc (unchecked_convert): Fixed typo. --- gcc/ada/gcc-interface/utils.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ada/gcc-interface/utils.cc b/gcc/ada/gcc-interface/utils.cc index 392ec0b7f4e..0c4f8b90c8e 100644 --- a/g

[PATCH v8] RISC-V: Add the 'zfa' extension, version 0.2.

This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commits/zfb https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da The binutils-gdb for 'Zfa' extension: https://github.com/a4lg/binutils-gdb/commit

[PATCH v4] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

This patch adds the 'Zfa' extension for riscv, which is based on: ( https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 ) latest 'Zfa' change on the master branch of the RISC-V ISA Manual as of this writing. The Wiki Page (details): ( https://github.com/a4lg

Re: [PATCH v8] RISC-V: Add the 'zfa' extension, version 0.2.

On 4/19/23 03:57, Jin Ma wrote: > This patch adds the 'Zfa' extension for riscv, which is based on: >https://github.com/riscv/riscv-isa-manual/commits/zfb > https://github.com/riscv/riscv-isa-manual/commit/1f038182810727f5feca311072e630d6baac51da > > The binutils-gdb for 'Zfa' extensio

[PATCH] RISC-V: When the TARGET_COMPUTE_MULTILIB hook is implemented, check the version of each extension.

When there is an extension with different versions, the result of the TARGET_COMPUTE_MULTILIB hook is generally wrong, so the version needs to be considered. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::match_score): Match the version of each extensio

[PATCH] RISC-V: Don't report an error until the link phase if suitable multilib isn't found.

When suitable multilib isn't found, an error is not reported until the link period, which is inconsistent with the result of compiling option `-print-multi-directory`. For example, when suitable multilib isn't found, the return result of `-print-multi-directory` is the default value '.', while the

[PATCH v6] RISC-V: Add support for experimental zfa extension.

This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 latest 'Zfa' change on the master branch of the RISC-V ISA Manual as of this writing. The Wiki Page (details): https://github.com/a4lg/binu