Hi,
This patch is removing unnecessary armv9-a multilib variant which was
introduced in commit 32ba7860ccaddd5219e6dae94a3d0653e124c9dd (add
armv9-a architecture to -march). Now armv9-a(+simd) multilibs point to
already existing armv8-a(+simd) ones as there are no changes between
the two.
Users
Ping :)
> This patch is sorting issue with LS64 intrinsics tests failing with
> aarch64-linux-gnu_ilp32 target.
>
> Regtested on aarch64-linux-gnu_ilp32, aarch64-elf and aarch64_be-elf
> and no issues.
>
> OK to install?
>
> gcc/ChangeLog:
>
> PR target/103729
> *
This patch is sorting issue with LS64 intrinsics tests failing with
aarch64-linux-gnu_ilp32 target.
Regtested on aarch64-linux-gnu_ilp32, aarch64-elf and aarch64_be-elf
and no issues.
OK to install?
gcc/ChangeLog:
PR target/103729
*
> -Original Message-
> From: Richard Sandiford
> Sent: 16 December 2021 10:46
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; christophe.l...@linaro.org; Richard Earnshaw
> ; Kyrylo Tkachov ;
> Marcus Shawcroft
> Subject: Re: [PATCH][GCC] aarch
Hi,
This patch is sorting issue with LS64 intrinsics tests failing with
AArch64_be targets.
Regtested on aarch64_be_elf and aarch64_elf, no issues.
OK to install?
gcc/ChangeLog:
PR target/PR103729
* config/aarch64/aarch64-simd.md (aarch64_movv8di): Allow big endian
> -Original Message-
> From: Richard Sandiford
> Sent: 14 December 2021 11:58
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH][GCC] aarch64: Add LS64 extension and intrinsic
Wirkus
> -Original Message-
> From: Richard Sandiford
> Sent: 15 November 2021 13:43
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH][GCC] aarch64: Add LS64 extension and in
> -Original Message-
> From: Richard Sandiford
> Sent: 17 November 2021 10:08
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Kyrylo Tkachov ;
> Marcus Shawcroft
> Subject: Re: [PATCH][GCC] aarch64: Add new vector mode V8DI
>
d no issues.
OK for master?
gcc/ChangeLog:
2021-11-11 Przemyslaw Wirkus
* config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
Define AARCH64_LS64_BUILTIN_LD64B, AARCH64_LS64_BUILTIN_ST64B,
AARCH64_LS64_BUILTIN_ST64BV, AARCH64_LS64_BUILTIN_ST64BV0.
> >
> > gcc/ChangeLog:
> >
> > * config/arm/arm-cpus.in (cortex-a710): New CPU.
> > * config/arm/arm-tables.opt: Regenerate.
> > * config/arm/arm-tune.md: Regenerate.
> > * doc/invoke.texi: Update d
Hi,
This patch is adding new V8DI mode which will be used with new Armv8.7-A
LS64 extension intrinsics.
Regtested on aarch64-elf and no issues.
OK for master?
gcc/ChangeLog:
2021-11-10 Przemyslaw Wirkus
* config/aarch64/aarch64-modes.def (VECTOR_MODE): New V8DI mode
> > > -Original Message-
> > > From: Przemyslaw Wirkus
> > > Sent: 18 October 2021 10:37
> > > To: gcc-patches@gcc.gnu.org
> > > Cc: Richard Earnshaw ; Ramana
> > > Radhakrishnan ; Kyrylo Tkachov
> > > ; ni...@redhat.com
>
Ping :)
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 18 October 2021 10:40
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
> ; ni...@redhat.com
> Subject: [PATCH][GCC] arm: enable cortex-a710 CPU
>
>
Ping :)
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 18 October 2021 10:37
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw ; Ramana
> Radhakrishnan ; Kyrylo Tkachov
> ; ni...@redhat.com
> Subject: [PATCH][GCC] arm: add armv9-a architecture to -march
-tune.md: Regenerate.
* doc/invoke.texi: Update docs.
--
kind regards,
Przemyslaw Wirkus
Staff Compiler Engineer | Arm
. . . . . . . . . . . . . . . . . . . . . . . . . .
Arm.com diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index
new armdef.
--
kind regards,
Przemyslaw Wirkus
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index d0d0d0f1c7e4176fc4aa30d82394fe938b083a59..3756ba56c6ea36fa9d017347bd73b27ab7752325 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -132,6 +132,9
> > On Thu, Sep 30, 2021, 3:37 PM Przemyslaw Wirkus
> > <mailto:przemyslaw.wir...@arm.com> wrote:
> > Subject: Re: [PATCH][GCC] arm: Add Cortex-R52+ multilib
> >
> > I think the RTEMS multilibs are based on the products that RTEMS supports,
> > so
> Subject: RE: [PATCH][GCC] aarch64: enable cortex-x2 CPU
>
>
>
> > -Original Message-
> > From: Kyrylo Tkachov
> > Sent: Friday, October 1, 2021 1:17 PM
> > To: Przemyslaw Wirkus ; gcc-
> > patc...@gcc.gnu.org
> > Cc: Richard Ear
> Hi Przemek,
>
> > -Original Message-
> > From: Przemyslaw Wirkus
> > Sent: Wednesday, September 22, 2021 9:35 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Richard Earnshaw ; Richard Sandiford
> > ; Marcus Shawcroft
> > ; Kyrylo Tkachov
>
> -Original Message-
> From: Kyrylo Tkachov
> Sent: 01 October 2021 13:16
> To: Przemyslaw Wirkus ; gcc-
> patc...@gcc.gnu.org
> Cc: Richard Earnshaw ; Richard Sandiford
> ; Marcus Shawcroft
>
> Subject: RE: [PATCH][GCC] aarch64: enable cortex-a710 CPU
Patch is fixing AARCH64_FL_V9 flag value which is now wrongly set due to
merge error.
Committed as obvious.
gcc/ChangeLog:
* config/aarch64/aarch64.h (AARCH64_FL_V9): Update value.
---
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index
> > Subject: [PATCH][GCC] aarch64: add armv9-a to -march
> >
> > Patch is adding new command line option 'armv9-a' to -march.
> >
> > OK for master?
>
> Ok.
commit f0688d42c9b74a6999548ff2e79ae440b049b87f
> Thanks,
> Kyrill
>
> >
>
> Subject: Re: [PATCH][GCC] arm: Enable Cortex-R52+ CPU
>
> This is OK
Applying as r52+ is now in Binutils.
commit cd08eae26ed23497ace5f4ee6f3a41eb5bd36c38
> Ramana
>
> On 22/09/2021, 09:45, "Przemyslaw Wirkus"
> wrote:
>
> Patch is adding Cortex-
> Subject: Re: [PATCH][GCC] arm: Add Cortex-R52+ multilib
>
> I think the RTEMS multilibs are based on the products that RTEMS supports,
> so this is really the RTEMS maintainers' call.
>
> Joel?
Ping :)
> On 22/09/2021 09:46, Przemyslaw Wirkus via Gcc-patches wrote
Patch is adding multilib entries for `cortex-r52plus` CPU.
See: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus
OK for master?
gcc/ChangeLog:
2021-09-16 Przemyslaw Wirkus
* config/arm/t-rtems: Add "-mthumb -mcpu=cortex-r52plus
-mfloat-abi=hard"
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
flag for -mcpu option.
See: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus
OK for master?
gcc/ChangeLog:
2021-09-22 Przemyslaw Wirkus
* config/arm/arm-cpus.in: Add Cortex-R52+ CPU.
* config
Patch is adding 'cortex-x2' to -mcpu command line option.
OK for master?
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-X2 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update
Patch is adding 'cortex-a710' to -mcpu command line option.
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-A710 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update docs
Patch is adding 'cortex-a510' to -mcpu command line option.
gcc/ChangeLog:
2021-09-02 Przemyslaw Wirkus
* config/aarch64/aarch64-cores.def (AARCH64_CORE): New
Cortex-A510 core.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Update docs
Patch is adding new command line option 'armv9-a' to -march.
OK for master?
gcc/ChangeLog:
2021-09-22 Przemyslaw Wirkus
* config/aarch64/aarch64-arches.def (AARCH64_ARCH): Added
armv9-a.
* config/aarch64/aarch64.h (AARCH64_FL_V9): New.
(AARCH64_FL_FOR_ARCH9
> -Original Message-
> From: Christophe Lyon
> Sent: 03 June 2021 10:10
> To: Przemyslaw Wirkus
> Cc: Vladimir Makarov ; ja...@redhat.com; Richard
> Earnshaw ; Richard Biener
> ; gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
>
> Subject: Re: [backport gcc1
> -Original Message-
> From: Christophe Lyon
> Sent: 03 June 2021 09:45
> To: Przemyslaw Wirkus
> Cc: Vladimir Makarov ; ja...@redhat.com; Richard
> Earnshaw ; Richard Biener
> ; gcc-patches@gcc.gnu.org; Ramana Radhakrishnan
>
> Subject: Re: [backport gcc1
Hi,
> -Original Message-
> From: Vladimir Makarov
> Sent: 31 May 2021 16:52
> To: Przemyslaw Wirkus ; Richard Biener
>
> Cc: gcc-patches@gcc.gnu.org; ja...@redhat.com; ni...@redhat.com;
> Richard Earnshaw ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
>
> Subj
> -Original Message-
> From: Richard Biener
> Sent: 02 February 2021 10:08
> To: Przemyslaw Wirkus
> Cc: Vladimir Makarov ; gcc-patches@gcc.gnu.org;
> ja...@redhat.com; ni...@redhat.com; Richard Earnshaw
> ; Ramana Radhakrishnan
> ; Kyrylo Tkachov
>
> Subj
> On 2021-01-18 7:50 a.m., Richard Biener wrote:
> > On Mon, 18 Jan 2021, Przemyslaw Wirkus wrote:
> >
> >> Hi all,
> >>
> >> Can we backport PR97969 patch to GCC 10 and (maybe) GCC 9 ?:
> >> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97969
&g
If no objections.
Kind regards,
Przemyslaw Wirkus
gcc-10 and gcc-9.
I've regression tested this patch on both gcc-10 and gcc-9 branched for
x86_64 cross (arm-eabi target) and no issues.
OK for gcc-10 and gcc-9 ?
PS: I can commit if approved.
Kind regards,
Przemyslaw Wirkus
> Przemyslaw Wirkus writes:
> > > This is a bug in the vectoriser: the vectoriser shouldn't generate
> > > IFN_REDUC_MAX calls that the target doesn't support.
> > >
> > > I think the problem comes from using the wrong interface to get th
> > Subject: [PATCH][GCC] arm: Add support for Cortex-A78C
> >
> > This patch adds support for -mcpu=cortex-a78c command line option.
> > For more information about this processor, see [0]:
> >
> > [0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-
> > a78c
> >
> > OK from
> Przemyslaw Wirkus writes:
> > Hi,
> >
> > Recent 'support SVE comparisons for unpacked integers' patch extends
> > operands of define_expands from SVE_FULL to SVE_ALL. This causes an
> > ICE hence this PR patch.
> >
> > This patch
Hi,
Recent 'support SVE comparisons for unpacked integers' patch extends
operands of define_expands from SVE_FULL to SVE_ALL. This causes an ICE
hence this PR patch.
This patch adds this relaxation for:
+ reduc__scal_ and
+ arch64_pred_reduc__
in order to support extra modes. Missing modes were
> > OK for master ?
> >
> > gcc/ChangeLog:
> >
> > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-
> A78C core.
> > * config/aarch64/aarch64-tune.md: Regenerate.
> > * doc/invoke.texi: Update docs.
>
> OK, thanks.
> Richard
commit
> > Subject: [PATCH][GCC] aarch64: Add +pauth to -march
> >
> > New +pauth (Pointer Authentication from Armv8.3-A) feature option for
> > -march command line option.
> >
> > Please note that majority of PAUTH instructions are implemented behind
> > HINT instruction. PAUTH stays a Armv8.3-A feature
This patch adds support for -mcpu=cortex-a78c command line option.
For more information about this processor, see [0]:
[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
OK from master ?
gcc/ChangeLog:
* config/arm/arm-cpus.in: Add Cortex-A78C core.
*
This patch adds support for -mcpu=cortex-a78c command line option.
For more information about this processor, see [0]:
[0] https://developer.arm.com/ip-products/processors/cortex-a/cortex-a78c
OK for master ?
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
New +pauth (Pointer Authentication from Armv8.3-A) feature option for
-march command line option.
Please note that majority of PAUTH instructions are implemented behind HINT
instruction. PAUTH stays a Armv8.3-A feature but now can be assigned to other
architectures or CPUs.
Patch includes:
- new
> >> >> gcc/ChangeLog:
> >> >>
> >> >> * config/aarch64/aarch64-option-extensions.def
> >> >> (AARCH64_OPT_EXTENSION): New +flagm option in -march for AArch64.
> >> >> * config/aarch64/aarch64.h (AARCH64_FL_FLAGM): Add new flagm
> >> >> extension bit mask.
> >> >> (AARCH64_FL_FOR_ARCH8_4): Add
> >> gcc/ChangeLog:
> >>
> >> * config/aarch64/aarch64-option-extensions.def
> >> (AARCH64_OPT_EXTENSION): New +flagm option in -march for AArch64.
> >> * config/aarch64/aarch64.h (AARCH64_FL_FLAGM): Add new flagm
> >> extension bit mask.
> >> (AARCH64_FL_FOR_ARCH8_4): Add flagm to Armv8.4-A.
> >
New +flagm (Condition flag manipulation from Armv8.4-A) feature option for
-march command line option.
Please note that FLAGM stays an Armv8.4-A feature but now can be
assigned to other architectures or CPUs.
OK for master?
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def
> > Backport of commit 6abd428605e3a279e533fde1cecbc9735ce03b66
> > from master branch.
> >
> > OK for gcc-10 ?
Cherry-picked and applied: commit eb061188276d0ac9ec53fd5619c578a6bce6b129
> Ok.
> Thanks,
> Kyrill
> > This patch is a backport of PR97251 fix already commited to master.
> >
> > OK for gcc-10 branch ?
Cherry-picked and applied: commit d121b3259b77203e62402024add1538c1bdf5fdf
> Ok.
> Thanks,
> Kyrill
Backport of commit 6abd428605e3a279e533fde1cecbc9735ce03b66
from master branch.
OK for gcc-10 ?
This patch fixes ICEs in gcc.dg/torture/float16-basic.c for
-march=armv8.1-m.main+mve -mfloat-abi=hard. The problem was
that an fp16 argument was (rightly) being passed in FPRs,
but the fp16 move
This patch is a backport of PR97251 fix already commited to master.
OK for gcc-10 branch ?
This patch fixes ICEs when compiling
gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c with
-mfp16-format=ieee -mfloat-abi=hard -march=armv8.1-m.main+mve
-mpure-code.
The existing conditions in the
t; [1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-
> > a78ae
> >
> > OK for master branch ?
commit 60e4b3cade5c63f919df4ddc0f0d23261f968e13
> Ok.
> Thanks,
> Kyrill
>
> >
> > kind regards
> > Przemyslaw Wirkus
&g
; > [1]:
> > https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae
> >
> > OK for master branch ?
commit b6860cb96d038fe7519797adfb9c3c2e635234de
> Ok.
> Thanks,
> Kyrill
>
> >
> > kind regards
> > Przemyslaw Wirkus
> >
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.
[0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
[1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae
OK for master branch ?
kind regards
Przemyslaw Wirkus
gcc
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.
[0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
[1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae
OK for master branch ?
kind regards
Przemyslaw Wirkus
gcc/ChangeLog
> Ok. Please make sure aarch64-tune.md is properly regenerated when
> committing as Alex has been adding new CPUs in there recently too.
commit f836f3bc8f76ef3e3ad21762590302ad11abc9f8
> Thanks,
> Kyrill
>
> >
> > kind regards,
> > Przemyslaw Wirkus
> &
> Ok, but please make sure this is properly rebased on top of Alex's patches
> that have recently gone in in this area.
commit 0eef5eea2b42d892df52b655e55458f27ac3fb81
> Thanks,
> Kyrill
>
>
> kind regards,
> Przemyslaw Wirkus
>
> gcc/ChangeLog:
>
>
Hi,
This change adds support for the Arm Cortex-X1 CPU. For more information about
this processor, see [0].
[0] : https://www.arm.com/products/cortex-x
OK for master branch ?
kind regards,
Przemyslaw Wirkus
gcc/ChangeLog:
* config/arm/arm-cpus.in: Add Cortex-X1 core
Hi,
This change adds support for the Arm Cortex-X1 CPU in AArch64 GCC. For more
information about this processor, see [0].
[0] : https://www.arm.com/products/cortex-x
OK for master branch ?
kind regards,
Przemyslaw Wirkus
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Cortex
> Przemyslaw Wirkus writes:
> > Hello maintainers,
> >
> > Can I backport this patch to GCC 10 please ?
>
> Sure, that's fine.
commit 41d22ec51c4190133a082197e7ff67b4741fc09b
Date: Fri Aug 28 11:31:04 2020 +0100
> Thanks,
> Richard
>
> >
>
Hello maintainers,
Can I backport this patch to GCC 10 please ?
Regards
Przemyslaw
> Committed with:
>
> commit b648814c02eb418aaf27897c480452172ee96303
> Date: Fri Aug 28 11:31:04 2020 +0100
>
> Kind regards,
> Przemyslaw
> Sorry for the micromanagement, but I think this is easier to read if it flows
> as a
> single paragraph:
[snip...]
> I should have realised this would be the case, sorry, but now that there's
> only
> one rewrite, this should simply be:
>
> "&& reload_completed
>&& register_operand
Hi Richard,
Thank you for your comments.
I've attached updated patch with changes reflecting your comments.
Kind regards,
Przemyslaw
> -Original Message-
> From: Richard Sandiford
> Sent: 19 August 2020 11:32
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; R
Hi,
Problem is related to that operand 4 (In original pattern
*cond_sub_any_const) is no longer the same as operand 1, and so
the pattern doesn't match the split condition.
Pattern *cond_sub_any_const is being split by this patch into two
separate patterns:
* Pattern *cond_sub_relaxed_const now
Commited cd91a084877dabcc53aec57ab70ca4fc32f3d985
> -Original Message-
> From: Przemyslaw Wirkus
> Sent: 22 July 2020 09:49
> To: Richard Sandiford
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH][GCC][aarch64] Generation of adjusted ldp/stp for vector
ChangeLog:
2020-07-22 Przemyslaw Wirkus
* MAINTAINERS (Write After Approval): Add myself.
---
diff --git a/MAINTAINERS b/MAINTAINERS
index
d1343d33f1abb4a4bec7deac6c86551b83ecbdf1..300c10edf196d5698ea0fb0f8ee6a8f50a642292
100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -645,6 +645,7
[snip...]
> Przemek, if you don't have commit access already, please follow the steps on
> https://gcc.gnu.org/gitwrite.html (happy to sponsor).
Done.
Thank you, Richard, for sponsoring this and all the support!
Kind regards,
Przemek
Richard,
In attachment reworked patch.
> -Original Message-
> From: Richard Sandiford
> Sent: 13 July 2020 17:13
> To: Przemyslaw Wirkus
> Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw
> ; Marcus Shawcroft
> ; Kyrylo Tkachov
> Subject: Re: [PATCH][GCC][aarch64
Hi,
Introduce simple peephole2 optimization which substitutes a sequence of
four consecutive load or store (LDR, STR) instructions with two load or
store pair (LDP, STP) instructions for 2 element supported vector modes
(V2SI, V2SF, V2DI, and V2DF).
Generated load / store pair instruction offset
gt;
> > > On Fri, 19 Jun 2020, Przemyslaw Wirkus wrote:
> > >
> > > > Hi all,
> > > >
> > > > Pattern "(x | y) - y" can be optimized to simple "(x & ~y)" andn
> > > > pattern.
> > > >
> >
On Fri, Jun 19 2020 Marc Glisse wrote:
> (not a reviewer)
>
> It looks fine to me. Do we already handle the related (x|y)^y and (x|y)&~y ?
These are already in match.pd:
/* (X | Y) ^ X -> Y & ~ X*/
/* (x | y) & ~x -> y & ~x */
> On Fri, 19 Jun 2020, Prze
Hi all,
Pattern "(x | y) - y" can be optimized to simple "(x & ~y)" andn pattern.
Bootstrapped and tested on aarch64-none-linux-gnu.
OK for master ?
Cheers,
Przemyslaw
gcc/ChangeLog:
PR tree-optimization/94880
* match.pd (A | B) - B -> (A & ~B): New simplification.
Hi,
Pattern "(x | y) - y" can be optimized to simple "(x & ~y)" andn pattern.
Bootstrapped and tested on aarch64-none-linux-gnu.
OK for master ?
Cheers,
Przemyslaw
gcc/ChangeLog:
PR tree-optimization/94880
* match.pd (A | B) - B -> (A & ~B): New simplification.
On 12 June 2020 20:55 Andrew Pinski wrote:
> Subject: Re: [PATCH][GCC][Aarch64]: Fix for PR94880: Failure to recognize
> andn pattern
>
> On Fri, Jun 12, 2020 at 7:50 AM Przemyslaw Wirkus
> wrote:
> >
> > Hi all,
> >
> > Pattern "(x | y) - y" c
Hi all,
Pattern "(x | y) - y" can be optimized to simple "(x & ~y)" andn pattern.
So, for the example code:
$ cat main.c
int
f_i(int x, int y)
{
return (x | y) - y;
}
long long
f_l(long long x, long long y)
{
return (x | y) - y;
}
typedef int v4si __attribute__ ((vector_size
gcc/ChangeLog:
2020-01-10 Przemyslaw Wirkus
Backport from trunk
* config/arm/t-multilib: Use arm->thumb multilib reuse rules
on a-profile.
Ok for gcc-9-branch?
kind regards
Przemyslaw Wirkusdiff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib
that they remain fixed ;-)
gcc/ChangeLog:
2020-01-08 Przemyslaw Wirkus
Backport from trunk
PR target/93188
* config/arm/t-multilib (MULTILIB_MATCHES): Add rules to match
armv7-a{+mp,+sec,+mp+sec} to appropriate armv7 multilib variants
when only building rm-profile
019-05-29 Przemyslaw Wirkus
* config/arm/iterators.md (VABAL): New int iterator.
* config/arm/neon.md (sadv16qi): New define_expand.
* config/arm/unspecs.md ("unspec"): Define UNSPEC_VABAL_S,
UNSPEC_VABAL_U
values.
2019-05-29 Przemyslaw Wirkus
d18, d19
vpadd.i32 d18, d18, d18
vmov.32 r0, d18[0]
Bootstrapped and tested on arm-none-linux-gnueabihf.
Ok for trunk?
Thanks,
Przemyslaw
2019-05-29 Przemyslaw Wirkus
* config/arm/iterators.md (VABAL): New int iterator.
* config/arm/neon.md (sadv16qi):
d18, d19
vpadd.i32 d18, d18, d18
vmov.32 r0, d18[0]
Bootstrapped and tested on arm-none-linux-gnueabihf.
Ok for trunk?
Thanks,
Przemyslaw
2019-06-06 Przemyslaw Wirkus
* config/arm/iterators.md (VABAL): New int iterator.
* config/arm/neon.md (sadv16qi):
> What is that backslash in \> doing in the ChangeLog entries?
> Jakub
My bad, tool I use for code review crafted in backslash when it wrongly assumed
I want a markdown. An early sign that machines want to take over, I guess...
I promise I will be more diligent next time.
kind regards
-05-13 Przemyslaw Wirkus
* internal-fn.def (SIGNBIT): New.
* config/aarch64/aarch64-simd.md (signbitv2sf2): New expand
defined.
(signbitv4sf2): Likewise.
gcc/testsuite/ChangeLog:
2019-05-13 Przemyslaw Wirkus
* gcc.target/aarch64/signbitv4sf.c: New test
Hi Richard,
New patch adds a new IFN_SIGNBIT internal function that maps
to signbit_optab.
gcc/ChangeLog:
2019-05-05 Przemyslaw Wirkus
* gcc/internal-fn.def (SIGNBIT): New.
* gcc/config/aarch64/aarch64-simd.md (signbitv4sf2): New expand
defined.
gcc/testsuite
// 19 [c=4 l=4] condjump
ret // 49 [c=0 l=4] *do_return
Thanks,
Przemyslaw
gcc/ChangeLog:
2019-03-20 Przemyslaw Wirkus
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Added CASE_CFN_SIGNBIT.
* config/aarch64
On 21/11/17 15:27 +, Jonathan Wakely wrote:
>>OK for trunk?
>OK, thanks.
I don't have privileges to commit. Could you please commit it on my behalf?
docs with 'make doc-pdf-docbook'.
OK for trunk?
Kind regards,
Przemyslaw Wirkus
libstdc++-v3/ChangeLog:
2017-11-08 Przemyslaw Wirkus <przemyslaw.wir...@arm.com>
* doc/xml/manual/using.xml (manual.intro.using.macros): Move
variablelist element at the end of its list.
diff
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