Re: [PATCH] xtensa: Optimize branch whether (reg:SI) is within/out the range handled by CLAMPS instruction

lve several issues including this.) > > gcc/ChangeLog: > > * config/xtensa/predicates.md (alt_ubranch_operator): > New predicate. > * config/xtensa/xtensa.md (*eqne_in_range): > New insn_and_split pattern. > --- > gcc/config/xtensa/predicates.md | 3 +++ > gcc/config/xtensa/xtensa.md | 36 + > 2 files changed, 39 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH v3] xtensa: Rewrite bswapsi2_internal with compact syntax

++ > 4 files changed, 126 insertions(+), 29 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/xtensa/bswap-SSAI8.c Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Rewrite bswapsi2_internal with compact syntax

-Wno-scalar-storage-order -O3 -finline-functions output pattern test +FAIL: gcc.dg/sso/t3.c -Wno-scalar-storage-order -O2 output pattern test +FAIL: gcc.dg/sso/t3.c -Wno-scalar-storage-order -O3 -finline-functions output pattern test -- Thanks. -- Max

Re: [PATCH 3/3] xtensa: Make use of compact insn definition syntax for insns whose have multiple alternatives

in compact syntax. > --- > gcc/config/xtensa/xtensa.md | 325 +--- > 1 file changed, 151 insertions(+), 174 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed the whole series to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Small improvement to "*btrue_INT_MIN"

; > gcc/ChangeLog: > > * config/xtensa/xtensa.md (*btrue_INT_MIN): > Change the branch insn condition to test for a negative number > rather than testing for the MSB. > --- > gcc/config/xtensa/xtensa.md | 17 +++-- > 1 file changed, 7 insertions(+), 10 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Refine constraint "T" to define_special_memory_constraint

ensa/constraints.md (T): > Change define_memory_constraint to define_special_memory_constraint. > --- > gcc/config/xtensa/constraints.md | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Fix remaining inaccuracies in xtensa_is_insn_L32R_p()

gt; instructions wherever possible, and add comments that help understand > the intent of the process. > --- > gcc/config/xtensa/xtensa.cc | 46 - > 1 file changed, 35 insertions(+), 11 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: Fix inaccuracy in xtensa_rtx_costs()

n a0, sp, 12 addisp, sp, 16 ret.n which may be expected with -O2 and -O3 that enable -fstrict-aliasing. Committed to master. -- Thanks. -- Max

Re: [PATCH v2] xtensa: Fix B[GE/LT]UI instructions with immediate values of 32768 or 65536 not being emitted

s(+), 12 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/xtensa/BGEUI-BLTUI-32k-64k.c Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

[COMMITTED] xtensa: Remove TARGET_PROMOTE_PROTOTYPES

From: "H.J. Lu" xtensa ABI requires sign extension of signed 8/16-bit arguments to 32 bits and zero extension of unsigned 8/16-bit arguments to 32 bits. TARGET_PROMOTE_PROTOTYPES is an optimization, not an ABI requirement. Remove TARGET_PROMOTE_PROTOTYPES and define xtensa_promote_function_mode t

Re: [PATCH] xtensa: Remove TARGET_PROMOTE_FUNCTION_MODE

On Sat, Jun 21, 2025 at 3:54 PM H.J. Lu wrote: > On Sun, Jun 22, 2025 at 6:35 AM Max Filippov wrote: > > On Sat, Jun 21, 2025 at 2:41 PM Max Filippov wrote: > > > On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa > > > wrote: > > >

Re: [PATCH] xtensa: Implement TARGET_ZERO_CALL_USED_REGS

e changed, 56 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Remove TARGET_PROMOTE_FUNCTION_MODE

On Sun, Jun 22, 2025 at 5:49 AM Takayuki 'January June' Suwa wrote: > > On 2025/06/22 6:41, Max Filippov wrote: > > On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa > > wrote: > >> > >> That hook has since been deprecated > &

Re: [PATCH] xtensa: Make use of DEPBITS instruction

c, no new regressions. I don't have a working config with DEPBITS option, just checked that it doesn't break anything for other configs. Committed to master without the include/xtensa-config.h part. -- Thanks. -- Max

Re: [PATCH] xtensa: Remove TARGET_PROMOTE_FUNCTION_MODE

On Sat, Jun 21, 2025 at 2:41 PM Max Filippov wrote: > > On Sat, Jun 21, 2025 at 2:12 PM Takayuki 'January June' Suwa > wrote: > > > > That hook has since been deprecated > > (commit a670ebde3995481225ec62b29686ec07a21e5c10) and has led to incorrect > >

Re: [PATCH] xtensa: Remove TARGET_PROMOTE_FUNCTION_MODE

*, int, bool, bool) gcc/expr.cc:6645 0xe8b7df expand_assignment(tree_node*, tree_node*, bool) gcc/expr.cc:6483 0xd50e9d expand_call_stmt gcc/cfgexpand.cc:3149 0xd50e9d expand_gimple_stmt_1 gcc/cfgexpand.cc:4223 0xd50e9d expand_gimple_stmt gcc/cfgexpand.cc:4370 0xd51b95 expand_gimple_basic_block gcc/cfgexpand.cc:6433 0xd53d26 execute gcc/cfgexpand.cc:7181 -- Thanks. -- Max

Re: [PATCH] xtensa: Revert "xtensa: Eliminate unwanted reg-reg moves during DFmode input reloads"

le2 pattern that was previously added. > --- > gcc/config/xtensa/predicates.md | 13 - > gcc/config/xtensa/xtensa.md | 30 -- > 2 files changed, 43 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Revert "xtensa: Eliminate unnecessary general-purpose reg-reg moves"

arget/xtensa/elim_GP_regmove_1.c | 10 > 3 files changed, 79 deletions(-) > delete mode 100644 gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_0.c > delete mode 100644 gcc/testsuite/gcc.target/xtensa/elim_GP_regmove_1.c Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Implement l(ceil|floor)sfsi2 insn patterns and their scaled variants

statements. > (lsfsi2, *lsfsi2_2x, *lsfsi2_scaled): > New insn patterns. > --- > gcc/config/xtensa/xtensa.cc | 16 ++++ > gcc/config/xtensa/xtensa.md | 50 - > 2 files changed, 54 insertions(+), 12 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Implement l(ceil|floor|round|)sfsi2 insn patterns and their scaled variants

On Thu, Jun 5, 2025 at 7:20 PM Takayuki 'January June' Suwa wrote: > > On 2025/06/06 8:55, Max Filippov wrote: > > > On Thu, Jun 05, 2025 at 09:19:19PM +0900, Takayuki 'January June' Suwa > > wrote: > >> On 2025/06/05 5:09, Max Filippov wr

Re: [PATCH] xtensa: Implement l(ceil|floor|round|)sfsi2 insn patterns and their scaled variants

On Thu, Jun 05, 2025 at 09:19:19PM +0900, Takayuki 'January June' Suwa wrote: > On 2025/06/05 5:09, Max Filippov wrote: > > On Tue, Jun 3, 2025 at 7:44 AM Takayuki 'January June' Suwa > > wrote: > > > > > > By using the previously unused

Re: [PATCH] xtensa: Implement l(ceil|floor|round|)sfsi2 insn patterns and their scaled variants

ointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test +FAIL: gfortran.dg/out_of_range_2.f90 -O3 -g execution test +FAIL: gfortran.dg/out_of_range_2.f90 -Os execution test At first glance they may be related to the rounding mode settings, let me take a closer look. -- Thanks. -- Max

Re: [PATCH 3/3] xtensa: Remove include of reload.h

| 1 - > 1 file changed, 1 deletion(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed the whole series to master with minor fixups in descriptions. -- Thanks. -- Max

[COMMITTED] testsuite: xtensa: add support for effective_target_sync_*

Add new function check_effective_target_xtensa_atomic and use it in the check_effective_target_sync_int_long and check_effective_target_sync_char_short. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_xtensa_atomic): New function. (check_effectiv

Re: [PATCH v3] xtensa: Fix up unwanted spills of SFmode hard registers holding function arguments/returns

retw.n > > gcc/ChangeLog: > > * config/xtensa/xtensa.cc (xtensa_register_move_cost): > Add appropriate move costs between AR_REGS and FP_REGS. > --- > gcc/config/xtensa/xtensa.cc | 28 +++++++- > 1 file changed, 19 insertions(+), 9 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. That's a nice fix, thank you Suwa-san! -- Thanks. -- Max

Re: [PATCH v2 3/3] xtensa: Make large const_int legitimate during RTL instruction combination pass

7b lra(_IO_FILE*, int) /home/jcmvbkbc/ws/tensilica/gcc/gcc/gcc/lra.cc:2636 0xbdbe77 do_reload /home/jcmvbkbc/ws/tensilica/gcc/gcc/gcc/ira.cc:5987 0xbdbe77 execute /home/jcmvbkbc/ws/tensilica/gcc/gcc/gcc/ira.cc:6175 -- Thanks. -- Max

Re: [PATCH v2] xtensa: Fix the issue in "*extzvsi-1bit_addsubx"

allocated registers that satisfy the above constraints. > --- > gcc/config/xtensa/xtensa.md | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH] xtensa: Define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P target hook

nsa.cc | 3 +++ > gcc/config/xtensa/xtensa.md | 12 ++-- > 2 files changed, 9 insertions(+), 6 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST

d a case statement for TYPE_FARITH. Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Fix suboptimal loading of pooled constant value into hardware single-precision FP register

rder alternative that corresponds to L32R machine instruction, > and prefix alternatives that correspond to LSI/SSI instructions > with the constraint character '^' so that they are disparaged by > reload/LRA. Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH] xtensa: Fix the regression introduce by abe81aa19f250516fd57f76cad9c0920cce221bc

A0_REG)' after calling > xtensa_expand_epilogue. > --- > gcc/config/xtensa/xtensa-protos.h | 2 +- > gcc/config/xtensa/xtensa.cc | 10 +- > gcc/config/xtensa/xtensa.md | 9 + > 3 files changed, 7 insertions(+), 14 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH v2 1/3] xtensa: Resurrect LEAF_REGISTERS and LEAF_REG_REMAP

> +extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; > +#define LEAF_REGISTERS xtensa_leaf_regs > + > +/* For Xtensa, no remapping is necessary, but this macro must be > + defined if LEAF_REGISTERS is defined. */ > +#define LEAF_REG_REMAP(REGNO) ((int) (REGNO)) > + > /* Internal macros to classify a register number. */ > > /* 16 address registers + fake registers */ > -- > 2.39.2 -- Thanks. -- Max

Re: [PATCH 3/3] xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions

(floatsisf2): Change from "floatsisf2". > (*floatsisf2_scaled): New insn definition. > --- > gcc/config/xtensa/predicates.md | 20 > gcc/config/xtensa/xtensa.md | 58 ++--- > 2 files changed, 66 insertions(+), 12 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

Re: [PATCH v2 2/3] xtensa: Make use of std::swap where appropriate

tensa-linux-uclibc, no new regressions. Committed to master -- Thanks. -- Max

[COMMITTED] gcc: xtensa: disable late-combine by default

gcc/ * config/xtensa/xtensa.cc (xtensa_option_override_after_change): New function. (TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define as xtensa_option_override_after_change. (xtensa_option_override): Call xtensa_option_override_after_change. --- gcc/con

Re: [RFC 1/2] libbacktrace: add FDPIC support

On Mon, Jul 15, 2024 at 10:21:18AM -0700, Ian Lance Taylor wrote: > Can you see whether this patch works for FDPIC support? This is based > on your patch but has various changes. Thanks. Yes, it is working. -- Thanks. -- Max

Re: [RFC 1/2] libbacktrace: add FDPIC support

On Wed, Jul 10, 2024 at 12:49 PM Ian Lance Taylor wrote: > On Sun, May 26, 2024 at 11:51 PM Max Filippov wrote: > > diff --git a/libbacktrace/internal.h b/libbacktrace/internal.h > > index 4fa0af8cb6c9..456911166026 100644 > > --- a/libbacktrace/internal.h > > ++

Re: [PATCH] xtensa: Eliminate double MEMW insertions for volatile memory

Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH v2] xtensa: constantsynth: Reforge to fix some non-fatal issues

s mentioned above, > and add new patterns for when TARGET_AUTO_LITPOOLS is enabled. > --- > gcc/config/xtensa/xtensa-protos.h | 2 +- > gcc/config/xtensa/xtensa.cc | 75 --- > gcc/config/xtensa/xtensa.md | 56 ++- > 3 files changed, 103 insertions(+), 30 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: constantsynth: Reforge to fix some non-fatal issues

./gt-ipa-prop.h:39 0xc99b58 gt_ggc_mx(ipa_return_value_summary*&) ./gt-ipa-prop.h:62 -- Thanks. -- Max

Re: [RFC 1/2] libbacktrace: add FDPIC support

On Sun, May 26, 2024 at 11:50 PM Max Filippov wrote: > > Instead of a single base address FDPIC ELF files use load map: a > structure with an array of mappings for individual segments. Change > libbacktrace functions and structures to support that. Ping? > libbacktrace/

Re: [PATCH 2/2] xtensa: Prepend "(use A0_REG)" to sibling call CALL_INSN_FUNCTION_USAGE instead of emitting it as insn at the end of epilogue

.h | 4 ++-- > gcc/config/xtensa/xtensa.cc | 16 ++-- > gcc/config/xtensa/xtensa.md | 13 +++-- > 3 files changed, 19 insertions(+), 14 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Simplify several MD templates

(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. Suwa-san, something has changed in your mail setup apparently: every patch context line now gets an extra space in the beginning. Could you please fix that? -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: Use epilogue_completed rather than cfun->machine->epilogue_done

h | 1 - > gcc/config/xtensa/xtensa.cc | 14 -- > gcc/config/xtensa/xtensa.md | 5 - > 3 files changed, 4 insertions(+), 16 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Use REG_P(), MEM_P(), etc. instead of comparing GET_CODE()

ig/xtensa/xtensa.md | 4 +- > 3 files changed, 51 insertions(+), 53 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. For some reason neither git am nor patch -p1 could apply this patch, so I did that manually. -- Thanks. -- Max

Re: [RFC 0/2] libbacktrace: add FDPIC support

See PR libstdc++/111641 for details. There's a patch in > there, too. Oh, cool, thanks for the pointer Rainer. So patch 2 of this series can be disregarded. -- Thanks. -- Max

[RFC 0/2] libbacktrace: add FDPIC support

bc. Adding -funwind-tables to the libstdc++ version of libbacktrace fixed that. Which makes me wonder how it works for other architectures? Max Filippov (2): libbacktrace: add FDPIC support libstdc++-v3/src/libbacktrace: add -funwind-tables libbacktrace/dwarf.c

[RFC 1/2] libbacktrace: add FDPIC support

Instead of a single base address FDPIC ELF files use load map: a structure with an array of mappings for individual segments. Change libbacktrace functions and structures to support that. libbacktrace/ PR libbacktrace/114941 * dwarf.c: Include or if available. (struct d

[RFC 2/2] libstdc++-v3/src/libbacktrace: add -funwind-tables

libstdc++-v3/ * src/libbacktrace/Makefile.am (AM_CFLAGS, AM_CXXFLAGS): Add -funwind-tables * src/libbacktrace/Makefile.in: Regenerate. --- libstdc++-v3/src/libbacktrace/Makefile.am | 4 ++-- libstdc++-v3/src/libbacktrace/Makefile.in | 4 ++-- 2 files changed, 4 insertions(

Re: [PATCH] libgcc: arm: fix build for FDPIC target

On Fri, Mar 22, 2024 at 1:15 PM Max Filippov wrote: > > libgcc/ > * unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast > last argument of _Unwind_VRS_Set to void *. > --- > libgcc/unwind-arm-common.inc | 2 +- > 1 file changed, 1 insertion(+),

Re: [PATCH] xtensa: Add supplementary split pattern for "*addsubx"

, so it is easy to solve by defining that pattern. > > gcc/ChangeLog: > > * config/xtensa/xtensa.md: Add new split pattern described above. > --- > gcc/config/xtensa/xtensa.md | 14 ++ > 1 file changed, 14 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

[PATCH] libgcc: arm: fix build for FDPIC target

libgcc/ * unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast last argument of _Unwind_VRS_Set to void *. --- libgcc/unwind-arm-common.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libgcc/unwind-arm-common.inc b/libgcc/unwind-arm-common.inc inde

[PATCH] gcc: xtensa: reorder movsi_internal patterns for better code generation during LRA

After switching to LRA xtensa backend generates the following code for saving/loading registers: movi a9, 0x190 add a9, a9, sp s32i.n a3, a9, 0 instead of the shorter and more efficient s32i a3, a9, 0x190 E.g. the following code can be used to reproduce it: i

Re: [PATCH 2/2] xtensa: Fix missing mode warning in "*eqne_zero_masked_bits"

1 file changed, 1 insertion(+), 1 deletion(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2 v2] xtensa: Recover constant synthesis for HImode after LRA transition

gcc/config/xtensa/xtensa.md | 22 ++ > 1 file changed, 14 insertions(+), 8 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Recover constant synthesis for HImode after LRA transition

812 0x1c08b57 decompose_multiword_subregs /home/jcmvbkbc/ws/tensilica/gcc/gcc/gcc/lower-subreg.cc:1569 0x1c09d7d execute /home/jcmvbkbc/ws/tensilica/gcc/gcc/gcc/lower-subreg.cc:1834 -- Thanks. -- Max

[COMMITTED] xtensa: Make full transition to LRA

From: Takayuki 'January June' Suwa gcc/ChangeLog: * config/xtensa/constraints.md (R, T, U): Change define_constraint to define_memory_constraint. * config/xtensa/predicates.md (move_operand): Don't check that a constant pool operand size is a multiple of UNITS_PER

[PATCH v2] xtensa: Make full transition to LRA

From: Takayuki 'January June' Suwa gcc/ChangeLog: * config/xtensa/constraints.md (R, T, U): Change define_constraint to define_memory_constraint. * config/xtensa/predicates.md (move_operand): Don't check that a constant pool operand size is a multiple of UNITS_PER

Re: [PATCH] xtensa: Make full transition to LRA

Hi Suwa-san, I've finally processed the new issues introduced by this change. On Wed, May 10, 2023 at 2:10 AM Max Filippov wrote: > On Mon, May 8, 2023 at 6:38 AM Takayuki 'January June' Suwa > wrote: > > > > gcc/ChangeLog: > > > >

[COMMITTED] gcc: xtensa: fix salt/saltu version check

gcc/ * config/xtensa/xtensa.h (TARGET_SALT): Change HW version from 26 (which corresponds to RF-2014.0) to 27 (which corresponds to RG-2015.0, the release where salt/saltu opcodes were introduced). --- gcc/config/xtensa/xtensa.h | 2 +- 1 file changed, 1 ins

[COMMITTED] gcc: xtensa: use salt/saltu in xtensa_expand_scc

gcc/ * config/xtensa/predicates.md (xtensa_cstoresi_operator): Add unsigned comparisons. * config/xtensa/xtensa.cc (xtensa_expand_scc): Add code generation of salt/saltu instructions. * config/xtensa/xtensa.h (TARGET_SALT): New macro. * config/xtensa/

Re: [PATCH] xtensa: Optimize several boolean evaluations of EQ/NE against constant zero

registers. > * config/xtensa/xtensa.md (*eqne_INT_MIN): Ditto. > (eq_zero_NSA, eqne_zero, *eqne_zero_masked_bits): New patterns. > --- > gcc/config/xtensa/xtensa.cc | 35 +-- > gcc/config/xtensa/xtensa.md | 112 > 2 files changed, 113 insertions(+), 34 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

[RFC] gcc: xtensa: use salt/saltu in xtensa_expand_scc

gcc/ * config/xtensa/predicates.md (xtensa_cstoresi_operator): Add unsigned comparisons. * config/xtensa/xtensa.cc (xtensa_expand_scc): Add code generation of salt/saltu instructions. * config/xtensa/xtensa.h (TARGET_SALT): New macro. * gcc/config/xte

Re: [PATCH] xtensa: Optimize boolean evaluation when SImode EQ/NE to zero if TARGET_MINMAX

a.cc | 43 +++-- > gcc/config/xtensa/xtensa.md | 34 ----- > 2 files changed, 37 insertions(+), 40 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Optimize boolean evaluation when SImode EQ/NE to zero if TARGET_MINMAX

On Tue, Sep 5, 2023 at 9:24 PM Takayuki 'January June' Suwa wrote: > On 2023/09/06 8:01, Max Filippov wrote: > > On Tue, Sep 5, 2023 at 2:29 AM Takayuki 'January June' Suwa > > wrote: > >> ;; after (prereq. TARGET_MINMAX) > >> test0: &

Re: [PATCH] xtensa: Optimize boolean evaluation when SImode EQ/NE to zero if TARGET_MINMAX

minua2, a2, a9 > ret.n ISTM that test1 could be done with movnez in the same two instructions: movi a9, 1 movnez a2, a9, a2 -- Thanks. -- Max

Re: [PATCH 2/3] gcc: xtensa: use dynconfig settings as builtin-macros

als. -- Thanks. -- Max

Re: [PATCH 2/3] gcc: xtensa: use dynconfig settings as builtin-macros

On Thu, Jul 20, 2023 at 10:45 AM Alexey Lapshin wrote: > > On Thu, 2023-07-20 at 08:25 -0700, Max Filippov wrote: > > But it defines them with their respective values. > > Just notice that it adds two leading underscores in front of the names. > > Why builtin macros

Re: [PATCH 2/3] gcc: xtensa: use dynconfig settings as builtin-macros

ts for keeping backwards compatibility with the overlay-based configuration method (: I did the same for the uClibc, but the change is still in my queue: https://github.com/jcmvbkbc/uclibc-ng-xtensa/commit/842aede0537812a0d2158433c5e048ee87324075 -- Thanks. -- Max

Re: [PATCH 2/3] gcc: xtensa: use dynconfig settings as builtin-macros

ctive values. Just notice that it adds two leading underscores in front of the names. > But the value must be set to make it work correctly. > It uses builtin_define() instead builtin_define_with_int_value() > > I will check how it could be soved with the loop approach. -- Thanks. -- Max

Re: [PATCH 2/3] gcc: xtensa: use dynconfig settings as builtin-macros

gt; +XTENSA_CPU_CPP_BUILTIN(XTENSA_MARCH_EARLIEST); > \ > +XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_CLAMPS); > \ > +XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_DEPBITS); > \ > +XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_EXCLUSIVE); > \ > +XTENSA_CPU_CPP_BUILTIN(XCHAL_HAVE_XEA3); > \ >} while (0) > > #define CPP_SPEC " %(subtarget_cpp_spec) " > -- > 2.34.1 > -- Thanks. -- Max

Re: [PATCH] xtensa: Use HARD_REG_SET instead of bare integer

clibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Fix missing mode warning in "*eqne_INT_MIN"

ed, 1 insertion(+), 1 deletion(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: The use of CLAMPS instruction also requires TARGET_MINMAX, as well as TARGET_CLAMPS

inux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: constantsynth: Add new 2-insns synthesis pattern

a_constantsynth_2insn): > Add new pattern for the abovementioned case. > --- > gcc/config/xtensa/xtensa.cc | 12 ++-- > 1 file changed, 10 insertions(+), 2 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/2] xtensa: Remove TARGET_MEMORY_MOVE_COST hook

nsa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode

On Mon, Jun 5, 2023 at 8:15 AM Max Filippov wrote: > > Hi Suwa-san, > > On Mon, Jun 5, 2023 at 2:37 AM Takayuki 'January June' Suwa > wrote: > > > > This patch optimizes the boolean evaluation of EQ/NE against zero > > by adding two insn_and_split patte

Re: [PATCH v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode

fig/xtensa/xtensa.md | 53 + > 3 files changed, 106 insertions(+), 9 deletions(-) This version performs much better than v1, but there's still new testsuite failure in the gcc.c-torture/execute/bitfld-3.c and the following change in the generated code from: l32i.n a11, a7, 8 l8uia9, a7, 12 movia10, 0xff add.n a9, a9, a10 addi.n a7, a11, -1 movi.n a10, 1 movi.n a6, 0 moveqz a10, a6, a11 to: l32i.n a10, a7, 8 l8uia9, a7, 12 movia11, 0xff add.n a9, a9, a11 addi.n a7, a10, -1 movi.n a11, 1 mov.n a10, a11 movnez a10, a11, a11 suggests that the pattern movsicc_ne0_reg_zero does not work correctly when its operands overlap. -- Thanks. -- Max

Re: [PATCH] xtensa: Optimize boolean evaluation or branching when EQ/NE to INT_MIN

IN, *eqne_INT_MIN): > New insn_and_split patterns. > --- > gcc/config/xtensa/xtensa.md | 64 + > 1 file changed, 64 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode

rtran build, all with the similar diagnostic: gcc/libgfortran/intrinsics/erfc_scaled_inc.c:179:1: error: unrecognizable insn: 179 | } | ^ (insn 23 22 24 2 (set (reg:CC 18 b0) (lt:CC (const_double:SF 0.0 [0x0.0p+0]) (reg/v:SF 96 [ x ]))) "gcc/libgfortran/intrinsics/erfc_scaled_inc.c":111:18 -1 (nil)) during RTL pass: vregs -- Thanks. -- Max

Re: [PATCH 2/3 v3] xtensa: Add 'adddi3' and 'subdi3' insn patterns

rtx_code_label *label; > + if (rtx_equal_p (operands[0], operands[1]) > + || rtx_equal_p (operands[0], operands[2]) > + || ! REG_P (operands[1]) || ! REG_P (operands[2])) I wonder if these additional conditions are necessary, given that the operands have the "register_operand" predicates? -- Thanks. -- Max

Re: [PATCH 2/3 v3] xtensa: Add 'adddi3' and 'subdi3' insn patterns

struc- > tion idioms described in the Xtensa ISA reference manual (p. 600). > --- > gcc/config/xtensa/xtensa.md | 52 + > 1 file changed, 52 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/3] xtensa: Improve "*shlrd_reg" insn pattern and its variant

swapped. > In addition, replace use of code iterator with new operator > predicate. > (*shlrd_const, *shlrd_per_byte): > Likewise regarding the code iterator. > --- > gcc/config/xtensa/predicates.md | 3 ++ > gcc/config/xtensa/xtensa.md | 81 ++++++--- > 2 files changed, 58 insertions(+), 26 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. I can also confirm that the pattern is now used as expected in the case where I previously had an issue. Thanks for fixing that! Committed to master. -- Thanks. -- Max

Re: [PATCH 2/3 v2] xtensa: Add 'adddi3' and 'subdi3' insn patterns

o_op1)); > + emit_insn (gen_subsi3 (hi_dest, hi_op0, hi_op1)); > + emit_cmp_and_jump_insns (lo_op0, lo_op1, GEU, const0_rtx, > + SImode, true, label = gen_label_rtx ()); > + emit_insn (gen_addsi3 (hi_dest, hi_dest, constm1_rtx)); > + emit_label (label); > + DONE; > +}) > + > (define_insn "subsf3" >[(set (match_operand:SF 0 "register_operand" "=f") > (minus:SF (match_operand:SF 1 "register_operand" "f") > -- > 2.30.2 -- Thanks. -- Max

Re: [PATCH 3/3 v2] xtensa: Optimize 'cstoresi4' insn pattern

/20070623-1.c) when an overflow occurs, e.g. for op0 == INT_MIN, op1 == INT_MAX. Maybe the dedicated instructions salt / saltu could be used in that pattern? They don't have their own XCHAL_* macros, but according to the ISA book they were introduced in RG-2015.0, which I believe could be tested as follows: #define TARGET_SALT (XTENSA_MARCH_EARLIEST >= 27) -- Thanks. -- Max

Re: [PATCH 3/3] xtensa: Rework 'setmemsi' insn pattern

/config/xtensa/xtensa.md | 4 +- > 3 files changed, 172 insertions(+), 154 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 2/3] xtensa: Add 'subtraction from constant' insn pattern

ion. > * config/xtensa/xtensa.md (*subsi3_from_const): > New insn_and_split pattern. > --- > gcc/config/xtensa/constraints.md | 2 +- > gcc/config/xtensa/xtensa-protos.h | 1 + > gcc/config/xtensa/xtensa.cc | 7 +++ > gcc/config/xtensa/xtensa.md | 24 > 4 files changed, 33 insertions(+), 1 deletion(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH 1/3] xtensa: Addendum of the commit e33d2dcb463161a110ac345a451132ce8b2b23d9

sn attribute related to TARGET_DENSITY. > (*extzvsi-1bit_addsubx): Ditto. > --- > gcc/config/xtensa/xtensa.md | 11 ++- > 1 file changed, 6 insertions(+), 5 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master with a more readable subject line. -- Thanks. -- Max

Re: [PATCH 2/2] xtensa: Merge '*addx' and '*subx' insn patterns into one

ge to also accept '*subx' pattern. > (*subx): Remove. > --- > gcc/config/xtensa/xtensa.md | 31 +-- > 1 file changed, 13 insertions(+), 18 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

Re: [PATCH v2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0'

On Mon, May 22, 2023 at 10:48 PM Takayuki 'January June' Suwa wrote: > > On 2023/05/23 11:27, Max Filippov wrote: > > Hi Suwa-san, > > Hi! > > > This change introduces a bunch of test failures on big endian configuration. > > I believe that's becau

Re: [PATCH 1/2] xtensa: Optimize '(x & CST1_POW2) != 0 ? CST2_POW2 : 0'

at do not fit into signed 12 bits in the > patterns added above. > --- > gcc/config/xtensa/predicates.md | 3 ++ > gcc/config/xtensa/xtensa.cc | 3 +- > gcc/config/xtensa/xtensa.md | 75 + > 3 files changed, 80 insertions(+), 1 deletion(-) This change introduces a bunch of test failures on big endian configuration. I believe that's because the starting bit position for zero_extract is counted from different ends depending on the endianness. -- Thanks. -- Max

Re: [PATCH] xtensa: Make full transition to LRA

xecution test +FAIL: gcc.dg/torture/pr97812.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test +FAIL: gcc.dg/torture/pr97812.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects execution test +FAIL: gcc.dg/tree-ssa/pr84969.c execution test and some more in the gfortran testsuite. -- Thanks. -- Max

[COMMITTED 2/2] gcc: xtensa: add -m[no-]strict-align option

gcc/ * config/xtensa/xtensa-opts.h: New header. * config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as xtensa_strict_align. * config/xtensa/xtensa.cc (xtensa_option_override): When -m[no-]strict-align is not specified in the command line set xtensa_

[COMMITTED 1/2] gcc: xtensa: add data alignment properties to dynconfig

gcc/ * config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New function. include/ * xtensa-dynconfig.h (xtensa_config_v4): New struct. (XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION) (XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)

Re: [PATCH] xtensa: Fix for enabling LRA

IL: c-c++-common/torture/builtin-arith-overflow-p-14.c -O2 execution test +FAIL: c-c++-common/torture/builtin-arith-overflow-p-14.c -O2 -flto -fno-use-linker-plugin -flto-partition=none execution test +FAIL: c-c++-common/torture/builtin-shufflevector-1.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects execution test -- Thanks. -- Max

[COMMITTED] xtensa: add .note.GNU-stack section on linux

gcc/ * config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro. libgcc/ * config/xtensa/crti.S: Add .note.GNU-stack section on linux. * config/xtensa/crtn.S: Likewise. * config/xtensa/lib1funcs.S: Likewise. * config/xtensa/lib2funcs.S: Likewise. --- gcc/conf

Re: [PATCH] xtensa: Remove REG_OK_STRICT and its derivatives

G_OK_STRICT, REG_OK_FOR_INDEX_P, > REG_OK_FOR_BASE_P): Remove. > --- > gcc/config/xtensa/xtensa.h | 11 +-- > 1 file changed, 1 insertion(+), 10 deletions(-) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

[PATCH 1/2] gcc: xtensa: add data alignment properties to dynconfig

gcc/ * config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New function. include/ * xtensa-dynconfig.h (xtensa_config_v4): New struct. (XCHAL_DATA_WIDTH, XCHAL_UNALIGNED_LOAD_EXCEPTION) (XCHAL_UNALIGNED_STORE_EXCEPTION, XCHAL_UNALIGNED_LOAD_HW)

[PATCH 2/2] gcc: xtensa: adjust STRICT_ALIGNMENT per hardware capabilities

gcc/ * config/xtensa/xtensa.h (STRICT_ALIGNMENT): Make it 0 when the hardware supports both unaligned loads and stores. --- gcc/config/xtensa/xtensa.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index

Re: [PATCH] xtensa: Make use of CLAMPS instruction if configured

sa/xtensa-protos.h | 1 + > gcc/config/xtensa/xtensa.cc | 13 +++ > gcc/config/xtensa/xtensa.h| 1 + > gcc/config/xtensa/xtensa.md | 37 +++ > 4 files changed, 52 insertions(+) Regtested for target=xtensa-linux-uclibc, no new regressions. Committed to master. -- Thanks. -- Max

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