Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

> I did a test run without the subreg condition and it also appears to > work when running on rv32gcv and rv64gcv newlib. Would it be better > to remove the subreg? Yep, if it works, i.e. all tests still pass then let's get rid of it. Regards Robin

Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

Hi Robin, I did a test run without the subreg condition and it also appears to work when running on rv32gcv and rv64gcv newlib. Would it be better to remove the subreg? Edwin On 6/12/2024 12:42 AM, Robin Dapp wrote: Hi Edwin, this is OK but did you check if we can get rid of the subreg con

Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

Hi Edwin, this is OK but did you check if we can get rid of the subreg condition now that we have gen_lowpart? Regards Robin

[PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets

On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in maybe_legitimize_instruction when zero extending a uint32 to uint64 due to a mismatch between the input operand's mode (DI) and the expanded insn operand's mode (Pmode == SI). Ensure that mode of the operands match gcc/ChangeLog: