Hi Kyrill,
On 2018/6/6 22:51, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 01/06/18 10:56, Zhangshaokun wrote:
>> Hi Ramana,
>>
>> Sorry to reply so later because of short leave.
>>
>> On 2018/5/23 18:41, Ramana Radhakrishnan wrote:
>>>
>>> On 23/05/2018 03:50, Zhangshaokun wrote:
Hi Ramana,
>
Hi Shaokun,
On 01/06/18 10:56, Zhangshaokun wrote:
Hi Ramana,
Sorry to reply so later because of short leave.
On 2018/5/23 18:41, Ramana Radhakrishnan wrote:
On 23/05/2018 03:50, Zhangshaokun wrote:
Hi Ramana,
On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
On Tue, May 22, 2018 at 9:40 AM
Hi Ramana,
Sorry to reply so later because of short leave.
On 2018/5/23 18:41, Ramana Radhakrishnan wrote:
>
>
> On 23/05/2018 03:50, Zhangshaokun wrote:
>> Hi Ramana,
>>
>> On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
>>> On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
>>> wrote:
tsv11
On 23/05/2018 03:50, Zhangshaokun wrote:
Hi Ramana,
On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
wrote:
tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
L1 Icache which can access L1 Dcache.
Therefore, DC CVAU is not nec
Hi Kyrill,
On 2018/5/23 16:08, Kyrill Tkachov wrote:
>
> On 23/05/18 05:54, Zhangshaokun wrote:
>> Hi Kyrill,
>>
>> On 2018/5/22 18:52, Kyrill Tkachov wrote:
>>> Hi Shaokun,
>>>
>>> On 22/05/18 09:40, Shaokun Zhang wrote:
This patch adds HiSilicon's an mcpu: tsv110.
---
gcc/
On 23/05/18 05:54, Zhangshaokun wrote:
Hi Kyrill,
On 2018/5/22 18:52, Kyrill Tkachov wrote:
Hi Shaokun,
On 22/05/18 09:40, Shaokun Zhang wrote:
This patch adds HiSilicon's an mcpu: tsv110.
---
gcc/ChangeLog| 9 +++
gcc/config/aarch64/aarch64-cores.def |
Hi Kyrill,
On 2018/5/22 18:52, Kyrill Tkachov wrote:
> Hi Shaokun,
>
> On 22/05/18 09:40, Shaokun Zhang wrote:
>> This patch adds HiSilicon's an mcpu: tsv110.
>>
>> ---
>> gcc/ChangeLog| 9 +++
>> gcc/config/aarch64/aarch64-cores.def | 5 ++
>> gcc/config/aar
Hi Ramana,
On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
> On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
> wrote:
>> tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
>> L1 Icache which can access L1 Dcache.
>> Therefore, DC CVAU is not necessary in __aarch64_sync_cache_ran
Hi Shaokun,
On 22/05/18 09:40, Shaokun Zhang wrote:
This patch adds HiSilicon's an mcpu: tsv110.
---
gcc/ChangeLog| 9 +++
gcc/config/aarch64/aarch64-cores.def | 5 ++
gcc/config/aarch64/aarch64-cost-tables.h | 103 +++
gcc/config
On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
wrote:
> tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
> L1 Icache which can access L1 Dcache.
> Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for
> tsv110, is there any good idea to skip DC CVAU operation f
This patch adds HiSilicon's an mcpu: tsv110.
---
gcc/ChangeLog| 9 +++
gcc/config/aarch64/aarch64-cores.def | 5 ++
gcc/config/aarch64/aarch64-cost-tables.h | 103 +++
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aar
tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
L1 Icache which can access L1 Dcache.
Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for
tsv110, is there any good idea to skip DC CVAU operation for tsv110.
Any thoughts and ideas are welcome.
Shaokun Zhang
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