Hi, I'm having trouble with the installation, but I don't know if this should
be posted hereI just downloaded the new version 20070221 of gEDA and I was
wondering how I can install it as root. I can't find anywhere on the site
where it limits the installation to just users, but when I try
Andy Peters wrote:
Does iverilog support SDF backannotation? The SDF has the delay
information.
Here are some information about that and a link to a previous discussion:
http://iverilog.wikia.com/wiki/Graffiti#SDF_support
Cheers,
Guenter
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On Sun, 18 Mar 2007, Jason Elder wrote:
Hi, I'm having trouble with the installation, but I don't know if
this should be posted hereI just downloaded the new version
20070221 of gEDA and I was wondering how I can install it as root.
Do not install as root. If you install as root, and you
I am a beginner, and I have a lot of exposure to Eagle, so please
keep these limitations/biases in mind.
I would really like to see the following additions:
1. In gschem, when selecting a footprint, I would like to see the
footprint _and_ its description in a popup window. I should be
Do not install as root. If you install as root, and you need to
install system-wide dependencies, the installer becomes confused when
it tries to fire up an expect session as root.
Now I'm confused. In all these years of working on Unix, I've always
thought packages need to be installed as
This is almost a religious issue.
Aren't most questions which have many correct answers? :)
However, I personally recommend users to install into a new directory,
/usr/local/geda, and then set their $PATH variables to point to it...
Great. This is really I wanted to know. I wanted to know
I assume that's the reason for PCB, too.
No, pcb's plugins are very tightly coupled to the internal data
structures. The reason I added pcb's plugins was to let people define
their own actions without the cvs-build-merge issues, not as a generic
way to allow for future expansion.
You have
3. There should be native support for elongated vias (they
are called pads in Eagle) when defining an element.
The way to do this in pcb is to put a pin and a pad in the same place.
The pin gives you the drill hole, and the pad defines the elongated
copper shape.
I suspect that I am
On Mar 17, 2007, at 7:56 PM, CSB wrote:
Wow, thanks for the quick responses !
Does iverilog support SDF backannotation? The SDF has the delay
information.
Ah ! Now you mention it, I remember removing a $sdf_annotate line
from the generated verilog file. It was causing an error with vvp,
so
On Sat, Mar 17, 2007 14:01, DJ Delorie wrote:
If you edit the .pcb file and remove all the Rats[] entries (they're
all at the end) it will at least load. However, all the layer
information is missing, so you'll have to re-add all the layers and
redefine the layer groups.
Well, I guess the
go look in your /tmp directory for unintentional back ups
Mikael W. Bertelsen wrote:
On Sat, Mar 17, 2007 14:01, DJ Delorie wrote:
If you edit the .pcb file and remove all the Rats[] entries (they're
all at the end) it will at least load. However, all the layer
information is missing,
Wen wrote:
Hi list,
I am going to do Equivalent circuit fitting for a university project with
impedance spectroscopy.
I am looking for a tool that first allows to define (via a graphic interface would be best) an electric circuit made of resistors, conductors, inductors and maybe constant
On Sunday 18 March 2007 17:42, Wen wrote:
Hi list,
I am going to do Equivalent circuit fitting for a university
project with impedance spectroscopy.
I am looking for a tool that first allows to define (via a
graphic interface would be best) an electric circuit made of
resistors,
3. There should be native support for elongated vias (they
are called pads in Eagle) when defining an element.
The way to do this in pcb is to put a pin and a pad in the same place.
The pin gives you the drill hole, and the pad defines the elongated
copper shape.
Yes, I've tried this
You may want to try one of the many footprint scripts that are around.
Making the footprints in a batch using a script is a lot less error prone
than one by one in the GUI.
If you are looking for DIPs or SIP headers with rounded pads over pins
you could try my website.
Actually I've seen some
On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote:
If I take a look at the bright side, this incident did convinced me to
finish my backup script which takes an hourly snapshot. Backup is not
so bad after all.
Why don't you use some sort of version control instead? :)
On 3/18/07, C P Tarun [EMAIL PROTECTED] wrote:
You may want to try one of the many footprint scripts that are around.
Making the footprints in a batch using a script is a lot less error prone
than one by one in the GUI.
If you are looking for DIPs or SIP headers with rounded pads over pins
A script to place TO220 pads can be pretty simple (see below). The
poorly named routine element_add_pin_oval overlays a pin, a rounded pad
on the component side and a rounded pad on the solder side.
Very interesting. What's Pcb_8? Where do I find it? I'm looking through
your Website to see if
Very interesting. What's Pcb_8? Where do I find it? I'm looking through
your Website to see if there's some Perl module there.
Found Pcb_8 in your Perl library documentation. Thanks.
Tarun
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On Mar 18, 2007, at 8:06 PM, Igor2 wrote:
On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote:
If I take a look at the bright side, this incident did convinced
me to
finish my backup script which takes an hourly snapshot. Backup is not
so bad after all.
Why don't you use some sort of version
On Sun, 18 Mar 2007, Andy Peters wrote:
On Mar 18, 2007, at 8:06 PM, Igor2 wrote:
On Sun, 18 Mar 2007, Mikael W. Bertelsen wrote:
If I take a look at the bright side, this incident did convinced
me to
finish my backup script which takes an hourly snapshot. Backup is not
so bad after
A script to place TO220 pads can be pretty simple (see below). The
poorly named routine element_add_pin_oval overlays a pin, a rounded pad
on the component side and a rounded pad on the solder side.
I have been reading your (excellently-formatted reference-class) documentation
on your library.
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