On Wed, 2008-03-12 at 01:05 +, Peter Clifton wrote:
> On Tue, 2008-03-11 at 20:25 -0400, Ian Chapman wrote:
> > I was learning ghdl and going through an exercise and I generated the
> > adder.vhd file per instructiions. When I run gtkwave adder.vhd I get a
> > fast flash of what may be an int
On Tue, 2008-03-11 at 20:25 -0400, Ian Chapman wrote:
> I was learning ghdl and going through an exercise and I generated the
> adder.vhd file per instructiions. When I run gtkwave adder.vhd I get a
> fast flash of what may be an interesting screen and that's it. Did I
> miss something when I ins
I was learning ghdl and going through an exercise and I generated the
adder.vhd file per instructiions. When I run gtkwave adder.vhd I get a
fast flash of what may be an interesting screen and that's it. Did I
miss something when I installed gEDA tarball? Regards Ian.
In the terminal I get:-
G
> Dave the established practice with pcb is to make it difficult for
> friends to solder. If you don't believe me I still have an unattempted
> DJ's torture^h^h^h^h^h^h^h challenge kits;)
I've been thinking of making some smaller ones, maybe with CSPs this
time... mwahahaha!!
_
On Tue, 2008-03-11 at 11:14 -0800, Dave N6NZ wrote:
> So then I decided to do a through-hole board that would be easy for some
> friends to solder.
Dave the established practice with pcb is to make it difficult for
friends to solder. If you don't believe me I still have an unattempted
DJ's t
Ben Jackson wrote:
> On Tue, Mar 11, 2008 at 10:39:22AM -0800, Dave N6NZ wrote:
>> Ben Jackson wrote:
>>> You've always had to draw lines to pads to connect to any
>>> surface polygons.
>> Not being able to create non-round pins that support thermals is a
>> fundamental brokenness. Let's fix it
On Tue, Mar 11, 2008 at 10:39:22AM -0800, Dave N6NZ wrote:
>
> Ben Jackson wrote:
> > You've always had to draw lines to pads to connect to any
> > surface polygons.
>
> Not being able to create non-round pins that support thermals is a
> fundamental brokenness. Let's fix it.
Does that apply t
Ben Jackson wrote:
> You've always had to draw lines to pads to connect to any
> surface polygons.
Not being able to create non-round pins that support thermals is a
fundamental brokenness. Let's fix it.
-dave
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Ben Jackson wrote:
> On Tue, Mar 11, 2008 at 08:39:31AM -0800, Dave N6NZ wrote:
>> Steve Meier wrote:
>>> I am also interested in why you would want a thermal for connecting a
>>> via onto a pad in which the via is sitting.
>> ?? OK, I'm still under-caffeinated, but I don't parse your question.
>>
On Tue, Mar 11, 2008 at 08:39:31AM -0800, Dave N6NZ wrote:
> Steve Meier wrote:
> > I am also interested in why you would want a thermal for connecting a
> > via onto a pad in which the via is sitting.
>
> ?? OK, I'm still under-caffeinated, but I don't parse your question.
> I'm guessing you mis
Steve Meier wrote:
> I am also interested in why you would want a thermal for connecting a
> via onto a pad in which the via is sitting.
?? OK, I'm still under-caffeinated, but I don't parse your question.
I'm guessing you missed my initial rant? What I was trying to do is
create an oblong pi
I am also interested in why you would want a thermal for connecting a
via onto a pad in which the via is sitting.
I have used vias in pads twice now.
1) High density bga with a minimal number of layers. number of layers is
no longer an issue with pcb.
2) Conducting heat away from a component and
I haven't tried this but a work around might be to use a polygon rather
then a pad. If you need to solder to the polygon then make a small pad
not connected to the via and open the soldermask clearence but not the
polygon clearance.
Steve M
joe tarantino wrote:
>
>
> On Mon, Mar 10, 2008 at 5:16
joe tarantino wrote:
> - Expanding the grammar to support inner layer pad <> outer layer pad
> would be great. (Would one geometry definition apply to all inner layers?)
> - Also consider whatever would allow pins (and vias) with no connection
> to some layers (maybe supporting blind and buried
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