On Sat, Feb 07, 2009 at 08:11:09PM -0500, Ales Hvezda wrote:
Hi,
Recent good news/changes:
* The gEDA's project's homepage has moved. The new address is:
http://www.gpleda.org
I have moved most things except the mailing list archives
and the
Hi there,
Has something changed in the configuration of the git server in the
changes of the last week? I now cannot clone from the repo at one of my
machines:
gar...@xdcnb047-vbox:~/devel/temp$ !406
git clone http://git.gpleda.org/gaf.git
Initialized empty Git repository in
On Sat, 07 Feb 2009 20:11:09 -0500, Ales Hvezda wrote:
* The PCB project has also moved to using git.
Is gedasymbols.org going to switch to git, too?
---(kaimartin)---
--
Kai-Martin Knaak tel: +49-511-762-2895
Universität Hannover, Inst. für
Kai-Martin Knaak wrote:
Is gedasymbols.org going to switch to git, too?
DJ has some automation scripts creating user parts of gedasymbols.org, so it
would be an effort to change it.
Probably not worth the change effort for the minor developing done on symbols
and footprints.
Git may be more
Hello,
How coudl I select all pins ?
I try select by name, then pins, but it ask me for a pattern,
I try nothing or *
but I never been successfull.
Thank
--
---
==
Patrick DUPRÉ | |
Department of
Patrick Dupre wrote:
Hello,
How coudl I select all pins ?
I try select by name, then pins, but it ask me for a pattern,
I try nothing or *
but I never been successfull.
Don't know that. I use select by area with shift key so it adds to current
selected set.
JG
Is gedasymbols.org going to switch to git, too?
I have no plans to do so. CVS may be archaic, but it's plentiful and
low overhead.
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geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
On Mon, 09 Feb 2009 16:34:32 +, Patrick Dupre wrote:
How coudl I select all pins ?
I try select by name, then pins, but it ask me for a pattern, I try
nothing or *
Precede the asterisk with a full stop. The pattern
.*
will select all pins on the layout.
The pcb manual contains
I'm testing gnucap and cam across a desire to autogenerate symbols from
structural verilog module definitions.
Does anyone have a symbol generator ready to go from structural verilog to
gschem symbol?
The handy symbol-generation-from-shorthand scripts djboxsym and derived
jgboxsym assume
Hi Steve,
On Montag, 9. Februar 2009, steve tell wrote:
On Sun, 8 Feb 2009, Werner Hoch wrote:
thanks very much for the detailed report, and for the patch. I've
applied the patch, and plan to look at the runtime warnings soon.
Thanks.
If you have a tiny ngspice ascii rawfile that fails
I just put yet another pcb footprint generator on my homepage, see
http://www.ssalewski.de/SFG.html.en
It is similar to footgen.py of Darrell Harmon.
While making this generator I wrote a short summary of recent pcb
footprint format, available at
http://www.ssalewski.de/PcbFootprintRef.txt
The edge2 flag is not supported by my generator currently -- I have
never understood the correct use of this flag, and I have not seen any
result if I include it...
I suspect it's mostly used for the pinout window - it tells you which
way to orient the text, by keeping track of where the
Not completely satisfied with either my GL branch's translucent
rendering of layers, nor thindraw poly, I decided to make a hybrid..
http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png
The code to do this isn't yet in the GL branch (since it was a hideous
HID abstraction breaking hack at the
Hi guys,
I was just filing some things into my gEDA_screenshots directory, and
came across some .ogg screencasts which haven't really seen the light of
day. I made these rehearsing a screencast demonstration for an
undergraduate robot design course. I never did the real, mistake-free
screen-cast,
This is probably a Mike Jarabek question:
I don't get usable hierarchic netlist output when I have placed schematics and
use the gnet-verilog.scm back-end.
It drops the module definitions and endmodule statements of the placed symbols
that refer to schematics.
So, is that the normal behavior,
In some Xilinx models, they make instantiations like this:
block instance(ports);
defparam instance.param=VALUE
This normally works ok. The problem is that inside the block,
generate statements are being used which are dependent on the value of
the parameter. What appears to be happening is
[snip]
Has something changed in the configuration of the git server in the
changes of the last week? I now cannot clone from the repo at one of my
machines:
Yes, I made a change which affected http git access. I have
re-enabled git access via http. Please try again.
On Mon, 2009-02-09 at 19:25 -0500, Ales Hvezda wrote:
[snip]
Has something changed in the configuration of the git server in the
changes of the last week? I now cannot clone from the repo at one of my
machines:
Yes, I made a change which affected http git access. I have
re-enabled
Hi John,
There is a BASH script geda_hier_tools.bsh to generate
Hierarchical Verilog netlist with example that I posted last
month:
http://archives.seul.org/geda/user/Jan-2009/msg00056.html
Note that you need to have your gnetlistrc in each of those
Verilog project to contain:
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